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Title: Construction of Bipolar Transistor Logic Gate

In this experiment the objective is:
1) To build logic gates from bipolar transistors using the TL! "TL and TTL design#
$) To examine and compare the results of these technologies#
Theory and Methodology:
Resistor-Transistor Logic (RTL):
esistor%Transistor Logic &TL) is a large step be'ond "iode Logic &"L)# Basicall'! TL
replaces the diode s(itch (ith a transistor s(itch# If a )*v signal &logic 1) is applied to the base
of the transistor &through an appropriate resistor to limit base%emitter for(ard voltage and
current)! the transistor turns full' on and grounds the output signal# If the input is grounded &logic
+)! the transistor is off and the output signal is allo(ed to rise to )* volts# In this (a'! the
transistor not onl' inverts the logic sense of the signal! but it also ensures that the output voltage
(ill al(a's be a valid logic level under all circumstances# Because of this! TL circuits can be
cascaded indefinitel'! (here "L circuits cannot be cascaded reliabl' at all#
Diode-Transistor Logic:
"iode,Transistor Logic &"TL) is a class of digital circuits built from bipolar junction transistors
&B-T)! diodes and resistors. it is the direct ancestor of transistor,transistor logic &TTL)#
"TL offers better noise margins and greater fan%outs than TL! but suffers from lo( speed
&especiall' in comparison to TTL)#
TL allo(s the construction of /0 gates easil'! but /1/" gates are relativel' more difficult to
get from TL# "TL! ho(ever! allo(s the construction of simple /1/" gates from a single
transistor! (ith the help of several diodes and resistors#
Transistor-Transistor Logic:
2e can thin3 of a bipolar transistor as t(o diodes placed ver' close together! (ith the point
bet(een the diodes being the transistor base# Thus! (e can use transistors in place of diodes to
obtain logic gates that can be implemented (ith transistors and resistors onl'. this is called
transistor%transistor logic &TTL)#
0ne problem that "TL doesn4t solve is its lo( speed! especiall' (hen the transistor is being
turned off# Turning off a saturated transistor in a "TL gate re5uires it to first pass through the
active region before going into cut%off# Cut%off! ho(ever! (ill not be reached until the stored
charge in its base has been removed# The dissipation of the base charge ta3es time if there is no
available path from the base to ground# This is (h' some "TL circuits have a base resistor that4s
tied to ground! but even this re5uires some trade%offs# 1nother problem (ith turning off the "TL
output transistor is the fact that the effective capacitance of the output needs to charge up through
c before the output voltage rises to the final logic 414 level! (hich also consumes a relativel'
large amount of time# TTL! ho(ever! solves the speed problem of "TL elegantl'#
Pre-Lab Homework:
6xplain ho( n%p%n B-T transistors (or37
The /8/ transistor can be used in t(o different modes: for(ard biased mode and the
reverse biased mode# In for(ard biased mode! the electric current can easily flow through
it# 9o it acts li3e a CL096" 92ITC:# :o(ever! in reverse biased mode! the current
through it is practicall' ;ero and thus! it acts li3e an 086/ 92ITC:#
1) /8/ silicon transistor : $/<1$< = > pcs?
$) esistors : 1*@A! 1@A! <#B @A = 9ufficient no?
C) Connecting (ires# : 9ufficient amount

Instructor chec3ed all 'our connections after (e (ere done setting up the circuit and made sure
that (e appl' onl' enough voltage &(ithin D"") to turn on the transistors andEor chip! other(ise it
ma' get damaged#
Experimental Procedure:
1# The circuit for TL inverter as sho(n in Fig#$ (as set up#
$# For each input combination! the output (as found and placed them in a Truth Table#
C# 9teps 1 and $ (ere repeated for each circuit set%up from Fig#C to Fig# G#
uestions !or report writing:
1) For! each of the above set%ups! describe in (ords (hat the data means# "id 'our results match
the expected ideal outputs7 If not! explain (h'7
"# "esign TL and TTL <%input 0 gates#
TL < input 0 Gate
TTL < input 0 Gate
$# "esign $%input TTL /1/" and /0 gates#
$ input TTL /or done in Fig# $#G
0ur experimental value and expected values varied a little! this ma' be because the
s(itches (ere not providing exactl' *D# 1nother reason ma' be the drop across the
transistor junction (as not exactl' ideal#
1s our experimental data approx# matched (ith the ideal data! (e ma' conclude that that
circuits (e implemented gave the oEp of respective gates#
=1? Thomas L# Flo'd! Digital Fundamentals! Hth 6dition! $++G! 8rentice :all#