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Histogram method of testing ADCs for INL and DNL.

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Maxim > Design Support > Technical Documents > Tutorials > High-Speed Signal Processing > APP 2085

Keywords: code density test, histogram testing, ADC, high-speed data converter, integral nonlinearity,

INL, differential nonlienarity, DNL, sample record, code count, bin width, probability density function,

confidence level, hardware histogram

TUTORIAL 2085

Histogram Testing Determines DNL and INL Errors

Jun 18, 2003

Abstract: Also called code density test, the histogram test approach helps determine nonlinearity

parameters such as differential and integral nonlinearities (INL and DNL) in data converters. The

following application note lends insight into the mathematical relationship between probability density

function and various data converter specifications required to successfully complete the histogram test.

Histogram Testing Determines DNL and INL Errors

Today manufacturers of data converters frequently use the histogram method to verify the integral (INL)

and differential (DNL) non-linearity specifications of their data converters. This approach, also referred to

as code density test, is performed in the amplitude-domain of a data converter. During a histogram test

a repetitive, dynamic signal with a bathtub distribution (e.g. sine-wave signal) is applied to the analog-to-

digital converter (ADC), generating a corresponding distribution of digital codes at the output of the

converter. Any deviation from the corresponding output code distribution results in various errors that

may be estimated with the histogram method. These error parameters include first and foremost DNL

and INL.

For an ADC, given an analog input signal, the histogram shows how many times each different digital

code word appears on the ADC output. One method of histogram testing involves the sampling and

digitizing of a sinusoidal-input signal. The digitized information is then sorted into code bins. Each code

bin represents a single output code. Depending on the input signal, the number of samples, or hits for

each bin is collected. With N representing the ADC's resolution or total number of bits, there will be 2

N

code bins. For an ideal ADC, each code bin width should correspond to a bit width of FSR/2

N

, where

FSR is the full-scale range of the ADC in volts. In the real world however, code bin widths for ADCs may

not be the same. For instance, if the number of collected samples (for a known input signal) in a code

bin is greater than expected, than this number would indicate that the code bin width is larger than ideal

(statistically-speaking).

The frequency of code samples is displayed as a function of code. For an ideal ADC, this plot will be the

probability density function, p(V), of a sine wave represented as follows

p(V) =1 / ( [A - V])

Having established this mathematical relationship, the size of the sample array must be determined.

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But what size data record represents a statistically significant number of samples?

The probability density function will help answer this question. For a given probability density function

and data record size, each code bin of an ideal ADC identifies an expected number of samples and its

correlating standard deviation. The confidence that the number of samples in the code bin is close to the

expected level is equal to the probability that the samples fall within the appropriate number of

deviations. Note that the ratio between standard deviation and expected values decreases with an

increasing number of samples in the data record. To obtain a confidence level for the entire range, the

probability for all codes falling within the desired code are multiplied together.

To calculate the probability of each code for the recorded data array requires the number of samples for

each code to be divided by the number of samples in the data record. The ideal probability of samples is

what an ideal ADC would generate with a pure sine wave applied to the input of the converter.

Integrating the probability density function for a sine-wave-based input signal over the number of bins

allows the exact size of each code bin to be calculated as follows

P(n) =1/ [arcsin(FSR {n-2

N-1

}/ A 2

N

) - arcsin(FSR {n-1-2

N-1

}/ A 2

N

)],

where n represents the code bin number, FSR is the full-scale range and N is the resolution of the ADC.

The deviation between measured (actual) and ideal histogram at each output code is a function of the

code size, which can be used to determine the data converter's DNL. DNL can be computed as follows

DNL (LSB) =[AP(n

th

code) / IP(n

th

code)] -1

where n represents the code bin number ranging from 1 to 2

N

, N is the resolution of the ADC, AP(n

th

code) expresses the measured histogram of samples in code bin n and IP(n

th

code) is the ideal

(expected) histogram of samples in code bin n.

Unfortunately the histogram method requires the capture of fairly large data records. The number of

samples required is depending on the resolution of the ADC, the desired confidence level of the

measurement, and the size of the DNL error. For instance, a 10-bit ADC with a DNL error () of 0.1LSB

and a 95% confidence level (Z

/2

) requires more than half a million samples (N

RECORD

) to be recorded.

Boosting the confidence level from 95% to 99% will result in a significantly higher data record size of

more than one million samples.

N

RECORD

= 2

N-1

(Z

/2

)] / = 2

9

(1.96) / (0.1) =617,920

N

RECORD

= 2

N-1

(Z

/2

)] / = 2

9

(2.58) / (0.1) =1,070,678

As the resolution of the ADC increases, the number of required samples to satisfy confidence level and

error resolution multiplies by a factor of two for each bit added to the converter's resolution. For ADC

with 12 bits resolution and higher this test may eventually become the limiting factor in measuring DNL,

as it requires massive data storage capabilities to host the more than four million data points required.

Although an increase in record size and resolution leads to the undesired and cost intensive side effect

of prolonged lab and production test time, introducing a so-called hardware histogram generator can help

to reduce test time. Test time for such generators is defined as the ratio between record size and

sampling rate of the ADC.

Determining DNL through the histogram method can be challenging, as this test is sensitive to amplitude

variations of the input sine wave, noise, clock jitter and converter hysteresis. In this case the use of a

cumulative histogram test may be the better choice to calculate INL and DNL errors. To do that, the

offset and transition voltages for the ADC have to be determined. To find the offset error in the collection

of digitized data points, equate the number of positive and negative samples in the data records

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(N

RECORD

=N

RECORD[P]

+N

RECORD[N]

) as follows

2

N-1

N

RECORD[N]

= AP(n

th

code)

n=1

2

N

N

RECORD[P]

= AP(n

th

code)

n=2

N-1

+1

V

OFFSET

=0.5 A sin[(N

RECORD[P]

-N

RECORD[N]

) / (N

RECORD[P]

+N

RECORD[N]

)]

With the offset error calculated, the transition voltages or code edges (V

j

) can be found by using the

following mathematical expression

j

V

j

=-A cos [ ( AP(n

th

code) / N

RECORD

)]

n=1

With the transition voltages known, the calculation for INL and DNL parameters becomes independent

from the input amplitude of the sine-wave signal and can be calculated with the following formula

j

INL

j

(LSB) = DNL

j

(LSB)

n=1

DNL

j

(LSB) =(V

j+1

- V

j

) (2

N

/FSR)

where DNL

j

is the difference between two adjacent codes and INL

j

represents the sum of all DNL

j

errors. FSR is the full-scale range and N is the resolution of the ADC for which INL and DNL are

measured.

The following figures illustrate the histogram, INL and DNL performance of the MAX1193, an 8-bit, low-

power 45Msps ADC. In case of the MAX1193, INL and DNL tests were performed with a 5.6018MHz

sinusoidal input signal. Note that Figure 1 represents a histogram comparison between a sufficient and

insufficient number of code counts. Figure 2 and 3 depict the resulting DNL and INL performances

under these (sufficient and insufficient sample sizes) conditions.

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Figure 1. Sufficient Code Count vs. Insufficient Code Count Histogram Display for MAX1193.

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Figure 2. DNL Discrepancies for Sufficient Code Count vs. Insufficient Code Count - MAX1193.

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Figure 3. INL Discrepancies for Sufficient Code Count vs. Insufficient Code Count - MAX1193.

Matlab Code For Code Density Testing to Determine INL and

DNL

Downloadable Matlab source code example (M, 2KB)

%Code densi t y/ hi st ogr amt est t o cal cul at e I NL and DNL r equi r e a l ar ge number

of sampl es.

%St ep 1: Appl y a cl ose t o f ul l - scal e si ne wave ( but not cl i ppi ng) and f i nd

t he mi d- code

%f or t he appl i ed si gnal .

%St ep 2: Appl y t he same si ne wave i nput , but sl i ght l y l ar ger ampl i t ude t o

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cl i p t he ADC

%sl i ght l y.

%Run t he f ol l owi ng pr ogr am, ent er t he number of sampl es, r esol ut i on and mi d-

code f r om

%St ep 1and cont i nue.

%Copyr i ght Au/ Hof ner , Maxi m I nt egr at ed Pr oduct s, 120 San Gabr i el Dr i ve,

Sunnyval e,

%CA94086

%Thi s pr ogr ami s bel i eved t o be accur at e and r el i abl e. Thi s pr ogr ammay get

al t er ed

%wi t hout pr i or not i f i cat i on.

f i l ename=i nput ( ' Fi l e Name or pr ess ENTER f or Li st i ng Tr ansf er HP16500C: ' ) ;

i f i sempt y( f i l ename)

f i l ename = ' l i st i ng' ;

end

f i d=f open( f i l ename, ' r ' ) ;

numpt =i nput ( ' Number of Dat a Poi nt s? ' ) ;

numbi t =i nput ( ' ADC Resol ut i on? ' ) ;

mi d_code=i nput ( Ent er Mi d- Code ( Mean) : ' ) ;

f or i =1: 13, %Di scar d 13 l i nes of r edundant or header - r el at ed HP16500C dat a

f get l ( f i d) ;

end

[ v1, count ] =f scanf ( f i d, ' %f ' , [ 2, numpt ] ) ;

f cl ose( f i d) ;

v1=v1' ;

code=v1( : , 2) ;

code_count =zer os( 1, 2^numbi t ) ; %Code count

f or i =1: si ze( code) ,

code_count ( code( i ) +1) =code_count ( code( i ) +1) + 1;

end

%Rout i ne t o det ect whet her t he ADC' s i nput i s cl i ppi ng or not

i f code_count ( 1) == 0 | code_count ( 2^numbi t ) == 0 | . . .

( code_count ( 1) < code_count ( 2) ) | ( code_count ( 2^numbi t - 1) >

code_count ( 2^numbi t ) )

di sp( ' I ncr ease Si ne- Wave Ampl i t ude t o Sl i ght l y Cl i p t he ADC! ! ! ' ) ;

br eak;

end

A=max( mi d_code, 2^numbi t - 1- mi d_code) +0. 1; %I ni t i al est i mat e of act ual si ne wave

ampl i t ude

vi n=( 0: 2^numbi t - 1) - mi d_code; %di st ance of codes t o mi d code

si n2r amp=1. / ( pi * sqr t ( A^2*ones( si ze( vi n) ) - vi n. *vi n) ) ; %si n2r amp*numpt i s t he

expect ed

%Count each code; keep i ncr easi ng est i mat e of A unt i l t he act ual t ot al number

of count s f r om

%code 1 t o 2^numbi t - 2 mat ches wi t h t hat pr edi ct ed by si n2r amp*numpt

whi l e sum( code_count ( 2: 2^numbi t - 1) ) < numpt *sum( si n2r amp( 2: 2^numbi t - 1) )

A=A+0. 1;

si n2r amp=1. / ( pi * sqr t ( A^2*ones( si ze( vi n) ) - vi n. *vi n) ) ;

end

di sp( ' You Have Appl i ed a Si ne Wave of ( dBFS) : ' ) ;

Ampl i t ude=A/ ( 2^numbi t / 2)

f i gur e;

pl ot ( [ 0: 2^numbi t - 1] , code_count , [ 0: 2^numbi t - 1] , si n2r amp*numpt ) ;

t i t l e( ' CODE HI STOGRAM - SI NE WAVE' ) ;

xl abel ( ' DI GI TAL OUTPUT CODE' ) ;

yl abel ( ' COUNTS' ) ;

axi s( [ 0 2^numbi t - 1 0 max( code_count ( 2) , code_count ( 2^numbi t - 1) ) ] ) ;

code_count n=code_count ( 2: 2^numbi t - 1) . / ( numpt *si n2r amp( 2: 2^numbi t - 1) ) ; %End

poi nt s di scar ded!

f i gur e;

pl ot ( [ 1: 2^numbi t - 2] , code_count n) ;

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t i t l e( ' CODE HI STOGRAM - NORMALI ZED' )

xl abel ( ' DI GI TAL OUTPUT CODE' ) ;

yl abel ( ' NORMALI ZED COUNTS' ) ;

dnl =code_count n- 1; %DNL=Vj +1- Vj - 1LSB wher e Vj r epr esent s a t r ansi t i on

poi nt

%Vj +1- Vj i s pr opor t i onal t o nor mal i zed code count

i nl =zer os( si ze( dnl ) ) ;

f or j =1: si ze( i nl ' )

i nl ( j ) =sum( dnl ( 1: j ) ) ; %I NL, j =DNL, 0+DNL, 1+. . . +DNL, j

end

%I NL st i l l cont ai ns t he of f set and gai n er r or ! ;

%I NL wi t h end- poi nt s f i t , i . e. I NL=0 at end- poi nt s t he st r ai ght l i ne j oi ni ng

t he 2 end poi nt s

%[ p, S] =pol yf i t ( [ 1, 2^numbi t - 2] , [ i nl ( 1) , i nl ( 2^numbi t - 2) ] , 1) ;

%t he best - f i t st r ai ght l i ne

[ p, S] =pol yf i t ( [ 1: 2^numbi t - 2] , i nl , 1) ;

i nl =i nl - p( 1) *[ 1: 2^numbi t - 2] - p( 2) ;

di sp( ' End Poi nt s El i mi nat ed f or DNL and I NL Cal cul at i ons' ) ;

f i gur e;

pl ot ( [ 1: 2^numbi t - 2] , dnl ) ;

gr i d on;

t i t l e( ' DNL' ) ;

xl abel ( ' DI GI TAL OUTPUT CODE' ) ;

yl abel ( ' DNL ( LSB) ' ) ;

f i gur e;

pl ot ( [ 1: 2^numbi t - 2] , i nl ) ;

gr i d on;

t i t l e( ' I NL ( BEST END- POI NT FI T) ' ) ;

xl abel ( ' DI GI TAL OUTPUT CODE' ) ;

yl abel ( ' I NL( LSB) ' ) ;

Footnotes

1. V=Asin[t], where V represents the independent variable (in this case a voltage) and A is the

amplitude of the sine wave.

2. An ideal histogram is the probability of code within a given bin multiplied by the number of samples

in the record.

3. The confidence level is the probability value (1-) associated with a confidence interval. The

confidence level is usually expressed in percent. For instance, if =1% then the confidence level is

equal to 1 - 0.01 =0.99 or 99% confidence level.

The confidence level values used in the NRECORD calculation originate from Table 2 of the IEEE

Standard 1241 Draft, printed on May 12th, 1997 - Standards for Terminology and Test Methods for

Analog-to-Digital Converters Prepared by the Analog-to-Digital Converter Subcommittee of the

Waveform Measurements and Analysis Committee of the IEEE Instrumentation and Measurement

Society

4. The cumulative histogram is a variation of the commonly used histogram. In the cumulative

histogram, the y-axis does not only provide the sample counts for a single code bin, but rather

displays the sample counts for that code bin plus all code bins for smaller values.

Additional Information: INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)

Related Parts

MAX1191 Ultra-Low-Power, 7.5Msps, Dual, 8-Bit ADC Free Samples

MAX1192 Ultra-Low-Power, 22Msps, Dual 8-Bit ADC Free Samples

Page 8 of 9

MAX1193 Ultra-Low-Power, 45Msps, Dual 8-Bit ADC Free Samples

More Information

For Technical Support: http://www.maximintegrated.com/support

For Samples: http://www.maximintegrated.com/samples

Other Questions and Comments: http://www.maximintegrated.com/contact

Application Note 2085: http://www.maximintegrated.com/an2085

TUTORIAL 2085, AN2085, AN 2085, APP2085, Appnote2085, Appnote 2085

Copyright by Maxim Integrated Products

Additional Legal Notices: http://www.maximintegrated.com/legal

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