VHDL Reserved Words

abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic group guarded if impure in inertial inout is label library linkage literal loop map mod nand new next nor not operator, absolute value of right operand. No () needed. used to define an access type, pointer specifies a time after NOW create another name for an existing identifier dereferences what precedes the .all operator, logical "and" of left and right operands a secondary design unit used to define an array, vector or matrix used to have a program check on itself used to declare attribute functions start of a begin end pair start of a block structure designates a procedure body rather than declaration a mode of a signal, holds a value a mode of a signal, can have multiple drivers part of a case statement starts the definition of a component a primary design unit declares an identifier to be read only signal driver condition middle of a range 31 downto 0 part of "if" statement, if cond then ... else ... end if; part of "if" statement, if cond then ... elsif cond ... part of many statements, may be followed by word and id a primary design unit sequential statement, used in loops used to declare a file type start of a for type loop statement starts declaration and body of a function make copies, possibly using a parameter introduces generic part of a declaration collection of types that can get an attribute causes a wait until a signal changes from False to True used in "if" statements an impure function is assumed to have side effects indicates a parameter in only input, not changed signal characteristic, holds a value indicates a parameter is used and computed in and out used as a connective in various statements used in attribute statement as entity specification context clause, designates a simple library name a mode for a port, used like buffer and inout used in attribute statement as entity specification sequential statement, loop ... end loop; used to map actual parameters, as in port map operator, left operand modulo right operand operator, "nand" of left and right operands allocates memory and returns access pointer sequential statement, used in loops operator, "nor" of left and right operands operator, complement of right operand

null of on open or others out package port postponed suspend procedure process pure range record register reject rem report return rol ror select severity signal shared sla op sll sra srl subtype then to transport type unaffected units until use variable wait when while with xnor xor

sequential statement and a value used in type declarations, of Real ; used as a connective in various statements initial file characteristic operator, logical "or" of left and right operands fill in missing, possibly all, data indicates a parameter is computed and output a design unit, also package body interface definition, also port map make process wait for all non postponed process to typical programming procedure sequential or concurrent code to be executed a pure function may not have side effects used in type definitions, range 1 to 10; used to define a new record type signal parameter modifier clause in delay mechanism, followed be a time operator, remainder of left operand divided by right op statement and clause in assert statement, string output statement in procedure or function operator, left operand rotated left by right operand operator, left operand rotated right by right operand used in selected signal assignment statement used in assertion and reporting, followed by a severity declaration that an object is a signal used to declare shared objects operator, left operand shifted left arithmetic by right operator, left operand shifted left logical by right op operator, left operand shifted right arithmetic by right operator, left operand shifted right logical by right op declaration to restrict an existing type part of if condition then ... middle of a range 1 to 10 signal characteristic declaration to create a new type used in signal waveform used to define new types of units used in wait statement make a package available to this design unit declaration that an object is a variable sequential statement, also used in case statement used for choices in case and other statements kind of loop statement used in selected signal assignment statement operator, exclusive "nor" of left and right operands operator, exclusive "or" of left and right operands