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IEEE WG15.08.09 Draft Document.
Modeling and Transient Simulation

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IN ELECTRIC POWER ENGINEERING APPLICATIONS

Report Prepared by the Power Electronics Task Force

of the IEEE Modeling and Analysis of System Transients Working Group

Contributing Authors: K. K. Sen (Co-Chair), L. Tang (Co-Chair), H. W. Dommel, K. G. Fehrle, A. M. Gole,

E.W. Gunther, I. Hassan, R. Iravani, A. J. F. Keri R. Lasseter, J. R. Marti, J. A. Martinez, M. F. McGranaghan,

O. B. Nayak, C. Nwankpa, P. F. Ribeiro

many power system engineers. This guideline provides general procedures to help these engineers to make their own

simulation cases as needed. The theories of power electronics are not in discussion. Attention is focused on the simulation of the interaction between the power electronic

subsystem and the connected power system. Thus, a model

for a power electronic switching device can be greatly simplified. Detailed descriptions about the device representation are presented in the later section of this paper. In the

last section of the paper, the references related to various

power electronics simulations are listed.

guidelines for modeling power electronics in various power

engineering applications. This document is designed for use by

power engineers who need to simulate power electronic devices

and subsystems with digital computer programs. The guideline

emphasizes the basic issues that are critical for successful modeling of power electronics devices and the interface between

power electronics and the utility or industrial system. The modeling considerations addressed in this guideline are generic for

all power electronics modeling independent of the computational tool. However, for the purposes of illustration, the simulation examples presented are based on the EMTP or EMTP

type of programs. The procedures used to implement power

electronics models in these examples are valuable for using

other digital simulation tools.

ELECTRONICS MODELING

2.1. Types of Problems

Power electronics modeling can be divided into

two basic categories, depending on study objectives. The

first category covers all steady state evaluations. The focus

is from the power system response to the harmonics injected

from a power electronics subsystem. Examples of this type

include a study of the steadystate harmonic propagation in a

transmission and distribution system, harmonic frequency

resonance, system voltage and current distortion, filtering

design calculation and performance evaluation, telephone

interference analysis and system losses associated with harmonics. In this type of study, the harmonic current injection

can often be assumed independent of the voltage variations

at a point of common coupling (PCC) which is an electrically dividing point between the utility system and the customer circuit. Therefore, the power electronics subsystem

can greatly be reduced to a shunt circuit equivalent.

1. INTRODUCTION

As a consequence of the advances in power electronics technologies over the last two decades, power electronics applications have quickly spread to all voltage levels,

from EHV transmission to low voltage circuits in end user

facilities. Commonly observed power electronics applications include HVDC terminals, various static var compensation (SVC) systems, high power AC to DC converter for DC

arc furnaces, static phase shifter, isolation switch, load transfer switch, converter/inverter based drive technologies,

active line conditioning, energy storage and instantaneous

backup power systems, renewable energy integration, and

numerous others covered under subjects of Flexible AC

Transmission Systems (FACTS) and Custom Power Systems

(CPS). The need for power electronics modeling and simulation is driven by both existing and new applications.

covers a much more extensive and complex range of practical problems. In many applications, operation of a power

electronics subsystem depends closely upon the operation

state of the connected system. To evaluate the dynamic and

transient performance of a system with power electronics

interfaces, the monitoring and control loops of the system,

including detailed signal processing and power electronics

device firing need to be modeled. Examples of this type of

applications can be a SVC system, a Superconducting Magnetic Energy Storage (SMES), active power conditioning

system and various adjustable speed drives applications.

verification of an application design

prediction the performance of a system

identification of potential problems

evaluation of possible problem solutions.

The simulation is specially important for a concept validation

and design iteration during a new product development.

Power electronics applications are relatively new to

2-1

interest of the study is overall system dynamics and transients. In such cases, the EMTP type programs are usually

more suitable tools. The currently available versions of the

EMTP type programs may be less efficient for detailed

power electronics modeling. However, these programs are

very attractive for an application oriented power electronics

simulation because these programs offer tremendous capability and flexibility in characterizing various types of power

system components, including power electronics switches

with reasonably simplified characteristics. As graphic interfacing features are gradually incorporated in these programs,

a level of difficulty in using these tools will decrease.

parameters need to be used to derive the power electronic

controls so the output of the power electronics subsystem

changes accordingly as demanded. Since a power electronics

subsystem directly affects overall system operation, a comprehensive treatment of the supply system and the power

electronics subsystem should be performed.

2.2. Frequency Domain and Time Domain Simulation

The solution methods are considered from two basic approaches:

1.

2.

time domain solution.

3. MODELING GUIDELINES

Digital computers can only simulate circuit phenomena at discrete frequencies or at discrete intervals of time

(step size (f or (t). This leads to truncation errors in all digital

simulations. Compared with the time domain calculation, a

frequency domain simulation is more robust because a circuit

solution is found at each individual frequency and truncation

errors are not accumulated. The programs using this solution

method often treat the nonlinearity of a system as known current sources. For a harmonic evaluation, the frequency

domain solution usually requires less computation time compared with a time domain solution. However, most available

frequency domain solution programs have difficulties in handling the system dynamics, control interfaces and fast transients. The time domain solution is based on the integration

over a discrete time interval. The numerical methods applied

in different programs can use either iterative techniques or

direct solution methods. The solution stability and accuracy

achieved are closely related to the time step size selection.

Because truncation errors can accumulate from step to step,

the solution m ay diverge from the true solution if an

improper time step is selected. The time domain simulation

has great advantages over a frequency domain simulation in

handling the system dynamics, power electronic interface

and transients.

For a power level application, the commonly used

switching devices are power diode, Silicon Controlled Rectifier (SCR), Gate Turn-Off thyristor (GTO) and Insulated

Gate Bipolar Transistor (IGBT). The diode is a two-terminal, uncontrollable device and the rest are three terminal controllable devices.

Representing the reverse recovery characteristic,

leakage current, and forward voltage drop of a diode is often

not necessary for an application study. For an application

simulation, some details of a device characteristic can be

reduced. In many cases, a simplified device model is acceptable. For example, instead of trying to represent a power

electronic diode device using its switching characteristic as

shown on the left in Fig. 1, a simplified or an idealized characteristic, shown by solid and dotted lines respectively on the

right, can be used. In commonly used simulation programs,

the simplified diode model may be available as a built-in

device or it can be realized with a voltage controlled switch.

I

Simulated Device

Characteristic

Real Device

Characteristic

V

tools for power electronics related simulations can be classified into three groups:

1. Power electronics simulation tools

2. General transients simulation tools or EMTP type of

programs

3. General harmonics simulation tools or frequency

domain simulation tools.

Cathode

Anode

its characteristic can be realized using a voltage controlled

unidirectional current flowing switch with a specified conducting voltage threshold, Vs, as shown in Fig. 2.

The tools of the first group may offer the best productivity if a detailed application topology and complicated

operation controls need to be simulated and if the main interest of the study is the power electronics subsystem. These

tools often have difficulties when an extensive utility net2-2

For numerical simulations, if the gating circuit power requirement is excluded from the study, there is very little difference

between modeling a GTO, IGBT or any other three-terminal,

controllable, unidirectional current flowing device. The device can all be represented by an simplified switch with gate

turn-on and turn-off controls. The different switching characteristics can be realized by applying different firing controls.

Vs

Conducting when V>Vs

a continuous current flowing path for an inductive load, a reversal diode (free wheeling diode) is used in parallel with a

controllable switching device to form the basic power electronics switching unit. However, several alternatives are

available for implementing this basic switching unit in digital

simulations.

specify on-state and off-state resistances, the device can be

realized using two above described switches connected in

parallel (Fig. 3) with the opposite polarities and different

conducting voltage thresholds when loss calculation is of

interest. To include losses, the resistors Rf and Rb can be

inserted in series with the forward and backward current

flowing switches respectively, and a leakage resistor Rl can

be connected crossing the terminals of the switch branches.

point of the application, the simplest model that can be used

to present one leg of the bridge rectifier or inverter can be constructed with one simplified bi-directional current flowing

switch with gate controls as shown in Fig. 5 (1). This model

V

Anode

Cathode

Vsf

Rf

Rb

Vsb

Gate

(1)

(2)

(3)

Rl

uses the least number of devices for a given power

electronics topology. The problem with this bidirectional current flowing switch representation is that it fails to correctly

represent an operation state during the idling period. This

can be better explained with an example of a simplified

inverter scheme used in a UPS as shown in Fig.6.

The switching characteristics of an actual, a simplified and an idealized SCR are shown in Fig. 4. To represent

the simplified SCR device, the turn-on control is added on

the simplified diode model. If the control is applied continuously, this switch simulates the diode which allows unidirectional current flow when the switch is forward biased.

Delaying the gate pulse allows control over the turn-on

instant of the forward biased switch.

'&

%DWWHU\

AC

6XSSO\

Simulated Device

Characteristic

Real Device

Characteristic

Ig1 Ig0

Vbo

Cathode

blocked, the DC battery charges through the rectifier bridge

consisting of six reversal diodes. However, if the ideal bidirectional switches are used, while the UPS is idling, the battery will not be charged by the AC supply.

Anode

Device

2-3

represented, the simple bidirectional device model can be

improved with a parallel reversal diode as shown in Fig. 5

(2). When the terminal effects as well as the individual

device current carrying conditions are of interest, a further

improvement on the model can be made by adding another

diode as shown in Fig. 5 (3).

DC R and L

Voltage

Source

switch connections on the same circuit node can lead to a singular system admittance matrix. When using a program with

such restriction, a small series resistor or inductor can be

used to create intermediate nodes and avoid the problem.

GTO

Load

To Firing Control

Fig. 8. An Example Circuit to Show GTO Simulation.

the gating signal is greater than zero, the GTO is turned on

and when the gating signal is equal to zero, the GTO is

turned off. The GTO is initially open. The current flowing

through the GTO and voltage across the load resistor after

t=0 are illustrated in Figs. 10 and 11 respectively. By controlling the GTO firing, the average output voltage at the load

terminal can be regulated.

an EMTP example of a GTO operation is given below. In

this example, a GTO module is built with a controlled bidirectional current flowing switch (type-13 switch) in series

with a built-in diode device (type-11 switch). Considering

the GTO is often utilized in applications with a reactive

power carrying capability, a reversal diode (free wheeling

diode) has been included. The schematic of the module connection is shown in Fig. 7. A list of the module file is given

in Appendix A. Note that although it has not been shown in

Fig. 7, some small resistors are used to introduce intermediate nodes between the EMTP switches and snubber elements

are used in this GTO module.

type-13

switch

Fig. 9. The GTO Firing Signal.

type-11

switch

An example circuit given in Fig. 8 is used to illustrate how this module is used in a circuit simulation. In this

example, the GTO device is used to regulate the voltage at a

resistive load terminal. By controlling the GTO tuning-on

and off, the average voltage across the resistor can be

adjusted.

2-4

If every individual power electronic switching

device is represented, a system model containing power electronic applications can easily reach a complication level that

is difficult for implementation. For an example, a HVDC terminal contains tens to hundreds series and parallel SCR

devices in one converter leg for high voltage and MVA ratings. Obviously, if one wants to represent each individual

SCR device in this HVDC system model, one will have to

build a very large model.

With these general guidelines, a voltage source converter model for a system dynamic evaluation can be built as

shown in Fig. 12. Irrespective of how many series and parallel GTO devices are used in an actual application, only two

GTO devices are used in each phase of the model to form a

converter leg. In this example, the just discussed GTO module is used as a building block to construct the converter

module.

Fortunately, (except for some failure mode analyses), for the purposes of most application simulations it is not

necessary to represent all individual devices. Usually, what

needs to be simulated is the terminal characteristics of a

power electronic subsystem and how it interfaces with the

connected system. Thus, the following procedures can be

used to reduce the modeling complexity:

Use one or a few equivalent devices to represent series

and parallel combination of a group of devices

Represent power electronic loads with similar characteristics by an equivalent load

Use the simplest device model which is appropriate for

the application

Represent a power electronic subsystem by equivalent

source injection whenever it is acceptable

Represent only the front end of the drive system when

the major concern is utility interfacing

Include the system dynamic and controls only when necessary

Use modular approach for large scale model development

The GTO firing control signals for the six-step operation is given in Fig. 13. The firing signal for the switching

cells No. 1 through No. 6 are shown in this figure by the

traces with the magnitude 1.1 through 1.6 respectively. The

device firing starts when the time reaches one 60 Hz cycle

ending point. When the gating signal is greater than zero, the

corresponding GTO device is turned on. When the gating

signal is equal to zero, the device is turned off. The resulting

line-to-neutral and line-to-line output voltages are illustrated

in Figs. 14 and 15, respectively.

Fig. 13. The GTO Firing Signal for the Six Step Converter Operation

2-5

Fig. 14. Six Step Operation Line-to-Neutral Voltage

Fig. 15. Six Step Operation Line-to-Line Voltage

applying these system reduction are presented. Some important issues addressed are:

derived by comparing the saw tooth carrier signal with a reference signal of a desired frequency of that phase. As shown

in Fig. 16, whenever, the instantaneous value of the reference

signal is greater than that of the carrier signal, the device is

turned on.

Harmonic cancellation when multiple loads are represented by their lumped equivalent

Existing system distortion.

Appropriate source topology for PE subsystem representation

System unbalance

Effects of a DC link or the inverter side connection on

the front end interface with the power supply system

Current or voltage sharing among the parallel or series

switching devices

Switching loss prediction

Similar to the situation in a power electronics subsystem, a power supply system can easily extend to a large

electrical and geographic radius and become too complicated

to model. Therefore, the power system needs to be simplified. The proper level of system reduction depends on the

study objectives.

Hz, Carrier Signal Frequency = 600 Hz

voltages are shown in Figs. 17 and 18, respectively. By

changing the magnitude and frequency of the reference signal, the output voltage magnitude and frequency can be

changed. The carrier frequency determines the characteristic

harmonic components of the output voltage.

If the purpose is to characterize the harmonics generated by a particular type of power electronics application,

the power system model can be significantly reduced. When

a pre-existing voltage distortion level at a power electronics

interfacing bus is low, the rest of the power system can be

2-6

satisfactorily represented by one or a set of first order equivalents connected to the bus at a higher system voltage level.

For an example, if the power electronics application interfaces with the system at the low voltage bus of a step-down

transformer, the equivalent of the system can be placed on

the high voltage bus of the transformer. When a pre-existing

voltage distortion level is greater than 2%, one needs an adequate harmonic source to properly represent the background

distortion.

electronics on a connected utility system, the model shall be

extended to cover all sensitive loads (i.e. rotating machines

and all other major power electronics) within a concerned

electrical radius. Special attention is needed if an unbalanced system condition is involved.

Extensive power system model is required for a harmonic propagation and resonant study. The main system

components and dominant topology need to be kept in the

power system model. Filter banks, nonlinear passive circuit

components, and all other harmonic injection sources should

be represented. Frequency dependent characteristics of the

system components might need to be considered.

3.4. Representation of System Controls

aspect of a power electronics simulation. As illustrated in

this paper, a switching device is greatly simplified. The

proper switching performance of a device is realized via

appropriate gate controls. Modeling of power electronic controls consists of three steps:

1. Monitoring and sampling

2. Signal processing and control reference derivation

3. Device gating signal generation.

Most simulation tools provide some means to

implement system controls. In some later developed programs, the control block diagram and flow-chart structures

are supported for modeling different levels of system controls. Using these tools, a user can define the specified controls in a simulated system with great flexibility. Some key

issues ensuring a correct control modeling is briefly mentioned below. These issues are more thoroughly treated in

the guideline with illustration examples.

For a time domain simulation, the highest resolution for

a signal sampling is determined by a selected time step.

In general, this presents no problem for analog control.

However, for digital control simulation, if the selected

time step is too large and if the simulated sampling resolution is significantly different from the real system sampling resolution, significant errors can be introduced and

even lead to instability.

For a time domain simulation, the computation time

does not reflect the simulated control logic response

time. User should always remember to introduce a rea-

control hardware and software.

When modeling a control response, it is important to

understand the program introduced time delay between

the primary system and the control interface. For an

example, the control model may introduce one or more

time step delay because of structure and solution method

of the program. This may not cause problems in some

simulations. However, if the modeled control logic

makes this time delay caused error to accumulate over a

period of time, it can eventually result in the solution

divergence. The problem can be corrected in most cases

by reducing the size of the time step or avoiding the possible accumulation mechanism in the control model.

Different methods may be used to synchronize power

electronics gating signals with required system references. In many cases, a real phase-locked-loop (PLL)

can be greatly simplified to reduce the modeling system

complexity. However, when the system contains significant waveform distortions, either harmonics or transient

disturbances, a practical PLL with all signal filters

should be carefully implemented in the control model in

order to accurately predict control response. This is particularly important when the objective of the simulation

is to verify control design and to evaluate the response of

a power electronic application to primary system dynamics.

All power electronic devices have their limit in switching frequency. When a load commutation or a standard

PWM type scheme is simulated, the highest switching

frequency in the simulation is controlled by the system

frequency or by a carrier frequency. Even considering a

variable carrier frequency, the number of switching per

fundamental frequency cycle is known and the highest

switching frequency can be made under a physical limit

of the simulated device. However, if the device firing is

determined by a simple comparison between the system

control reference and the system output, a device switching may take place in simulation whenever a comparison

difference is detected. Therefore, the switching frequency becomes highly dependent on the time step size,

and the average switching frequency becomes unpredictable. When using this type of firing logic, user should

always take extra measures, such as introducing a hysteresis loop, to ensure that the modeled device is working under its physical switching capability.

shown in Fig. 20. The system voltage at the terminal of the

load is sampled and used to generate the synchronous reference signal. From Fig. 21 through Fig. 26, the input, intermediate output quantities and output signal are plotted to show

the each step of this signal processing.

2-7

Uref

Vsyn

Va

Vd

ABC

COS()

Vb

VCO

PI

Vc

Vq

DQ

Uref

SIN()

RESET

Fig. 24 Derived Frequency Reference

disturbance is illustrated in Fig. 27. A balanced system fault

is placed on and removed from the system, resulting a three

cycle voltage sag.

Three phase fault

Rf=0.01 ohms

Tin=0.025s

Tcl=0.075s

Kpro = 100

Kint = 8.3E-3

Fig. 23 Derived Phase Error

PLL about three cycles to be relocked into the system voltage.

2-8

engineer. Otherwise, some of the measures listed later in this

section may have to be implemented to obtain correct results.

The finite nature of the simulation time step that the

EMTP type programs use also poses another problem for

power electronic circuit simulation which necessitates the

use of snubber circuits across fast acting power electronic

switches. Note that in some situations the snubber R and C

values of the actual system may or may not work in simulations using some programs. In this case, the R and C values

of the snubbers needed for stable simulation is primarily

dependent on the time step and secondarily on system configuration (capacitors and inductors in the system) and the load

current level. Programs using special features such as variable time steps (very short time steps during switching) or

interpolate switching (simulate the switching very close to

the required instant using linear interpolation between time

steps) do not require fictitious snubber circuits. Therefore,

one of the following measures or their combinations can be

taken to prevent numerical instability in the simulation:

Select a smaller time step

Use artificial snubber circuits

Introduce a small smoothing reactor for DC links

Introduce proper stray capacitances in the system model

Provide a parallel damping for lumped system.

given values to the values listed below, for the same system

and fault, one can observe that the same PLL logic can be

relocked into the system voltage within a half cycle period of

the time as shown in Fig. 28.

Three phase fault

Rf=0.01 ohms

Tin=0.025s

Tcl=0.075s

With Modified:

Kpro = 1000

Kint = 8.3E-4

three terminal, controllable power electronic device with

snubber connections is shown in Fig. 29. An actual snubber

configuration can be different from one application to

another. However, if the purpose of a simulation is not to

design the snubber, a sample snubber configuration shown in

this figure can often provide satisfactory results.

ATRMNL

GTRMNL

SNUBBR

SNUBBC

three phase to DQ transformation is valid for three-phase balanced application. Also, its performance characteristic is

highly affected by the parameter settings.

SNUBBR

SNUBBC

CTRMNL

The simulation programs using trapezoidal integration method are inherently prone to spurious oscillations

(also known as chatter) in capacitive and inductive circuits

when subjected to sudden changes such as step change in

voltage, current injection and switching. Some EMTP type

programs take special measures to detect and remove these

2-9

AC Supply

System

through the following sources:

1. switching device approximation and system reduction

2. added circuit elements for numerical oscillation control

3. control system simplification

4. time step related truncation

5. program structure and solution method introduced interfacing time delay

6. incorrect system initial conditions

For application simulations, some errors resulting

from the system simplification and measures of numerical

oscillation control are acceptable. The fourth and fifth items

in the list can be controlled by reducing the time step size. A

recommended time step size should not be greater than 1/5 to

1/20 of the period of the highest concerned frequency

cycle. For an example, for an IGBT inverter simulation with

5000Hz PWM switching, a selected time step could be 10

ms. However, if the objective of the simulation is to see the

detailed transient at the terminal of the induction motor

which is fed by the inverter through a section of the cable

with an 1.0 ms travel time, an adequate time step should be

0.2 ms or smaller.

DC Link

Induction

Motor

IM

Six Pulse

Diode Rectifier

PWM

Inverter

Drive

front end rectifier. The same switching devices with added

open/close controls are used to represent output inverter

IGBTs. The EMTP input data modules are use to build this

example case. Both the output reference frequency and the

PWM carrier frequency are made to be controllable. Modeling of a signal processing and firing pulse generation is illustrated in this example. The motor load of the drive is

represented by its R+jX equivalent branch. The simulated

AC input current, carrier and reference signal for the PWM

control, AC output voltage and current are presented in Fig.

31 through Fig. 33.

can be reduced by just letting the simulation run for a period

of time to reach a corrected initial condition. This may take

more computing time, but time is saved in model construction, especially if the program allows to restart. There are

some methods developed which help to accelerate the system

into the correct initial condition quickly.

4. SUMMARY OF DOCUMENTED EXAMPLES

Summary of simulation examples on PWM Voltage

Source Inverter Adjustable Speed Drive, Voltage notching

caused by operation of Current Source Inverter, HVDC terminal and shunt TSC/TCR compensation, modeling of rotating machines and a comprehensive treatment on the voltage

source inverter based FACTS devices and its modeling techniques using EMTP are presented in this section. The examples can be either a real case study or an exercise for

illustration purposes.

Speed Drive

4.1. Simulation of the Pulse Width Modulation (PWM) Voltage Source Inverter (VSI) Adjustable Speed Drive (ASD)

The first example is a PWM-VSI AC drive simulation using EMTP. The AC drive (Fig. 30) consisting of a

three-phase diode bridge rectifier, capacitive DC link and

three-phase PWM output inverter. The switching losses of

the drive are a secondary order consideration in the analysis

and the idealized switching characteristics are used.

Fig. 32. Simulated Carrier and Reference Signals for A PWM- VSI

Adjustable Speed Drive Firing Control

2-10

74 MVA

144 kV

10 MVA

7.87%

25 kV Bus

2 km 266 MCM

7.5 MVA

5.75%

Adjustable Speed Drive

ASD

harmonic

filters

5,7,11

Current Source Inverter (CSI) ASD

The second example is based on a case study. The

involved system is illustrated by the one line diagram in Fig.

34. The 35 kV distribution system is supplied through a 10

MVA transformer from the 144 kV transmission system. The

customer causing the voltage notching problem has a 6000

hp induction motor supplied through a CSI adjustable speed

drive[53]. This drive is at a 4.16 kV bus supplied through a

7.5 MVA transformer. Harmonic filters (5th, 7th, 11th) are

included to control the lower order characteristic harmonics

of the six pulse drive. The actual adjustable speed drive and

motor load were represented to reproduce the notching oscillations observed in the measurements.

6000 hp

other

loads

1500 kVA

4.7%

1500 kVA

4.7%

4.16 kV

Motor Load

(650 hp)

0.5 uF

surge capacitors

PF Correction

Capacitors

(160 kvar)

800 hp

in significant oscillations on the 25 kV supply system. These

oscillations caused clocks to run fast at the customer with the

6000 hp motor (clocks were fed separately from the 25 kV

system) and failure of surge capacitors on the 800 hp motor

at the customer located on the parallel feeder. The objective

of the simulation is to identify the power quality problem

associated with this 6000 HP CSI ASD operation. The simulation was carried out using EMTP.

The worst notching problems are associated with a

firing angle at about 70% load. The simulated waveform for

the 25 kV bus voltage is shown in Fig. 35. The oscillations at

each commutation point are in good agreement with the measurement results.

other

loads

4.16 kV

10 km

1/0

Fig. 34. One line diagram for the first example system.

kV bus where the 800 hp motor surge capacitors cause magnification of the oscillations. The potential for problems at

this location is quite evident.

2-11

(SVC+SC).

Fig. 38 shows the typical results obtained from the

simulation for a permanent DC block. The fixed compensator case does not control the overvoltage; however, all other

options do. The SVC option is the fastest to respond followed by the SVC+SC option and lastly the SC option. This

simulation setup can be used to conduct almost any type of

performance study including a thyristor miss-fire in HVDC

valve group or in the SVC itself.

Fig. 36. Simulated waveform at surge capacitor location (4.16 kV

bus of customer on parallel feeder)

Compensation

The third example is an illustration case for modeling of an HVDC system with shunt TSC/TCR compensation

at the inverter bus [54]. The simulation example is made

using PSCAD/EMTDC. The schematic system shown in

Fig. 37 is a modified version of the GIGRE Benchmark

Model for HVDC Control Studies [55].

The inverter short circuit ratio has been reduced

from its original value of 2.5 to 1.5 to make the study more

interesting. The DC link is a 1000MW, 500kV, 12 pulse

monopolar system. There are damped low and high pass filters at each converter terminal to reduce the distortion on the

AC bus. The control scheme for the HVDC system consists

of a rectifier current controller with the gamma controller.

Fig. 38 Inverter AC Voltage Following a Permanent DC Block

1000 MW

500kV

12 Pulse

Rectifier AC

System

Two possible situations can be considered for modeling a rotating machine when simulating a power electronic

system

1. The machine is a component of a larger system where

one or several power electronic devices are operating,

for instance a synchronous machine connected to a

transmission network where FACTS devices are used to

control power flows and improve transient stability.

2. The machine is part of the power electronic system, for

instance an adjustable speed drive.

Inverter AC

System

12

12

Filters

FC

Rectifier

Inverter

Filters

FC,SC

SVC

TCR and TSC (two stage) combination connected to the

inverter bus through a step up transformer. The SVC controls are designed to coordinate the control of TCR and TSC

in such a way that the combined susceptance of the SVC is

continuous over its entire operating range. The basic control

mode is voltage control and has as a voltage droop built into

the controls. Several studies to evaluate the recovery to full

power after a contingency were simulated [54]. The performances of several compensation options were compared.

These options included fixed capacitors (FC), SVC, synchro-

Similar modeling guidelines for representing rotating machine in both situations can be used, however some

particular considerations can be taken into account in some

cases and studies. Modeling guidelines provided in this document assume that power electronic systems operate at low

frequencies, between DC and 3 kHz. Therefore only the representation of rotating machines for this frequency range is

discussed. Regardless of the application to be simulated a

detailed modeling for the electrical and the mechanical parts

is usually required, saturation effects should be included, and

2-12

of electrical parameters, mainly rotor parameters might also

be considered. If frequencies of the transient case to be simulated are higher than 3 kHz, the simulation time is no longer

than a few milliseconds and the machine is not close to any

power electronic system (i.e. a synchronous machine connected to a transmission system), the mechanical part can be

usually neglected and the machine can be represented by

means of an ideal source behind its subtransient reactance

and a frequency-dependent resistor; capacitance effects

become important, they can be represented by a parallel

capacitance-to-ground [1].

Other representations should be considered for specific applications

A) An agg reg ated r epr ese ntatio n o f sever al

machines can be used to reduce complexity and simulation

time. Ref. [2] resents an aggregated induction model to be

used in power quality studies where short term interruptions

(i.e. sags) are of concern.

B) A very simplified representation for synchronous

and induction machines can be used in harmonic studies

when the machine is not directly connected to the harmonic

source [3].

An important aspect of the simulation of a rotating

machine is the procedure to obtain machine parameters and

the information where these parameters are derived. Electrical parameters of synchronous machines may usually be

obtained in one of the following forms : (1) data supplied

from manufacturer (conventional stability format data, standstill frequency response), (2) data from field tests (on-line

frequency response, load rejection test, other tests) and (3)

computer calculation using the finite-element method [4]. A

good discussion about methods to obtain electrical and also

mechanical parameters can be found in [5]. Data from steady

state and short circuit tests include reactances and time constants, armature resistance as well as saturation effects. Several procedures have been proposed to pass from these data

to electrical parameters which are used in the transient solution of the machine [6-8]. Although these tests and the corresponding procedures can also be used to obtain electrical

parameters of an induction machine, data conversion procedures for this type of machines are performed from different

specifications [9-10].

Frequency response tests have received much attention during the last 25 years. Several methods have been proposed to obtain parameters of d- and q-axis equivalent

circuits; they are based on standstill frequency response

(SSFR) [11-14], and on-line frequency response [15-16].

Some techniques have also been developed to account for

saturation effects [17].

4.5. Voltage Source Inverter Based FACTS Devices and

theirModeling Techniques Using EMTP

modeling techniques of Voltage Source Inverter-based Flexible Alternating Current Transmission Systems (FACTS)

devices, namely, STATic synchronous COMpensator (STATCOM), Static Synchronous Series Compensator (SSSC), and

Unified Power Flow Controller (UPFC) using an EMTP

simulation package. The FACTS model includes all the necessary components - a voltage source inverter with a DC link

capacitor, a magnetic circuit, and a realizable controller. The

UPFC model consists of two solid-state voltage source

inverters which are connected through a common DC link

capacitor. Each inverter is coupled with a transformer at its

output. The first voltage source inverter, known as STATCOM, injects an almost sinusoidal current, of variable magnitude, at the point of connection. The second voltage source

inverter, known as SSSC, injects an almost sinusoidal voltage, of variable magnitude, in series with the transmission

line. When the STATCOM and the SSSC operate as standalone devices, they exchange almost exclusively reactive

power at their terminals. While operating both the inverters

together as a UPFC, the injected voltage in series with the

transmission line can be at any angle with respect to the line

current. The exchanged real power at the terminals of one

inverter with the line flows to the terminals of the other

inverter through the common DC link capacitor. The functionalities of the models have been verified.

4.5.1 VSI Based Facts Devices

Flexible Alternating Current Transmission Systems

(FACTS) devices, namely STATic synchronous COMpensator (STATCOM), Static Synchronous Series Compensator

(SSSC) and Unified Power Flow Controller (UPFC), are

used to control the power flow through an electrical transmission line connecting various generators and loads at its sending and receiving ends. Each of the STATCOM and the

SSSC consists of a solid-state voltage source inverter with

several Gate Turn Off (GTO) thyristor switch-based valves

and a DC link capacitor, a magnetic circuit, and a controller.

The number of valves and the various configurations of the

magnetic circuit depend on the desired quality of AC waveforms generated by the FACTS devices. When the STATCOM and the SSSC operate as stand-alone devices, they

exchange almost exclusively reactive power at their terminals. While operating both the inverters together as a UPFC,

the exchanged power at the terminals of each inverter can be

reactive as well as real. The exchanged line flows to the terminals of the other inverter through the common DC link

capacitor. The objective in this section is to describe each

component, such as a voltage source inverter, a magnetic circuit, and a controller of FACTS devices and its modeling

techniques using an EMTP simulation package. Since, the

emphasis of modeling is purely on FACTS devices, the

power system in which the FACTS devices are connected to

has been modeled in a simplistic way. A simple transmission

line, shown in Fig. 39, has an inductive reactance, Xs, and a

voltage source, , at the sending end and an inductive reac-

2-13

tance, Xr, and a voltage source, , at the receiving end, respectively. The STATCOM is connected at BUS 1 of the

transmission line as shown in Fig. 39. The STATCOM

model in EMTP consists of a harmonic neutralized voltage

source inverter, VSI1, a magnetic circuit, MC1, a coupling

transformer, T1, a mechanical switch, MS1, current and voltage sensors, and a controller. The STATCOM injects an

almost sinusoidal current at the point of connection. This

injected current is almost in quadrature with the line voltage,

thereby emulating an inductive reactance or a capacitive

reactance at the point of connection. To achieve the basic

function of a STATCOM, the inverter is operated by regulating the reactive current flow through it.

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consists of two harmonic neutralized voltage source inverters, VSI1 and VSI2, two magnetic circuits, MC1 and MC2,

two coupling transformers, T1 and T2, four mechanical

switches, MS1, MS2, MS3, and MS4, two electronic switches,

ES2 and ES22, current and voltage sensors, and a controller.

The voltage source inverters are connected through a common DC link capacitor. In a basic operation of a UPFC, the

STATCOM is operated by regulating the reactive current

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simple transmission line between BUS 1 and BUS 2. The

SSSC model in EMTP consists of a harmonic neutralized

voltage source inverter, VSI2, a magnetic circuit, MC2, a

coupling transformer, T2, a mechanical switch, MS2, two

electronic switches, ES2 and ES22, current and voltage sensors, and a controller. The SSSC injects an almost sinusoidal

voltage, of variable magnitude, in series with the transmission line. This injected voltage is almost in quadrature with

the line current, thereby emulating an inductive reactance or

a capacitive reactance in series with the transmission line.

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referred to as a 3-level pole, which consists of a positive

valve, A+, a negative valve, A-, and an AC valve, A AC.

When a pole is connected across a series of capacitors which

are charged with a total DC voltage of vDC and the valves are

closed and opened alternately, the pole output voltage, vAO,

at the midpoint of the pole A with respect to the midpoint, O,

of the capacitor is a quasi square wave containing a positive

sequence fundamental component and all the odd harmonic

components, such as the zero sequence third, the negative

sequence fifth, and the positive sequence seventh, etc.

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2-14

fundamental and all the harmonic components of the pole

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fundamental as well as all the harmonic components have the

highest possible amplitudes.

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with 3-Level poles

connected across the same DC link capacitor and the pole

outputs are connected to a 3-phase load whose neutral point,

N, is not connected to the midpoint of the capacitor. The

poles A, B, and C which form a 6-pulse inverter are operated

in such a way that the pole voltages, vAO, vBO, and vCO, are

time shifted from one another by one third of the time period

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path to the midpoint of the DC link capacitor, the zero

sequence components of each pole voltage, vNO = (vAO + vBO

+ vCO)/3, appear between the neutral point and the midpoint

of the DC link capacitor. Therefore, each phase of the load

voltages, vAN = vAO - vNO, vBN = vBO - vNO, and vCN = vCO vNO, consists of only a fundamental component and odd harmonic components (n) given by the equation (1) where n = 6k

1 for k = 1, 2, 3, etc.

Fig. 44 shows two 6-pulse inverters (ABC and DEF)

which are operated from the same DC link capacitor. On the

AC side, they are connected to a 3-phase load (XYZ) through

a magnetic circuit. The poles D, E, and F are operated in

such a w ay th at t he po le v ol tag e f un dam e nta l p hasors V E, 1, V C, 1

and

V F, 1 and are 120 o apart and the

fundamental voltage phasor set of the DEF inverter lags the

fundamental voltage phasor set of the ABC inverter by 30o.

The displacement angle between two consecutive 6-pulse

inverters in a multipulse inverter arrangement is 2/6m,

where m is the total number of 6-pulse inverters used. The

configuration of the magnetic circuit in Fig. 44 is such that if

Table 1 shows the time shifted A and D pole voltages first twenty five harmonic components final phase

angles after appropriate phase shift. The pole voltages from

the ABC inverter exhibits a 6-pulse harmonic neutralized

waveform with harmonic components n = 6k 1 for k = 1, 2,

3, etc. Similarly, the pole voltages from the DEF inverter

exhibits a 6-pulse harmonic neutralized waveform whose

harmonic components (n = 6k 1 for k = 1, 2, 3, etc.) have

the same magnitudes as the corresponding harmonic components of the ABC inverters 6-pulse harmonic neutralized

waveform. However, the harmonic components (n = 6k 1

for k = 1, 3, 5, etc.) are in opposite phases while the harmonic

components (n = 6k 1 for k = 2, 4, 6, etc.) are in phases with

the corresponding harmonic components of the ABC

inverters 6-pulse harmonic neutralized waveform. Therefore, if all the outputs from each 6-pulse inverter are combined by connecting the corresponding phases in series, a 12pulse harmonic neutralized waveform is obtained. The

resulting output voltage exhibits a fundamental component

and odd harmonic components (n) given by the equation (1)

where n = 12k 1 for k = 1, 2, 3, etc. Note that the output

voltage of a 12-pulse inverter with 3-level poles is referred to

as a 12-pulse waveform when the poles are operated with

dead angle = 0.

Fig. 45 shows a possible configuration of the magnetic circuit which can be used to generate a 12-pulse harmonic neutralized voltage. The ABC 6-pulse inverter

voltage is fed to a Y-Y transformer and the DEF 6-pulse

inverter voltage is fed to a (-Y transformer. The inverter side

A winding and DE winding will have per turn fundamental

component voltages which are of same magnitude and in

phase and the fifth and the seventh harmonic components

each of which are of same magnitude but in opposite phase.

Therefore, if the line side of the transformer windings are

connected in series, the phase-X voltage will exhibit only a

2-15

Note that the inverter side ( winding has 3 times the turns

as the inverter side Y winding has. This is needed in order to

keep the same volts per turn in both windings. The line side

inverter windings can have any turns ratio other than 0.5 to

increase or decrease the output voltage.

n

time shift

5

7

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section. In an actual simulation case, the gating signals are

used to operate the pole valves of an inverter structure such

as one shown in Fig. 42.

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component and odd harmonic components (n) where n = 12k

1 for k = 1, 2, 3, etc. The presence of 12-pulse harmonic

components in the inverter output voltage may not be acceptable in many applications. Therefore, an inverter with a

higher pulse output voltage should be considered [56-58].

ig. 46 shows the block diagram of the EMTP simulation program layout. Sample EMTP program files are

given in [56-58]. First, some general constants are defined.

Next, the control or the Transient Analysis of Control Systems (TACS) section receives its input signals from the sensors or measuring switches. This section generates the gating

signals for the pole valves on the fly. The ideal pole voltages are mathematically combined to produce harmonic neu-

modeled with a number of GTO thyristors connected in

series each having an antiparallel diode and appropriate

snubber circuits. The pole output voltages are fed to a magnetic circuit, located in the branch section, which produces a

3-phase voltage set. In this way, the effects of a nonideal

magnetic circuit, which includes leakage reactance, magnetic

saturation, etc. can be studied. However, in this paper, the

valves and the magnetic circuit are assumed to be ideal. The

voltage, vDC, across the DC link capacitor is maintained by

the power balance equation at both AC and DC sides of the

inverter. This modeling technique gives more insight to the

operation of the power circuit which produces a 3-phase voltage set. The source section has some independent voltage

sources which establish the power flow in a transmission

line. Next, the controlled and the independent sources are

fed to the branch section which contains the transmission line

and the coupling transformer. The line voltage set, v 1 , at

BUS 1, the inverters current sets, i1 and i2, and the line current, i, are measured by the measuring switches. Finally, the

output section is defined. In reality, the magnetic circuit can

also serve as the coupling transformer. Therefore, there is no

need for an additional coupling transformer.

The modeling may be done at various levels. For

example, to study the functionality of a FACTS device on an

elaborated power system network, a FACTS device with a

simplified model consisting of sinusoidal voltage sources

and detailed control and protection schemes may be adequate. For magnetic circuit and valve designers, the primary

focus should be on the modeling of the detailed power circuit. The modeling techniques described in this section are

2-16

The various control techniques of FACTS devices

and simulation results are described in the next section. In

each case, an instantaneous 3-phase set of line voltages, v1, at

BUS 1 is used to calculate the reference angle, which is

phase-locked to the phase a of the line voltage, v1a.

A. STATCOM

The controller of a STATCOM is used to operate the

inverter in such a way that the phase angle between the

inverter voltage and the line voltage is dynamically adjusted

so that the STATCOM generates or absorbs desired VAR at

the point of connection [56]. Fig. 47 shows the control block

diagram of the STATCOM. An instantaneous 3-phase

0 and 50 ms, the mechanical switch, MS1, stays open, disconnecting the STATCOM from the transmission line. The DC

link capacitor is precharged. The inverter output 12-pulse

voltage of phase a, e1a, and the line voltage of phase a, v1a,

are in phase. At 50 ms, MS1 closes and the quadrature current demand, I 1q * , of the inverter is set to zero. Since the

inverter current is zero, the inverter voltage of phase a, e1a,

and the line voltage of phase a, v1a, have equal amplitudes.

At 125 ms, the quadrature current demand, I 1q * , of the

inverter is set to one per unit capacitive, which means the

STATCOM should see the system as an inductive reactance and the inverter current of phase a, i1a, lags the line

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to be either positive if the STATCOM is emulating an inductive reactance or negative if it is emulating a capacitive reactance. The DC link capacitor voltage, vDC, is dynamically

adjusted in relationship with the inverter voltage. The control scheme used in this section shows the implementation of

the inner current control loop which regulates the reactive

current flow through the inverter regardless of the line voltage. However, if one is interested in regulating the line voltage, an outer voltage control loop must be implemented. The

outer voltage control loop will automatically determine the

reference reactive current for the inner current control loop

which, in turn, will regulate the line voltage.

Fig. 48 shows the digital simulation results from the

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into its real or direct component, I1d, and reactive or quadrature component, I 1q , respectively. The quadrature component is compared with the desired rference value, I1q *, and

the error is passed through an error amplifier which produces

a relative angle, , of the inverter voltage with respect to the

line voltage. The phase angle, 1, of the inverter voltage is

calculated by adding the relative angle, , of the inverter

voltage and the phase-lock-loop angle, . The reference

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12-Pulse Harmonic Neutralized Inverter Operating in Capacitive and

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voltage set, v1. At 175 ms, the quadrature current demand,

I1q* , of the inverter is set to one per unit inductive, which

means the STATCOM should see the system as a capacitive reactance and the inverter current in phase a, i1a, leads

voltage set, e1, is less than the line voltage set, v1. At 250 ms,

the quadrature current demand, I1q*, of the inverter is set to

one per unit capacitive and the transition takes place in a subcycle time. The phase angle, , between the inverter voltage

and the line voltage is dynamically adjusted so that the

inverter maintains proper DC link capacitor voltage.

Fig. 49 shows the expanded view of two sections of

Fig. 48. The inverter voltage and current show the presence

2-17

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B. SSSC

An SSSC controller uses a solid-state voltage source

inverter to inject an almost sinusoidal voltage, of variable

magnitude, in series with a transmission line. This injected

voltage is almost in quadrature with the line current. A small

part of the injected voltage which is in phase with the line

current provides the losses in the inverter. Most of the

injected voltage which is in quadrature with the line current

emulates an inductive or a capacitive reactance in series with

the transmission line. This emulated variable reactance,

inserted by the injected voltage source, influences the electric

power flow in the transmission line. If an SSSC is operated

with an energy storage system, the controller becomes an

impedance compensation controller which can compensate

for the transmission line resistance as well as reactance. The

reactance compensation controller is used to operate the

inverter in such a way that the injected alternating voltage in

series with the transmission line is proportional to the line

current with the emulated reactance being the constant of

proportionality [57]. When an SSSC injects an alternating

voltage leading the line current, it emulates an inductive

reactance in series with the transmission line causing the

power flow as well as the line current to decrease as the level

of compensation increases and the SSSC is considered to be

operating in an inductive mode. When an SSSC injects an

alternating voltage lagging the line current, it emulates a

capacitive reactance in series with the transmission line causing the power flow as well as the line current to increase as

the level of compensation increases and the SSSC is considered to be operating in a capacitive mode. An SSSC controller can also be used for stable reversal of power flow in the

transmission line.

An instantaneous 3-phase set of measured line currents, i, is

first decomposed into its real or direct component, I d , and

reactive or quadrature component, Iq, and then the amplitude,

I, and the relative angle, ir, of the line current with respect

to the phase-lock-loop angle, , are calculated. The phase

angle, i, of the line current is calculated by adding the relative angle, ir, of the line current and the phase-lock-loop

angle, . The calculated amplitude, I, of the line current

multiplied by the compensating reactance demand, Xq*, is the

insertion voltage amplitude demand, Vq*. The phase angle,

the demanding compensating reactance is capacitive. The

DC link capacitor voltage is dynamically regulated in relationship with the insertion voltage amplitude demand. The

insertion voltage amplitude demand, Vq* , and the DC link

capacitor voltage demand, VDC*, are related by the inverter

DC-to-fundamental AC amplitude gain factor (Kinv = 2/ for

a true harmonic netralized voltage source inverter). The DC

link capacitor voltage demand, VDC*, and the measured DC

voltage, vDC, are compared and the error is passed through an

error amplifier which produces an angle, . The phase angle,

2, of the inverter voltage is calculated by adding the angle,

, of the DC voltage regulator and the phase angle, v, of the

insertion voltage demand. The compensating reactance

demand, Xq*, is either negative if the SSSC is emulating an

inductive reactance or positive if it is emulating a capacitive

reactance. In another application, the insertion voltage

amplitude demand, Vq * may directly be specified and the

SSSC will inject the desired voltage almost in quadrature

with the line current.

2-18

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SSSC emulates a reactance in series with the transmission

line. At the beginning of the operation, the mechanical

switch, MS2, and the electronic switch, ES22, are open and

the electronic switch, ES2, is closed. The inverter, VSI2,

injects no voltage. The DC link capacitor voltage, v DC, is

zero. At 50 ms, an inductive reactance compensation of 0.15

per unit is requested. The inverter output 24-pulse voltage,

175 ms, the inductive reactance demand is increased to 0.3

per unit. As the inductive reactance demand increases, the

line current, ia, and the power flow, Pq and Qq, in the transmission line decrease. At 300 ms, a capacitive reactance

compensation of 0.1 per unit is requested. The inverter volt

age, e2a, lags the line current, ia, by almost 90 . At 450 ms,

the capacitive reactance demand is increased to 0.15 per unit.

As the capacitive reactance demand increases, the line current, ia, and the power flow, Pq and Qq , in the transmission

line increase. In reality, the SSSC would encounter power

losses in the valves and in the magnetic circuit. Therefore,

there will always be a small part of real current component,

I1d, flowing into the inverter and the inverter voltage will be

almost 90 out of phase with the line current. The instantaneous DC link capacitor voltage is proportional to the amplitude of the inverter voltage.

Therefore, when an SSSC emulates a reactance in

series with the transmission line, the power flow in the transmission line always decreases if the emulated reactance is

inductive. Also, the power flow always increases if the emulated reactance is capacitive.

Fig. 52 shows the expanded view of the two sections of Fig.

51. The inverter voltage show the presence of 24-pulse harmonic components.

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C. UPFC

The stand alone operations of the STATCOM and

the SSSC, as just described, only allow the inverters to

exchange almost exclusively reactive power at their terminals. However, if both the inverters are operated from a common DC link capacitor, the injected voltage by the SSSC can

be at any angle with respect to the line current. The real

power exchanged at the terminals of the SSSC appears at the

terminals of the STATCOM through the DC link capacitor.

The STATCOM can still be used to control the reactive current flow through it independently [58]. The current injected

by the STATCOM has two components. First, a real or direct

component, which is in phase with the line voltage, absorbs

or delivers the real power exchanged by the SSSC with the

line. Second, a reactive or quadrature component, which is

in quadrature with the line voltage, emulates an inductive or

a capacitive reactance at the point of connection with the

transmission line.

The SSSC can be operated in many different modes,

such as voltage injection, phase angle shifter emulation, line

impedance emulation, automatic power flow control, etc. In

each mode of operation, the final outcome is such that the

SSSC injects a voltage in series with the transmission line

[58]. In this section, the SSSC is operated in a voltage injection mode. The control block diagram for the SSSC is shown

in Fig. 53.

The desired peak fundamental voltage, Vdq*, at the

output of the inverter and its relative angle, , with respect to

the reference phase-lock-loop angle are specified. The phase

angle, 2, of the inverter voltage is calculated by adding the

relative angle, , of the inverter voltage and the phase-lock-

2-19

accordance with the operation of 24-pulse quasi harmonic

neutralized inverter [58].

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voltage injection mode of operation of an SSSC while the

STATCOM is operated to deliver no reactive current.

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coupling transformer, T2, is the voltage across its leakage

reactance. The mechanical switch, MS1, is open, disconnecting the STATCOM from the transmission line. The DC link

capacitor is precharged. At 50 ms, MS1 closes and the

quadrature current demand, I1q*, of the inverter is set to zero.

At 100 ms, a series voltage injection of 0.2 per unit at an

requested. The series inverter output voltage, e2a, of phase a

leads the line current, i a , by an angle . The real power

absorbed by the series inverter appears at the BUS 1 through

the STATCOM. The shunt inverter output voltage, e1a, of

phase a is in phase with the current, i1a, flowing through it.

The power delivered at the receiving end decreases. At 175

ms, the injected voltage request is increased to 0.4 per unit

while maintaining the same angle. As the voltage injection

demand increases, the line current, ia, and the power flow, Pr

and Qr, in the transmission line decrease. By injecting a voltage by the SSSC of any magnitude, within the rating of the

inverter, and at any angle with respect to the line current, the

real power, Pr, and the reactive power, Q r, at the receiving

end of the transmission line can be increased, decreased or

even reversed selectively.

Fig. 55 shows the expanded view of two sections of

Fig. 54. The inverter voltage and current show the presence

of harmonic components.

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24-Pulse Quasi Harmonic Neutralized Inverter with 3-Level Poles

Operating in a Voltage Injection Mode

Fig. 54 Performance of a Unified Power Flow Controller with a 24Pulse Quasi Harmonic Neutralized Inverter with 3-Level Poles Operating in a Voltage Injection Mode

switch, MS2, and the electronic switch, ES22, are open and

the electronic switch, ES2, is closed. The inverter, VSI2,

4.5.4 SUMMARY

FACTS devices - STATCOM, SSSC, and UPFC,

have been modeled using an EMTP simulation package. The

UPFC consists of two voltage source inverters - one injects

an almost sinusoidal voltage in series with the transmission

2-20

point of connection. The injected voltage can be at any angle

with the line current. The injected current has two parts.

First, the real part, which is in phase with the line voltage,

delivers or absorbs real power to the line that is exchanged by

the injected voltage source plus losses in the UPFC. Second,

the reactive part, which is in quadrature with the line voltage,

emulates an inductive reactance or a capacitive reactance at

the point of connection. The SSSC model has been operated

injecting a voltage in series with the transmission line. The

STATCOM model has been operated regulating the reactive

current flow through it and the transition from one mode of

operation to the other mode takes place in a subcycle time.

The operation of the model is verified with the model connected to a simple transmission line which can easily be

replaced by the utilitys existing more complex power system

network.

3.

5. CONCLUSIONS

10.

very important in power system simulations involving power

electronics operations. In most of these simulations, detailed

representations of the power electronics are not necessary.

Depending on the objective of a study, the involved power

electronics subsystem can be always reduced to some extend

with minimal loss of accuracy.

Numbers of the digital computation tools are capable of simulating power electronics cases. However, in power systems

engineering community, the EMTP type of programs are

more commonly used. This results mainly from the great capabilities and flexibility of these programs in handling conventional power system dynamics and electromagnetic

transients beside their capabilities of handling power electronics. With an adequate power electronics device and circuit

simplification, the EMTP type of programs are powerful for

modeling various types of power electronics applications.

Because these programs are based on the time domain solution method, the dynamic interaction between the power electronics and the rest of the system can be easily incorporated in

simulation.

The important considerations for simulating power electronics applications have been summarized in this guidelines.

Several modeling examples including a comprehensive treatment of voltage source inverter based FACTS device and its

modeling techniques using EMTP type of programs were presented. The procedures used to implement power electronics

models in these examples are valuable for using other digital

simulation tools.

6. REFERENCES

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the Hydro-Quebec - New England HVDC system and

digital controls with EMTP, IEEE Trans. on Power Delivery, Vol. 8, No. 2, April 1993, pp. 559-566.

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2-23

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