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CMOS TECHNOLOGY

CMOS circuits require that both NMOS and PMOS enhancement devices to be fabricated
on same chip The main advantage of CMOS over NMOS and BIPOLA techno!og" is the
much sma!!er po#er dissipation$ %n!i&e NMOS or BIPOLA circuits' a CMOS circuit has
a!most (ero static po#er dissipation$ Po#er is on!" dissipated in case the circuit actua!!"
s#itches$ This a!!o#s to integrate man" more CMOS gates on an IC than in NMOS or bipo!ar
techno!og"' resu!ting in high pac&ing densit"$
Advantages of CMOS !ogic
No static po#er dissipation
)igh o*p vo!tage s#ing+O*P S,IN- B.T,..N /00 and -O%N0 POT.NTIAL1
)igh Noise margin
)igh Pac&ing densit"
0isadvantage
Possibi!it" of !atch up due to parasitic bipo!ar transistors because of e2istence of
PMOS and NMOS circuits in same substrate
CMOS structure
CMOS circuits require that both NMOS and PMOS enhancement devices to be fabricated
on same chip$ CMOS structure ma" be
n#e!! structure3n#e!! is imp!anted in psubstarte$nmos is fabdricated in in p3substrate
and p#e!!! is imp!anted in #hich nMOS is fabricated$
p#e!! structure3p#e!! is imp!anted in n substrate$Pmos is fabricated in n3substrate and
n3#e!!! is imp!anted in #hich PMOS is fabricated$
T#in #e!! structure 4 t#o separate #e!!s +n#e!! and p#e!!1 are imp!anted in !ight!"
doped si!icon
A basic CMOS structure using n #e!! process is sho#n be!o#$
This basic CMOS structure is bui!t on a p3t"pe substrate$ The pMOS transistor requires an n3
t"pe bod" region' so an n3#e!! is diffused into the substrate in its vicinit"$ the nMOS
transistor has heavi!" doped n3t"pe source and drain regions and a po!"si!icon gate over a thin
!a"er of si!icon dio2ide +SiO5' a!so ca!!ed gate o2ide1$ n6 and p6 diffusion regions indicate
heavi!" doped n3t"pe and p3t"pe si!icon$ The pMOS transistor is a simi!ar structure #ith p3
t"pe source and drain regions$ The po!"si!icon gates of the t#o transistors are tied together
some#here off the page and form the input A$ The source of the nMOS transistor is
connected to a meta! ground !ine and the source of the pMOS transistor is connected to a
meta! /00 !ine$ The drains of the t#o transistors are connected #ith meta! to form the output
7$ A thic& !a"er of SiO5 ca!!ed fie!d o2ide prevents meta! from shorting to other !a"ers e2cept
#here contacts are e2p!icit!" etched$
A 8unction bet#een meta! and a !ight!" doped semiconductor forms a Schott&" diode that
on!" carries current in one direction$ ,hen the semiconductor is doped more heavi!"' it forms
a good ohmic contact #ith meta! that provides !o# resistance for bidirectiona! current f!o#$
The substrate must be tied to a !o# potentia! to avoid for#ard3biasing the p3n 8unction
bet#een the p3t"pe substrate and the n6 nMOS source or drain$ Li&e#ise' the n3#e!! must be
tied to a high potentia!$ This is done b" adding heavi!" doped substrate and #e!! contacts' or
taps' to connect -N0 and /00 to the substrate and n3#e!!' respective!"$
OPERATION OF A BASIC CMOS STRUCTURE
,hen the input is !o# NMOS transistor is off 'PMOS device #i!! be ON and the o*p vo!tage
#i!! be pu!!ed up to high state near the positive po#er supp!" vo!tage /00 $,hen input is
high NMOS turns on and PMOS turns O99 and output vo!tage #i!! no# drop to !o# state
near ground potentia!$In either of these conditions one of the transistor is off and current
through the CMOS pair is neg!igib!e$ )ence po#er consumption is !o#'on!" significant
po#er consumption is during transition$Another advantage is !arge output vo!tage s#ing
'#ith high state o*p vo!tage c!ose to /00 and !o# state c!ose to ground potentia!$
FABRICATION -n-well CMOS structure
A basic CMOS structure 3 inverter cou!d be defined b" a h"pothetica! set of si2 mas&s: n3
#e!!' po!"si!icon'n6 diffusion' p6 diffusion' contacts' and meta!$
Step 1 S! Su"str#te
The n3#e!! CMOS process starts #ith a moderate!" doped +#ith impurit" concentration
around 5
;<=
5<
impurities*m
>
1 p3t"pe si!icon substrate$
The #afer is first o2idi(ed in a high3temperature +t"pica!!" ?==4<5== @C1 furnace that causes
Si and O5 to react and become SiO5 on the #afer surface$ O2ide must be patterned to define
the n3#e!!$
An organic photoresist that softens #here
e2posed to !ight is spun onto the #afer$
The first !ithographic mas& defines the n #e!! region is brought in c!ose pro2imit" to the
#afer$
The photoresist is e2posed through the n3#e!! mas& that a!!o#s !ight to pass through on!"
#here the #e!! shou!d be$
The softened photoresist is removed to e2pose the o2ide
The o2ide is etched #ith h"drof!uoric acid +)91 #here it is not protected b" the photoresist $
Strip off remaining photoresist$ photoresist is stripped a#a" using a mi2ture of acids ca!!ed
piranha etch
The #e!! is formed #here the substrate is not covered #ith o2ide$ T#o #a"s to add dopants
are diffusion and ion imp!antation$ In the diffusion process' the #afer is p!aced in a furnace
#ith a gas containing the dopants$ ,hen heated' dopant atoms diffuse into the substrate$ ,ith
ion imp!antation' dopant ions are acce!erated through an e!ectric fie!d and b!asted into the
substrate$ In either method' the o2ide !a"er prevents dopant atoms from entering the substrate
#here no #e!!
is intended$
9ina!!"' the remaining o2ide is stripped #ith )9 to !eave the bare #afer #ith #e!!s in the
appropriate p!aces$
The transistor gates are formed ne2t$ These consist of po!"cr"sta!!ine si!icon' genera!!" ca!!ed
po!"si!icon' over a thin !a"er of o2ide$ The thin o2ide is gro#n in a furnace$ Then the #afer is
p!aced in a reactor #ith si!ane gas +Si)A1 and heated again to gro# the po!"si!icon !a"er
through a process ca!!ed chemica! vapor deposition$ The po!"si!icon is heavi!" doped to form
a reasonab!" good conductor
The #afer is patterned #ith photoresist and the po!"si!icon mas& !eaving the po!"si!icon gates
on top of the thin gate o2ide$
The n6 regions are introduced for the transistor active area and the #e!! contact$
a1A protective !a"er of o2ide is formed $
b1O2ide !a"er is patterned #ith the n3diffusion mas& to e2pose the areas #here the dopants
are needed
Mas&ing
c1.tching o2ide over n6regions
The n6 regions for source and drain of nMOS transistor and substrate tap are t"pica!!"
formed #ith ion imp!antation' sti!! are often ca!!ed n3diffusion$The po!"si!icon gate over the
nMOS transistor b!oc&s the diffusion so the source and drain are separated b" a channe! under
the gate$ This is ca!!ed a se!f3a!igned process because the source and drain of the transistor are
automatica!!" formed ad8acent to the gate #ithout the need to precise!" a!ign the mas&s$
d1
e19ina!!"' the protective o2ide is stripped
The $!el% &'!%e !s (r&wn t& !nsul#te t)e w#$er $r&* *et#l and patterned #ith the contact
mas& to !eave contact cuts #here meta! shou!d attach to diffusion or po!"si!icon$
9ina!!"' a!uminum is sputtered over the entire #afer' fi!!ing the contact cuts as #e!!$
Sputtering invo!ves b!asting a!uminum into a vapor that even!" coats the #afer$ The meta! is
patterned #ith the meta! mas& and p!asma etched to remove meta! ever"#here e2cept #here
#ires shou!d remain This comp!etes the nMos fabrication process$
L#tc) up
E+u!,#lent l#tc) up c-t !s (!,en #s
Latch3up is defined as the generation of a !o#3impedance path in CMOS chips bet#een the
po#er supp!" rai! and the ground rai! due to interaction of parasitic pnp and npn bipo!ar
transistors$ These BBTs form a si!icon3contro!!ed rectifier +SC1 #ith positive feedbac& and
virtua!!" short circuit the po#er rai! to3ground' thus causing e2cessive current f!o#s and even
permanent device damage$
In the equiva!ent circuit' C< is a vertica! pnp transistor #hose base is formed b" the n3
#e!! #ith its base3to3co!!ector current gain +D
<
1 as high as severa! hundreds$ C5 is a !atera!
doub!e3emitter npn transistor #ith its base formed b" the p3t"pe substrate$ The base3to3
co!!ector current gain (D
5
) of this !atera! transistor ma" range from a fe# tenths to tens$ Rweil
represents the parasitic resistance in the n3#e!! structure #ith its va!ue ranging from < &ohm
to 5= &ohm$ The substrate resistance Rsub strong!" depends on the substrate structure'
#hether it is a simp!e p3 or p3 epita2ia! !a"er gro#n on top of the p6 substrate #hich acts as a
ground p!ane$ In the former case Rsub can be as high as severa!
hundred ohms' #hereas in the !atter case the resistance can be as !o# as a fe# ohms$
To e2amine the !atch3up event' first assume that the parasitic resistances Rwell and
Rsub are sufficient!" !arge so that the" can be neg!ected +open circuit1$ %n!ess the SC is
triggered b" an e2terna! disturbance' the co!!ector currents of both transistors consist of the
reverse !ea&age currents of the co!!ector3base 8unctions and therefore' their current gains are
ver" !o#$ If the co!!ector current of one of the transistors is temporari!" increased b" an
e2terna! disturbance' ho#ever' the resu!ting feedbac& !oop causes this current perturbation to
be mu!tip!ied b" (D
5
). This event is ca!!ed the triggering of the SC$ Once triggered' each
transistor drives the other transistor #ith positive feedbac&'eventua!!" creating and sustaining
a !o#3impedance path bet#een the po#er and the ground rai!s' resu!ting in !atch3up$
It can be seen that if the condition
.
1
/.
0
11
is satisfied' both transistors #i!! continue to conduct a high +saturation1 current' even after
the triggering perturbation is no !onger avai!ab!e$
C#uses &$ l#tc) up
Sudden transients in po#er or ground buses due to simu!taneous s#itching of man"
drivers ma" turn on a BBT in SC$
Large currents in the parasitic SC in CMOS chips can occur #hen the input or
output signa! s#ings either far be"ond the VDD !eve! or far be!o# the Vss +ground1
!eve!' thus in8ecting a triggering current$
Lea&age currents in #e!! 8unctions can cause !arge enough !atera! currents$
Pre,ent!&n &$ l#tc) up
The !atch3up susceptibi!it" is inverse!" proportiona! to the product of the substrate doping
!eve! and the square of the spacing$
%se p6 guard rings connected to ground around nMOS transistors and n6 guard rings
connected to VDD around pMOS transistors to reduce Rwell and Rsub and to capture
in8ected minorit" carriers before the" reach the base of the parasitic BBTs$
P!ace substrate and #e!! contacts as c!ose as possib!e to the source connections of
MOS transistors to reduce the va!ues of Rwell and Rsub
educe the gains of BBTs
CMOS l&(!c c!rcu!ts
In CMOS !ogic circuits' both N3t"pe and P3t"pe transistors are used to rea!i(e !ogic
functions$
-.N.AL ST%CT%. O9 COMPL.M.NTACMOS LO-IC -AT.
CMOS !n,erter
G#te sc)e*#t!c L&(!c s2*"&l
Trut) t#"le
I*P+A1 NMOS PMOS 7
< ON O99 =
= O99 ON <
CMOS inverter structure' consists of an enhancement3t"pe nMOS transistor and an
enhancement3t"pe pMOS transistor' operating in comp!ementar" mode $ This configuration is
ca!!ed Comp!ementar" MOS +CMOS1$ The circuit topo!og" is comp!ementar" push3pu!! in
the sense that for high input' the nMOS transistor drives +pu!!s do#n1 the output node #hi!e
the pMOS transistor acts as the !oad' and for !o# input the pMOS transistor drives +pu!!s up1
the output node #hi!e the nMOS transistor acts as the !oad$
,hen a !o# vo!tage += /1 is app!ied at the input' pMOS is conducting +s#itch c!osed1
#hi!e Nmos behaves !i&e an open circuit$Therefore' the supp!" vo!tage +E /1 appears
at the output$
Converse!"' #hen a high vo!tage +E /1 is app!ied at the input' the nMOS is conducting
+s#itch c!osed1 #hi!e pMOS behaves !i&e an open circuit$)ence' the ouput vo!tage is
!o# += /1$
The CMOS inverter has t#o important advantages over the other inverter configurations$
The stead"3state po#er dissipation of the CMOS inverter circuit is virtua!!"
neg!igib!e' e2cept for sma!! po#er dissipation due to !ea&age currents$.ither one of
the t#o transistors is ON in stead" state'hence there is no continuous current path
from /00 to /ss po#er rai!$
The vo!tage transfer characteristic +/TC1 e2hibits a fu!! output vo!tage s#ing
bet#een = / and /00$ie high vo!tage s#ing and hence high noise margin
3OLTAGE TRANSFER CHARACHTERISTICS 4 5C CHARACTERISTICS
Summar" of CMOS IN/.T. OP.ATION
egion nmos pmos
A LIN.A C%T O99
B LIN.A SAT%AT.0
C SAT%AT.0 SAT%AT.0
0 SAT%AT.0 LIN.A
. C%T O99 LIN.A
Considering static conditions first In region A'NMOS is turned ON'PMOS is turned
O99'output node is direct!" connected to /00$No curren f!o#s through inverter$In region E
/in FG !ogic <'n MOS IS ON PMOS is O99$o*P node is pu!!ed do#n to !ogic =$No current
f!o#s$
In region B'input vo!tage has increased to a thresho!d that 8ust e2ceeds thresho!d vo!tage of
nmos'NMOS is conduction #ith !arge va!ue of drain to source vo!tage 'hence operates in
saturation and pmos is conducting #th sma!! va!ue of /
0S
'hence it operates in !inear
region$A sma!! current no# f!o#s through inverter$everse is the case in region 5$PMOS is
in saturation and nmos in !inear region$
In region C 'both transistors are in saturation$Ma2imum current f!o#s through the circuit$
Thresho!d vo!tage of inverter is that va!ue of i*p vo!tage at #hich /in F/out$In the idea! case
ie /tnFH/tpH and transcinductance ratioD
n
FD
p
$/thF/00*5$
6SEE 5ERI3ATION OF THRESHOL5 3OLTAGE IN TE7T -PUC8NELL9
NAN5 G#te
GATE SCHEMATIC3NAN05
LOGIC SYMBOL3NAN05
TRUTHTABLE
9igure sho#s a 53input CMOS NAN0 gate$ It consists of t#o series nMOS transistors
bet#een output node 7 and -N0 and t#o para!!e! pMOS transistors bet#een 7 and /00$ If
either input A or B is =' at !east one of the nMOS transistors #i!! be O99' brea&ing the path
from 7 to -N0$ But at !east one of the pMOS transistors #i!! be ON' creating a path from 7
to /00$ )ence' the output 7 #i!! be <$ If both inputs are <' both of the nMos transistors #i!!
be ON and both of the pMOS transistors #i!! be O99$ )ence' the output #i!! be =$ Thus' the
dua! or comp!ementar" circuit structure a!!o#s that' for an" given input combination' the
output is connected either to /00 or to ground via a !o#3resistance path$ A 0C current path
bet#een the /00 and ground is not estab!ished for an" of the input combinations$ This
resu!ts in the fu!!" comp!ementar" operation mode
&3input NAN0 gates are constructed using & series nMOS transistors and & para!!e!
pMOS transistors
NOR gate
-AT. SC).MATIC3 NOR0

LO-IC S7MBOL
TRUTHTABLE
A B P%LL0O,N
N.T
P%LL %P N.T 7
= = O99 ON <
= < ON O99 =
< = ON O99 =
< < ON O99 =
The circuit consists of a para!!e!3connected n3net+pu!! do#n net#or&1 and a series3connected
comp!ementar" pnet+pu!! up net#or&1$ The nMOS transistors are in para!!e! to pu!! the output
!o# #hen either input is high$ The pMOS transistors are in series to pu!! the output high #hen
oth inputs are !o#$ If either input A or B or is !ogic <' at !east one or both of the nMOS
transistors #i!! be ON' creating a path from 7 to -N0$)ence' the output 7 #i!! be =$ If both
inputs are =' both of the nMOS transistors #i!! be ON and o*p #i!! be !ogic =$If both inputs
are =' both of the pMOS transistors #i!! be ON and both of the nMOS transistors #i!! be O99$
)ence' creating a path from output 7 to /00$)encethe output #i!! be <$ Thus' the dua! or
comp!ementar" circuit structure a!!o#s that' for an" given input combination' the output is
connected either to /00 or to ground via a !o#3resistance path$ A 0C current path bet#een
the /00 and ground is not estab!ished for an" of the input combinations$ This resu!ts in the
fu!!" comp!ementar" operation mode $&3input NO gates are constructed using & para!!e!
nMOS transistors and & series pMOS transistors
CMOS Full A%%er
The sumout and carr"3out signa!s of the fu!! adder are defined as the fo!!o#ing t#o
combinationa! Boo!ean functions of the three input variab!es' A' B' and C$
%sing inverting propert" of fu!! adder:inverting a!! inputs to a fu!! adder !eads to
inverted outputs'sum can be e2pressed in terms of carr"'hence reducing the no:of
transistors to rea!i(e a fu!! adder$
%sing inverting propert" of fu!! adder Carr"outIFAIBI6BICI6AICI
Therfore Sum JoutFABC6+A6B6C1Carr"JoutI
)ence #e rea!i(e
A gate3!eve! rea!i(ation of these t#o functions is sho#n in 9igure be!o#$ Instead of
rea!i(ing the t#o functions independent!"' #e use the carr"3out signa! to generate the
sum output$ This imp!ementation #i!! u!timate!" reduce the circuit comp!e2it" and'
hence' save chip area$
The transistor3!eve! design of the CMOS fu!!3adder circuit is sho#n in 9igure be!o#$$
9or trans!ating the gate3!eve! design into a transistor3!eve! circuit description' #e
note that both the sum$$out and the carr"out functions are represented b" nested AN03
O3NO structures in 9igure be!o#$ .ach such combined structure +comp!e2 !ogic
gate1 can be rea!i(ed in CMOS as fo!!o#s: the AN0 terms are imp!emented b" series3
connected nMOS transistors' and the O terms are imp!emented b" para!!e!3
connected nMOS transistors$ The input variab!es are app!ied to the gates of the nMOS
+and the comp!ementar" pMOS1 transistors$ Thus' the nMOS net ma" consist of
nested series3para!!e! 'connections of nMOS transistors bet#een the output node and
the ground$ Once the nMOS part of a comp!e2 CMOS !ogic gate is rea!i(ed' the
corresponding pMOS net' #hich is connected bet#een the output node and the po#er
supp!"' is obtained as the dua! net#or& of the nMOS net$ the dua! +pMOS1 net#or& is
actua!!" equiva!ent to the nMOS net#or& for both the sumJout and the carr"3out
functions' #hich !eads to a fu!!" s"mmetric circuit topo!og"$The circuit contains a
tota! of <A nMOS and <A pMOS transistors' together #ith the t#o CMOS inverters
#hich are used to generate the outputs$
TRANSMISSION GATE
The CMOS transmission gate consists of one nMOS and one pMOS transistor' connected in
para!!e!$ The gate vo!tages app!ied to these t#o transistors are a!so set to be comp!ementar"
signa!s$ As such' the CMOS T- operates as a bidirectiona! s#itch bet#een the nodes A and B
#hich is contro!!ed b" signa! C$
TANSMISION -AT. S7MBOLS
If the contro! signa! C is !ogic3high' i$e$' equa! to /00' then both transistors are turned
on and provide a !o#3resistance current path bet#een the nodes A and B$ If' on the other
hand' the contro! signa! C is !o#' then both transistors #i!! be off' and the path bet#een
the nodes A and B #i!! be an open circuit$ This condition is a!so ca!!ed the high3impedance
state$
The strength of a signa! is measured b" ho# c!ose!" it appro2imates an idea! vo!tage
source$ An nMOS transistor is an a!most perfect s#itch #hen passing a = and thus #e sa" it
passes a strong =$ )o#ever' the nMOS transistor is imperfect at passing a <$ The high
vo!tage !eve! is some#hat !ess than /00+/003/tn because of thresho!d drop1$ ,e sa" it
passes a degraded or #ea& <$ A pMOS transistor again has the opposite behavior' passing
strong <s but degraded =s+H/tpH because of thresho!d drop1$ ,hen an nMOS or pMOS is used
a!one as an imperfect s#itch' #e sometimes ca!! it a pass transistor$ B" combining an nMOS
and a pMOS transistor in #e obtain a s#itchin figure be!o# ' that turns on #hen a < is app!ied
to g in #hich =s and <s are both passed in an acceptab!e fashion$ ,e term this a tr#ns*!ss!&n
(#te &r p#ss (#te
9ig a1transmission gate structure$ 9ig b:.quiva!ent c&t depending on gate i*p$9ig C$passing =
AN0 < #hen T- is on$
E+u!#,lent res!s!st#nce &$ tr#ns*!ss!&n (#te pl&tte% #s # $unct!&n &$ !4p ,&lt#(e

eq
F
eqn
HH
eqp

eqF.quiva!ent resistance of nMOS

eqnF.quiva!ent resistance of pMOS

eqpF.quiva!ent resistance of transmission gate


esistance offered b" transmission gate is a!most a constant irrespective of i*p vo!tage$
App!ication
%sed in !ogic circuits !i&e mu2
%sed in !ogic circuits !i&e !atches
Transmission gate realization of boolean expressions
Transmission gates consists of NMOS and PMOS pass transistors
in parallel with nmos and pmos controllled by control signals of
opposite polarity.
1)2 I/p XOR ->F=A! "A!
#o$ to %ra$ t&e 'ir'(it
% need to rea!i(e t#o e2pressions to rea!i(e 2or$+ABI and AIB1
So T).. S)O%L0 B. T,O TANSMISSION -AT.S IN
CIC%IT$
Ta&e one of the t#o variab!es A or B as contro! input of each
transmission gate$
9or eg $If A is ta&en AS CONTOL I*P ther shou!d be provision for
passing BI #hen AF< AN0 B #hen AF=$
One T- shou!d turn on #hen AF< AN0 OT). S)O%L0
T%N ON #hen AF=$
-ate contro! input for one transmission gate shou!d be such that A
is tied to gate of nmos AN0 AI is tied to gate of PMOS$,hen AF<
this T- #i!! turn ON$and the i*p to be connected to this T- is BI $
+hence ,).N AF<'BI is passed as this T- turns on1
-ate contro! input for second transmission gate shou!d be such
that AI is tied to gate of nmos AN0 A is tied to gate of
PMOS$hence #hen AF= this T- #i!! turn ON$and the i*p to be
connected to this T- is B $ hence ,).N AF='B is passed as T-
turns on1
Both these transmission gates are o*ps are tied together'hence either
B or BI is passd depending on AF= or AF< respective!"
)*T 'onsists of a transmission gate an% an in+erter,
-#./ !=01T2 t(rns on 1A is passe% to o/p,-#./ !=1,T2 t(rns
OFF,A i/p is b3passe% t&ro(g& t&e ot&er pat& an% a+ailable as i/p
to in+erter,4o(r'e of 56O4 is 'onne'te% to 1 7!=1) an% 4O8R).
OF /6O4 I4 )O//.)T.9 TO 2RO8/97!=0),&en'e in+erter $ill be
f(n'tional an% it in+erts $&ate+er is applie% as inp(t to t&e 'ir(it,
#./). -#./ !=1 A 7A is in+erte% b3 in+erter se'tion1 T2 is o:)
is passe% to o/p,
-&en !=0, A is passe% to o/p as T2 is on,7in+erter is not
f('tioning at t&is moment)
#./). I65;.6./T.9 A!" A!
A e2pressions to be rea!i(ed$So A paths fromi*p to o*p
.ach I*p shou!d be passed to o*p 0.P.N0IN- ON /AL%.S O9 both S< ad S=$So t#o transmission
gates one #ith triggering i*p s< and other #ith triggering i*p S= are connected in seies for passing
each input to 7 $O*P is either of four i*ps $hence each case shou!d be connected in para!!e!$
To a+oi% t&e <oating o/p for
t&e i/p 'ombination 4241 1$e
$ill a%% one more expression
0,42417/O )#A/2. TO ORI2I/A; .X5R.44IO/),#./). -#./
42=41=110 is passe% to o/p
(USE TRNSM!SS!ON "TE S#M$% U &'E STU(!E( NOT T&!S ONE)
F=A!" A!)" A)
=A7!"!))"A)
!,=99 "!) =!,1"!) =!"!) is implemente% b3 (pper t$o pat&s,T&en
it is gi+en as i/p to anot&er T2 $&i'& t(rns on -#./ A=1, T#./
A7!"!)) is obtaine%,its o/p is tie% $it& bottom pat& t&at implements
A),&en'e A7!"!))"A) is implemente%,
)6O4 I65;.6./TATIO/
*OR
C&*ple*ent#r2 p#ss tr#ns!st&r l&(!c6CPL9&r 5!$$erent!#l p#sss tr#ns!st&r l&(!c
The main idea behind CPL is to use a pure!" nMOS pass3transistor net#or& for the !ogic
operations' instead of a CMOS T- net#or&$ A!! inputs are app!ied in comp!ementar" form'
i$e$' ever" input signa! and its inverse must be providedK the circuit a!so produces
comp!ementar" outputs' to be used b" subsequent CPL stages$ Thus' the CPL circuit
essentia!!" consists of comp!ementar" inputs' an nMOS pass transistor !ogic net#or& to
generate comp!ementar" outputs' and CMOS output inverters to restore the output
signa!s$
Basic b!oc& diagram for CPL circuits #ith t#o i*p variab!es is sho#n above$
A%,#nt#(es
The comp!e2it" of fu!!3CMOS pass3gate !ogic circuits can be reduced dramatica!!" $
The e!imination of pMOS transistors from the pass3gate net#or& significant!" reduces
the parasitic capacitances associated #ith each node in the circuit' thus' the operation
speed is t"pica!!" higher compared to a fu!!3CMOS counterpart$
5!s#%,#nt#(e
But the improvement in transient characteristics comes at a price of increased process
comp!e2it"$In CPL circuits' the thresho!d vo!tages of the nMOS transistors in the
pass3gate net#or& must be reduced to about = / through thresho!d3ad8ustment
imp!ants' in order to e!iminate the thresho!d3vo!tage drop+ If /tnF='#hen i*p is
<'O*PF/dd3/tnF/dd 1
5es!(n &$ CPL NAN50 #n% NOR0
NAN053LMAP NO53LMAP

9ig a3CPL NAN05 9ig b 4CPL NO5$
CPL 7OR


S)!$ter
N "!t s)!$ter s)&ul% "e#"le t& s)!$t up t& n-1 pl#ces !n r!()t s)$t &r le$t s)!$t
%!rect!&n
T)e : "!t s)!$ter *ust )#,e
!4p $r&* # : l!ne p#r#llel %#t# "us
: &4p l!nes $&r t)e s)!$te% %#t#
Me#ns &$ tr#ns$err!n( !4p %#t# t& &4p l!nes w!t) #n2 s)!$t $r&* ; t& <
"!ts-P#ss tr#ns!st&rs &r Tr#ns*!ss!&n (#tes
5#t# $l&ws )&r!=&nt#ll2 > c&ntr&l s(ls $l&w ,ert!c#ll2
An2 !4p l!ne c&nnecte% t& #n2 &r #ll &4p l!nes
:': cr&ss"#r sw!tc) #rr#n(e*ent $&r s)!$ter
5e*er!ts
!$ #ll s4ws cl&se%? #ll !4p@s c&nnecte% t& #ll &4p@s
1A c&ntr&l s(ls nee%e%
B#rrel s)!$ter
C&uple (#tes !n (r&ups &$ : > : sep#r#te (r&ups $&r s);?1?0?< "!ts
4&ift /
o/p
O(t
0
O(t
1
O(t
2
O(t
>
Sh
+
In
0
In
1
In
2
!n
,
Sh
-
!n
,
In
0
In
1
!n
.
Sh
.
!n
.
!n
,
In
0
In
1
Sh
,
In
1
In
2
!n
,
In
0
St!c- 5!#(r#*s
St!c- 5!#(r#*s use% t& c&n,e2 l#2er !n$&r*#t!&n t)r&u() t)e use &$ # c&l&r c&%e/
C&*p&nents !n CMOS tec)n&l&(2
+ia )onne'tion bet$een
metal la3ers
9emar'atio
n line
///////////////
//($RO0N)
5$ell e%ge
=99 or =44
'onta't
4(bstrate/$ell
'onta't
L#2ers IN STIC8 5IAGRAM
Met#l
T#o t"pes of meta! are used to represent the supp!" rai!s meta!< +b!ue 1 or meta!5 +purp!e 1
P&l2s!l!c&n
Po!"si!icon + red1 is used to represent the gate$
n-t2pe %!$$us!&n
n3t"pe diffusion + green1 is used to represent the source and drain n3transistors$
p-t2pe %!$$us!&n
p3t"pe diffusion +"e!!o# 1 is used to represent the source and drain p3transistors$
C&nt#cts
Contacts + b!ac&1 are used to represent e!ectrica! connections$+eg diffusion to meta!'or
po!"si!icon to meta!1
3!#
Cuts ca!!ed vias are used to ma&e contact bet#een t#o meta! !a"ers
CMOS B&!n!n( Rules
C)ere,er POLYSILICON 6re%9 cr&ss 5IFFUSION 6(reen9 #n n-tr#ns!st&rs !s
$&r*e% #n% p-tr#ns!st&r !s $&r*e% w)ere,er POLYSILICON 6re%9 cr&ss
5IFFUION 62ell&w9
5!$$us!&ns &$ t)e &pp&s!te t2pes c#nn&t cr&ss #n% c&nt#ct
Met#l c#n cr&ss p&l2s!l!c&n &r %!$$us!&n w!t)&ut #n2 s!(n!$!c#nt e$$ect
p #n% n %!$$us!&n w!res *ust n&t %!rectl2 D&!n e#c) &t)er n&r *#2 t)e2 cr&ss
pwell &r nwell "&un%#r2 !e %!$$us!&n s)&ul% n&t cr&ss %e*#rc#t!&n l!ne !n st!c-
%!#(r#*
Met#l1 6"lue9 c#n c&nt#ct *et#l0 6purple9? "ut ,!# !s nee%e%
S!*ple c&nt#cts c#n "e use% t& c&nnect %!$$us!&n &r p&l2s!l!c&n t& *et#l
Onl2 *et#l #n% p&l2s!l!c&n c#n cr&ss %e*#rc#t!&n l!ne
E(-
CMOS IN3ERTER6us!n( pwell pr&cess9
6POINTS TO BE CONSI5ERE5 IN 5RACING STIC8 5IGRAM9
n > p tr#ns!st&rs #re sep#r#te% "2 5e*#rc#t!&n l!ne
Pl#ce cr&sses &n 355 > 3SS r#!ls &ne e#c) $&r e,er2 p > n tr#ns!st&rs/
5!$$us!&n p#t)s *ust n&t cr&ss 5e*#rc#t!&n l!ne
n-%!$$us!&n > p-%!$$us!&n w!res *ust n&t D&!n
Onl2 Met#l > p&l2s!l!c&n c#n cr&ss 5e*#rc#t!&n l!ne
Steps t& %r#w CMOS !n,erter st!c- %!#(r#*
5r#w 355 #n% 3SS p&wer suppl2 r#!ls/6tw& )&r!=&nt#l l!nes9 C#n "e %r#wn
us!n( *et#l1 &r *et#l 0/Here *et#l 1 !s use% 6"lue9/
5r#w n %!$$us!&n6(reen9 #n% p %!$$us!&n62ell&w9 "el&w #n% #"&,e t)e
%e*#rc#t!&n l!ne/5!$$us!&n !s cr&sse% "2 p&l2s!l!c&n 6(#te9t& $&r* n*OS #n%
pMOs respect!,el2/s&urse &$ nMOS !s c&nnecte% t& 3SS ?s&urce &$ p*&s !s
c&nnecte% t& 355/5!$$us!&n c&nnecte% w!t) *et#l s& c&nt#ct !s re+u!re%/
G#te &$ n*&s #n% p*&s !s D&!ne% #n% c&nnecte% t& !nput/6p&l2s!l!c&n c#n "e use%
$&r s!(n#l w!res e( !4p?&4p etc9/s& n& c&nt#ct !s re+u!re% t& c&nnect (#te t& !nput/
5r#!ns &$ tr#ns!st&rs #re c&nnecte% us!n( *et#l #n% &utput !s t#-en/e!t)er
p&l2s!l!c&n &r *et#l c#n "e use% $&r &utput l!ne/I$ *et#l !s use% s!*pl2 e'ten%
*et#l c&nnect!&n "4w tw& %r#!ns/I$ p&l2s!l!c&n !s use% *#-e # c&nt#ct w)ere
p&l2s!l!c&n c&nt#cts *et#l/
5e*#rc#t!&n l!ne !s s)&wn w)!c) s)&ws pwell e%(e/It seper#tes n su"str#te !n
w)!c) p*&s !s $#"r!c#te% #n% n*&s !n pwell/
5r#w su"str#te c&nt#ct6355 CONTACT9 #n% well c&nt#ct63SS
CONTACT9/SINCE HERE P-CELL PROCESS IS USE5
BLUE METAL 1
YELLOC PE5IFFUSION
GREEN NE5IFFUSION
-- - - -- --- --- -- 5EMARCATION LINE
355 OR 3SS CONTACT
CONTACT
0I4P CMOS NOR GATE
0 I4P CMOS NAN5
I*ple*ent
Pr&ce%ure $&ll&we% t& %r#w st!c- %!#(r#* !n #ltern#te *et)&%
0ra# /00 and /SS po#er rai!s+S)O%L0 M. MAL.0 AS /00 AN0 /SS1
0ra# %e*#rc#t!&n l!ne mar&ing p#e!! edge+BO,N1
0ra# p %!$$us!&n hori(onta! straight !ine+ 7.LLO,1
0ra# n %!$$us!&n hori(onta! straight !ine+-..N1
0ra# p&l2s!l!c&n (#tes +.01 vertica! straight !ine crossing n and p diffusion as
man" times as no :of input variab!es$for e2amp!e for n variab!e e2pression n nmos
and n pmos transistors are formed$
Source and drain of nmos and pmos are connected b" *et#l l!nes +BL%.1 to obtain
para!!e! and series combination of transiostors so formed as per transistor
schematic$,henever meta! is connected to diffuision contact is made$
.2amp!es sho#n
7FABC
7FA6BC
7FAB6C0
<!nput NAN5
NMOS 5ESIGN STYLE
6MO5ULE-< SPECIFIE5 IN UR SYLABUS 5EALS CITH CMOS/ BUT THERE IS
NMOS 5ESIGN STYLE IN UR TE7T/ CMOS 5ESIGN IS 5ERI3E5 FRM NMOS
CITH SLIGHT CHANGES/I 5I5N@T TELL ANYTHING ABOUT NMOS IN CLASS
SO THAT U CONT BE CONFUSE5/HERE I HA3E INCLU5E5 ITS BASICS 9
NMOS LOGIC CIRCUITS HA3E NMOS PULL5OCN NETCOR8
IMPLEMENTING LOGIC FUNCTION/AN5 NMOS 5EPLETION MO5E
TRANSISTOR IN PULLUP NETCOR8/5EPLETION MO5E TRANSISTOR !s
s)&wn !n %!#(r#* #s # tr#ns!st&r w!t) (#te s)&rte% t& s&urce &$ n*&s/
G#te c&nnecte% t& s&urce &$ n*&s pull up tr#ns!st&r "2 "urr!e% c&nt#ct/T& s)&w #
%eplet!&n *&%e tr#ns!st&r 2ell&w !*pl#nt !s s)&wn w)!c) !n%!c#tes c)#nnel !s !*pl#nte%/
6%eplet!&n *&%e tr#ns!st&r )#s c)#nnel !*pl#nte% #t t!*e &$ $#"r!c#t!&n9
N*&s IN3ERTER
NMOS NAN5