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Nathaniel Kan

2/10/02

ABSTRACT:

In the Digital Logic lab we became familiar with integrated circuits in the form of logic

gates. We verified the truth table of a NAND gate, and constructed and verified the truth

tables of an OR gate and an EXCLUSIVE OR gate. We then constructed and verified the

truth tables of an RS latch, a half adder circuit, and a counting circuit, which was

connected to a seven segment LED display. We found all these circuits to work as

according to their pre-determined truth tables.

PURPOSE:

The purpose of the Digital Logic lab was to familiarize ourselves with the use of digital

logic gates. We first became familiar with the ranges of voltages representing high and

low, the use of a logic breadboard, and the functions of NOT, NAND, and NOR gates. We

then were to construct several more complex circuits, including a memory circuit, an

arithmetic circuit, and a counting circuit.

PRINCIPLES:

In this lab we were primarily working with Integrated Circuits in the Transistor-Transistor-

Logic family. These circuits use two logic levels to report results, corresponding to two

voltage ranges:

0= False = Low = approx. 0 to 0.8 V

For this experiment we use a breadboard, which contains many common circuit elements

as well as a holding area which provides easy wiring into the IC chips (See C1 Lab

handout page 3 for diagram).

PROCEDURE:

We began by checking the functionality of all components of the breadboard including the

power source, the LEDs, the clock signal, and the switches. We then tested the NAND

gates on one of the IC circuits by connecting their inputs to two switches, and their outputs

to an LED. Pin 14 and Pin 7 are connected to the positive and ground terminals of the

power supply, respectively. We then verified that the actual truth table was a duplicate of

the predicted one (See Data section).

Next we constructed the OR gate and the EXCLUSIVE OR gate (See Lab book page 53

for diagrams). The OR gate produces a result of True if either input A or B is True, or both

are True. The EXCLUSIVE OR gate produces a result of True if input A or B is True, but

1

False if A and B are both True or both False. We then verified that their truth tables

matched up to the theoretical ones. We then used our knowledge of IC circuits to design a

circuit to solve the Part 4 Logic Problem (See Data section).

The next circuit was the RS latch (see Lab book page 54 for diagram). This circuit, because

it is a feed back loop between two NAND gates, has two stable settings, Q = 0 and Q’ = 1,

or Q = 1 and Q’ = 0. These settings will be maintained in “memory” until a new stable

setting is inputted. If both R and S inputs are set to True, the circuit will continue in its

stable 1,0 or 0,1 setting. If both inputs are set to False, then the circuit will temporarily go

high, but then return to its stable setting.

Next we constructed a half-adder digital arithmetic circuit (Lab book page 55). This circuit

adds two binary digits (1 or 0) together in binary, where the QF is the tens digit and C is the

unit digit. We then verified the circuits’ truth table.

The last circuit we constructed was a counting circuit, using the 7490 chip. By connecting

the A B C D outputs to LEDs, the powered chip counts from 0 to 9 in binary through

turning the LEDs on and off (see C1 Lab handout page 7 for diagram). After verifying this,

we then connected the counting circuit to a seven segment LED. The LEDs are arranged

such that when lit properly they form numbers from 0 to 9. The circuits inside the LED

holding box allowed the 7490 chip to be connected directly to the box through four

contacts, which then connected through logic gates to the LEDs, lighting the correct LEDs

to produce the numbers 0 through 9 in correct succession.

DATA:

A B QA QB QF

0 0 1 1 0

1 1 0 0 1

1 0 0 1 1

0 1 1 0 1

A B Q1 Q2 Q3 QF

0 0 1 1 1 0

1 1 0 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

Part 2C Problem-Solving Circuit Truth Table (See Lab book page 54 for circuit diagram)

2

A B C Q1 Q2 QF

0 1 1 1 0 1

1 0 1 1 0 1

1 1 1 1 0 1

0 0 1 0 1 0

0 1 0 1 1 0

1 0 0 1 1 0

1 1 0 1 1 0

0 0 0 0 1 0

R S QR QS

0 0 1 1

0 1 0 1

1 0 1 0

1 1 Q Q

A B Q1 Q2 Q3 QF C

0 0 1 1 1 0 0

1 0 0 1 1 0 1

0 1 0 1 1 0 1

1 1 1 0 1 1 0

RESULTS:

When the LED is connected through the clock signal, the diode flashes at the same

frequency as the signal. This is because the diode does not allow the negative current to

flow, but does allow the positive current through. This means that the current oscillates

between off and on at the frequency of the clock.

All the circuits we constructed matched their logically predicted truth tables (after we had

corrected all construction errors). In constructing the circuit to solve the Part 2C problem,

we used an OR gate with the two inputs being A and B, and then used the result of that, Q1

and C in a NAND gate which fed its result, Q2, into both inputs of another NAND gate,

which outputs the answer, Q3.

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