EURASIP Journal on Applied Signal Processing 2005:18, 3076–3086

c 2005 C. Charoensak and F. Sattar
Design of Low-Cost FPGA Hardware for Real-time
ICA-Based Blind Source Separation Algorithm
Charayaphan Charoensak
School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798
Email: ecchara@ntu.edu.sg
Farook Sattar
School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798
Email: efsattar@ntu.edu.sg
Received 29 April 2004; Revised 7 January 2005
Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multi-
sensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a
real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture
offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The
FPGA design implements the modified Torkkola’s BSS algorithm for audio signals based on ICA (independent component analy-
sis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the
feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster conver-
gence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented.
Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given.
Keywords and phrases: ICA, BSS, codesign, FPGA.
1. INTRODUCTION
Blind signal separation, or BSS, refers to performing inverse
channel estimation despite having no knowledge about the
true channel (or mixing filter) [1, 2, 3, 4, 5]. BSS technique
has been found to be very useful in many real-world mul-
tisensor applications such as blind equalization, fetal ECG
detection, and hearing aid. BSS method based on ICA tech-
nique has been found effective and thus commonly used
[6, 7]. A limitation using ICA technique is the need for long
unmixing filters in order to estimate inverse channels [1].
Here, we propose the use of noncausal filters [6] to shorten
the filter length. In addition to that, using noncausal filters
in the feedback network allows a good separation even in the
case where the direct channels filters do not have stable in-
verses. A variable step-size parameter for adaptation of the
learning process is introduced here to provide a fast and sta-
ble convergence.
FPGA architecture allows optimal parallelism needed to
handle the high computation load of BSS algorithm in real
This is an open access article distributed under the Creative Commons
Attribution License, which permits unrestricted use, distribution, and
reproduction in any medium, provided the original work is properly cited.
time. Being fully custom-programmable, FPGA offers rapid
hardware prototyping of DSP algorithms. The recent ad-
vances in IC processing technology and innovations in the
architecture have made FPGA a suitable alternative to using
powerful but expensive computing platform.
In spite of its potential for real-world applications, there
have been very few published papers on real-time hardware
implementation of the BSS algorithm. Many of the works
such as [8] focus on the VLSI implementation and do not
provide a detailed set of specifications of the BSS imple-
mentation that offer a good balance between hardware re-
quirement (gate count and minimal clock speed) and sepa-
ration performance. Here, we propose an efficient hardware
architecture that can be implemented using a low-cost FPGA
and yet offers a good blind source separation performance.
Extensive set of experimentations, discussion on separation
performance, and the proposal for future improvement are
presented.
The FPGA design process requires familiarity with the
associated signal processing. Furthermore, the developed
FPGA prototype needed to be verified, through both func-
tional simulation and real-time testing, in order to fully un-
derstand the advantages and pitfalls of the architecture under
investigation. Thus, an integrated system-level environment
FPGA Hardware for Real-time ICA-Based BSS 3077
for software-hardware co-design and verification is need-
ed. Here, we carried out FPGA design of a real-time
implementation of the ICA-based BSS using a new system-
level design tool called System Generator from Xilinx.
The rest of the paper is organized as follows. Section 2
provides an introduction to BSS algorithm and the appli-
cation of noncausal filters within the feedback network.
Section 3 describes the hardware architecture of our FPGA
design for the ICA-based BSS algorithm. Some critical issues
regarding the implementation of the BSS algorithm using
the limited hardware resources in the FPGA are discussed.
Section 4 presents the system level design of the FPGA fol-
lowed by detailed FPGA simulation results, synthesis result,
and the real-time experimentation of the final hardware us-
ing real environment setup. The summary and the motiva-
tions for future improvement are given in Section 5.
2. BACKGROUNDOF BSS ALGORITHM
2.1. Infomax or entropy maximization criterion
BSS is the main application of ICA, which aims at reducing
the redundancy between source signals. Bell and Sejnowski
[9] proposed an information-theoretic approach for BSS,
which is referred to as the Infomax algorithm.
2.2. Separation of convolutive mixture
The Infomax algorithm proposed by Bell and Sejnowski
works well only with instantaneous mixture and was further
extended by Torkkola for the convolutive mixture problem
[10]. As shown in Figure 1, minimizing the mutual informa-
tion between outputs u
1
and u
2
can be achieved by maximiz-
ing the total entropy at the output.
This architecture can be simplified by forcing W
11
and
W
22
to be mere scaling coefficients to achieve the relation-
ships shown below [6, 11]:
u
1
(t) = x
1
(t) +
L12
¸
k=0
w
12
(k)u
2
(t −k),
u
2
(t) = x
2
(t) +
L21
¸
k=0
w
21
(k)u
1
(t −k),
(1)
and the learning rules for the separation matrix:
∆w
i j

¸
1 −2y
i

u
j
(t −k). (2)
2.3. Modified ICA-based BSS method using modified
Torkkola’s feedback network
Torkkola’s algorithm works only when the stable inverse of
the direct channel filters exists. This is not always guaran-
teed in real-world systems. Considering the acoustical condi-
tion when the direct channel can be assumed a nonminimum
phase FIR filter, the impulse response of its stable inverse
will become noncausal infinite double-sided converging se-
X
2
X
1
Mixed
inputs
W
22
W
11
+
+
W
12
W
21
g(u) g(u)
Maximize
entropy
Adjust unmixing filter
coefficients, W
12
and W
21
U
1
U
2
Blind source
separation
output results
Figure 1: Torkkola’s feedback network for BSS.
quence, or a noncausal IIR filter. By truncating this non-
causal IIR filter, the stable noncausal FIR filter (W
12
or W
21
)
can be realized [12]. It was also shown in [6] that the algo-
rithm can be easily modified to use the noncausal unmix-
ing FIR filters. The relationships between the signals are now
changed to
u
1
(t) = x
1
(t + M) +
M−1
¸
k=−M
w
12
(k)u
2
(t −k), (3)
u
2
(t) = x
2
(t + M) +
M−1
¸
k=−M
w
21
(k)u
1
(t −k), (4)
where M is half of the filter length, L, that is, L = 2M +1 and
the learning rule
∆w
i j
(t
1
−p
1
+M)
= ∆w
i j
(t
0
−p
0
+M)
+ K
¸
u
i
¸
t
0

u
j
¸
p
0

, (5)
where
K
¸
u
i
¸
t
0

= λ
¸
1 −2y
i
¸
t
0

, (6)
y
i
¸
t
0

=
1
1 + e
−ui (t0)
,
t
1
= t
0
+ 1,
p
0
= t
0
−k for k = −M, −M + 1, . . ., M,
p
1
= t
1
−k for k = −M, −M + 1, . . ., M.
(7)
The term λ in (6) represents the variable learning step
size which is explained in more detail in Section 3.5.
3. ARCHITECTURE OF HARDWARE
FOR BSS ALGORITHM
The top-level block diagram of our hardware architecture for
the BSS algorithm based on Torkkola’s network is shown in
Figure 2. The descriptions for the subsystems in the figure
will be discussed in the following subsections. Some criti-
cal issues regarding the practical realization of the algorithm
while minimizing the hardware resources are discussed.
3078 EURASIP Journal on Applied Signal Processing
X
2
X
1
Unmixing
filters
W
Variable learning
stepping
Entropy
measurement
Feedback
network
U
1
U
2
Figure 2: Top-level block diagram of hardware architecture for BSS
algorithm based on Torkkola’s network.
3.1. Practical implementation of the modified
Torkkola’s network for FPGArealization
In order to understand the effect of each filter parameter such
as filter length (L) and learning step size on the separation
performance, a number of simulation programs written in
MATLAB were tested. A set of compromised specification is
then proposed for practical hardware realization [11].
As a result of our MATLAB simulations, we propose that
in order to reduce the FPGA resource needed, as well as to
ensure real-time BSS separation given the limited maximum
FPGA clock speed, the specifications shown below are to be
used. Sections 3.2 and 3.6 explain the impact of some param-
eters on hardware requirement in more details.
(i) Filter length, L = 161 taps.
(ii) Buffer size for iterative convolution, N = 2500.
(iii) Maximum number of iterations, I = 50.
(iv) Approximation of the exponential learning step size
using linear piecewise approximation.
The linear piecewise approximation is used to avoid com-
plex circuitry needed to implement the exponential func-
tion (see Section 3.5 for more explanation of implementa-
tion, and Section 4.2.1 for comparison of simulation results
using exponential function and linear piecewise function).
There are many papers discussing the effect of filter
length on the separation performance [13]. We have cho-
sen a smaller filter length considering the maximum operat-
ing speed of the FPGA and considered only the case of echo
of a small room. (See Section 3.6 for calculation of required
FPGA clock speed and Section 4.2.3 for the FPGA simulation
result.)
3.2. Three-buffer technique
In real-time hardware implementation, to achieve an unin-
terrupted processing, the hardware must process the input
and output as streams of continuous sample. However, this
is in contrast with the need of batch processing of BSS algo-
rithm [14]. To perform the separation, a block of data buffer
has to be filtered iteratively. Here, we implement a buffering
mechanism using three 2500-sample (N = 2500) buffers per
one input source. While one buffer is being filled with the in-
put data, a second buffer is being filtered, and the third buffer
is being streamed out.
A side effect of this three-buffer technique is that the sys-
tem produces a processing delay equivalent to twice the time
Address for W
W
12
Address for U
U
2
Address for X
X
2
Memory
blocks
MAC
(muliply
accumulate)
Register
Register
Enable
+
u
1
(t)
Figure 3: Implementation of (8) for the modified Tokkola’s feed-
back network.
needed to fill up a buffer. For example, if the signal sam-
pling frequency is 8000 Hz, the time to fill up one buffer is
2500/8000 = 0.31 second. The system will then need another
0.31 second to process before the result being ready for out-
put. The total delay is then 0.31+0.31 = 0.62 s. This process-
ing delay may be too long for many real-time applications. A
suggestion on applying overlapped processing windows, to-
gether with polyphase filter, in order to shorten this delay is
given in Section 5.
3.3. Implementation of feedback network mechanism
According to feedback network in (3), there is a need to ad-
dress negative addresses for the values of w
12
(i) when i < 0.
In practice, the equation is modified slightly to include only
positive addresses:
u
1
(t) = x
1
(t + M) +
M
¸
i=−M
w
12
(i + M)u
2
(t −i). (8)
Equation (8) performs the same noncausal filtering on
u
2
as in (3) without the need for negative addressing of w
12
.
Equation (4) is also modified accordingly.
The block diagram shown in Figure 3 depicts the hard-
ware implementation of (8). Note that the implementa-
tion of the FIR filtering of w
12
is done through multiply-
accumulate unit (MAC) which significantly reduces the
numbers of multipliers and adders needed when com-
pared to direct parallel implementation. The tradeoff is that
the FPGA has to operate at oversampling frequency (see
Section 3.6).
3.4. Mechanismfor learning the filter coefficients
The mechanism for learning of the filter coefficients was im-
plemented according to (5). The implementation of the vari-
able learning step size, λ, is explained in the next subsection.
3.5. Implementation of variable learning step size
In order to speed up the learning of the filter coefficients
shown in (5), we implement a simplified variable step-size
technique.
In our application, the variable learning step size in (6),
that is, the learning step size λ, may be implemented using
FPGA Hardware for Real-time ICA-Based BSS 3079
(9) below where n is the iteration level, λ
0
is the initial step
size, and I is the maximum number of iterations, that is, 50:
λ = exp

−u
0

n
I
¸
, (9)
where
u
0
= −log
2
¸
λ
0


1
I
. (10)
The exponential term is difficult to implement in digi-
tal hardware. Lookup table could be used but will require a
large block of ROM(read only memory). Alternative to using
lookup ROMis the CORDICalgorithm(COrdinate Rotation
DIgital Computer) [15]. However, circuitry for CORDIC
algorithm will impose a very long latency (if not heavily
pipelined) which will result in the need for even higher FPGA
clock speed. Instead, we used a linearly decreasing variable
step size as shown:
λ = 0.0006 −0.000012n. (11)
We had carried out MATLAB simulations to compare the
separation performance using exponential equation and lin-
ear piecewise term equation. It was found out that, using
the specifications given in Section 3.1, there is no significant
degradation in separation performance (see also simulation
results in Section 4.2.1). A multipoint piecewise approxima-
tion will be implemented in future improvement.
3.6. Calculation of the required FPGAclock speed
As mentioned earlier that in order to save hardware resource,
multiply-accumulate (MAC) technique is used. This implies
that MAC operation has to be done at a much higher rate
than that of the input sampling frequency. This MAC operat-
ing frequency is also the frequency of the FPGA clock. Thus,
a detailed analysis of the FPGA system clock needed for real-
time blind source separation is required.
The FPGA clock frequency can be calculated as shown in
(12) (see also [11]) where Fs is the sampling frequency of the
input signals, L is the tap length of the FIR filter, and I is the
number of iterations:
FPGA clock frequency = L · I · Fs. (12)
In our FPGA design, filter tap L = 161, iterations I = 50,
and input sampling frequency Fs = 8000 Hz; the FPGA clock
frequency is thus
161 · 50 · 8000 = 64.4 MHz. (13)
This means that the final FPGAdesign must operate properly
at 64.4 MHz. In practice, the maximum operating speed of a
hardware circuit can be optimized by analyzing the “critical
path” in the design. A more detailed analysis of the critical
path in the FPGA design is given in Section 4.1.2.
Note that the frequency 64.4 MHz also represents the
number of multiplications per second needed to perform the
blind source separation (per channel). This represents a very
large computation load if a general processor, or DSP (digital
signal processor), is to be used for real-time applications. Us-
ing fully hardware implementation, the performance gain is
easily obtained by bypassing the fetch-decode-execute over-
head, as well as by exploiting the inherent parallelism. FP-
GAs allow the above-mentioned advantage plus the repro-
grammability and cost effectiveness.
Some discussion on applying polyphase filter to increase
the filter length while maintaining the FPGA clock speed is
given in section 5.
4. SYSTEM-LEVEL DESIGNANDTESTINGOF THE
FPGA FOR BSS ALGORITHM
4.1. System-level design of FPGAfor BSS algorithm
System generator provides a bit-true and cycle-true FPGA
blocksets for functional simulation under MATLAB
Simulink environment thus offering a very convenient and
realistic system-level FPGA co-design and cosimulation.
Some preliminary theoretical results from MATLAB m-file
can directly be used as reference for verifying the FPGA
results (refer to [16] and http://www.xilinx.com/system
generator for more detailed description).
Note that the FPGA design using system generator is dif-
ferent from the more typical approach using HDL (hardware
description language) or schematics. Using system generator,
the FPGA is designed by means of Simulink models. Thus,
the FPGA functional simulation can be carried out easily
right inside Simulink environment. After the successful sim-
ulation, the synthesizable VHDL (VHSIC HDL where VH-
SIC is very-high-speed integrated circuit) code is automati-
cally generated from the models. As a result, one can define
an abstract representation of a system-level design and easily
transform it into a gate-level representation in FPGA.
The top level design of the ICA-based BSS algorithm
based on the described architecture is shown in Figure 4. As
can be seen from the figure, the FPGA reads in the data from
each wave file, and outputs the separated signals, as streams
of 16-bit data sample. The whole design is made up of many
subsystems. Here, a more detailed circuit design of the sub-
system which implements the computation for updating the
filter coefficients is shown in Figure 5.
The process of FPGA design is simplified. The Simulink
design environment also enhances the system-level software-
hardware co-design and verification. The upper right-hand
side of Figure 3 shows how to use Simulink “scope” to dis-
play the waveform generated by the FPGA during simula-
tion. This technique can be used to display the waveform
at any point in the FPGA circuitry. This offers a very prac-
tical way to implement a software-hardware co-design and
verification. Note also the use of the blockset “to wave file”
to transfer the simulation outputs from the FPGA back to a
wave file for further analysis.
3080 EURASIP Journal on Applied Signal Processing
System generator
From wave file
rss1 norm 1.wav
(8000 Hz/1 Ch/16 b)
From wave file
From wave file
rss2 norm 1.wav
(8000 Hz/1 Ch/16 b)
From wave file
Dbl Fpt
Gateway in
Dbl Fpt
Gateway in
Gateway out
Gateway out
New u
1
u
1
New u
2
u
2
Input 1 Out 1
Input 2 Out 2 Fpt Dbl
Dbl Fpt
T:[0 0], D:0 Probe
Terminator
try x2c.wav
To wave file 1
try x1c.wav
To wave file
Time scope 1
Time scope
Figure 4: Top-level design of BSS using system generator under MATLAB Simulink.
Sel
D0
D1
Sel
D0
D1
Sel
D0
D1
3
Addr
Delay
And
Delay
And Delay
Addr muxb
Delay
Addr muxa
Addr
Data Wa
We
Wa
Addr
Data Wa
We
Wb
Mem out mux
1
Out1
Figure 5: Detailed circuit for updating the filter coefficients.
4.1.1. Using fixed-point arithmetic in FPGA
implementation
When simulating a DSP algorithm using programming lan-
guages such as C and MATLAB, double precision floating
point numeric system is commonly used. In hardware im-
plementation, fixed-point format numeric is more practical.
Although several groups have implemented floating-point
adders and multipliers using FPGA devices, very few practi-
cal systems have been reported [17]. The main disadvantages
of using floating point in FPGA hardware are higher resource
requirements, higher clock frequency, and longer design time
than an equivalent fixed-point system.
For fixed filters, the analysis of the effect of fixed-point
arithmetic on the filter performance has been well presented
in other publications [18, 19]. An analysis of word length ef-
fect on the adaptation of LMS algorithm is given in [18].
We use only fixed-point arithmetic in our design. As
mentioned earlier, we use 16-bit fixed-point at the inputs and
outputs of our FPGA design. In practice, depending on the
applications, the size of data width should be selected taking
into account the desired system performance and FPGA gate
count. In terms of separation performance, it can be shown
that word length of the accumulator unit in the MAC unit is
most critical. Using system generator, it is easy to study the
effect of round-off error on the overall system performance
and that helps in selecting the optimal bit size in the final
FPGA design.
4.1.2. Analysis of critical path in FPGAimplementation
of BSS algorithm
It was shown in Section 3.6 that in order for the FPGAto per-
form the blind source separation in real time, the required
FPGA Hardware for Real-time ICA-Based BSS 3081
x
y
∗ + Delay
MAC out
Figure 6: Simplified block diagram of MAC operation.
clock frequency is 64.4 MHz. We will now analyze the criti-
cal paths in the ICA-based BSS design in order to verify that
the clock frequency can be met. Referring to Figures 1 and 2,
one can see that the maximum operating speed of the FPGA
is determined by the critical path in the multiply-accumulate
blocks. The propagation delay in this critical path is the sum-
mation of the combinational delay made up of one multiplier
and one adder as shown in the simplified block diagram in
Figure 6. Based on Xilinx data sheet of Virtex-E FPGA, de-
lays of the dedicated pipeline multiplier and adder units are
(i) delay of 16-bits adder: 4.3 nanoseconds,
(ii) delay of pipelined 16-bit multiplier: 6.3 nanoseconds.
Thus, we can approximate the total delays in the criti-
cal path to be 4.3 + 6.3 = 10.6 nanoseconds, which converts
to 94 MHz maximum FPGA clock frequency. This is much
higher than the required 64.4 MHz needed. Note that this is
only an approximation and we mention it here for the pur-
pose of discussion about our BSS architecture. The accurate
maximumclock speed can easily be extracted fromthe FPGA
synthesis result which is given in Section 4.3. Note also that
the available dedicated multipliers depend very much on the
FPGA family and the size of device used.
4.2. Simulation results of the FPGAdesign for
ICA-based BSS
We carried out experimentations using different wave files,
all sampled at 8000 Hz, and with various types of mixing
conditions. The output separation performance results were
measured.
4.2.1. FPGAsimulation using two female voices
In this simulation, we use wave files of two female voices.
Each file is approximately one-second long, with sampling
frequency of 8000 samples per second, and 16 bits per sam-
ple. The files were preprocessed to remove dc component
and amplitude normalized. The two original input voices are
shown in Figures 7a and 7b, respectively.
To simulate the mixing process, the two inputs were pro-
cessed using the instantaneous mixing program called “in-
stamix.m” downloaded from the website http://www.ele.tue.
nl/ica99 given in [20]. The mixing matrix used is [0.6 1.0, 1.0
0.6]. The two mixed voices are shown in Figures 8a and 8b.
The separation results from the FPGA simulation are
shown in Figures 9 and 10. The separated outputs are shown
in Figures 9a and 9b. By comparing the separated out-
put voice in Figure 9a to the corresponding mixed voice in
Figure 8a, the separation is clearly visible. By listening to the
0 1000 2000 3000 4000 5000 6000 7000 8000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(a)
0 1000 2000 3000 4000 5000 6000 7000 8000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(b)
Figure 7: Two original female voices used for FPGA simulations:
(a) first female voice and (b) second female voice.
output, the voice is much more intelligible. Similar conclu-
sion can be drawn for the other voice (the measurements to
show the separation performance are given in the next sub-
section).
The error of the separated first female voice, measured by
subtracting the output in Figure 9a fromthe original input in
Figure 7a, is shown in Figure 10a. Figure 10b shows error of
the second voice.
Figures 11a and 11b show the FPGA simulation results
using linear piecewise function, compared to exponential
function shown in (7). Figure 11a shows the plot of learning
step sizes, using exponential function and linear piecewise
function, against number of iterations. Figure 11b compares
the averaged changes of filter coefficients ∆w
12
and ∆w
21
, for
all the 161 taps, plotted against number of iterations. It can
be seen that, for the maximum number of iterations used
(= 50), both the learning step size using exponential func-
tion and the learning step size using linear piecewise function
converge to zeros properly.
4.2.2. FPGAsimulation using one female voice mixed
with Gaussian noise
A second experiment was carried out to measure the sepa-
ration performance of the FPGA under noisy environment
[21]. The first female voice used in the last experimentation
3082 EURASIP Journal on Applied Signal Processing
0 1000 2000 3000 4000 5000 6000 7000 8000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(a)
0 1000 2000 3000 4000 5000 6000 7000 8000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(b)
Figure 8: Two mixed female voices used for FPGA simulation. The
program “instamix.m” downloaded from http://www.ele.tue.nl/
ica99 is used; (a) mixed first signal and (b) mixed second input.
was mixed with white Gaussian noise (see Figure 12) and the
signal-to-noise ratios (SNRs), before and after the BSS opera-
tion by the designed FPGA, were measured. The same mixing
matrix [0.6 1.0, 1.0 0.6] was used. By adjusting the variance
of the white Gaussian noise source, σ
2
, the input SNR varies
in the range −9 dB to 10 dB.
The input signal-to-noise ratio, SNRi, is defined in this
experimentation as
SNRi (dB) = 10 log
¸
¸
T
i=1
x
2
1
(i)
¸
T
i=1
x
2
2
(i)

. (14)
Here, T is the total number of samples in the time period
of measurement and x
1
(i) and x
2
(i) are the original female
voice and the white Gaussian noise respectively.
Similarly, the output signal-to-noise ratio, SNRo, is de-
fined in (15). e
1
(i) represents the overall noise left in the first
separated output u
1
and defined as e
1
(i) = u
1
(i) − x
1
(i) as
shown in Figure 12:
SNRo (dB) = 10 log
¸
¸
T
i=1
x
2
1
(i)
¸
T
i=1
e
2
1
(i)

. (15)
0 1000 2000 3000 4000 5000 6000 7000 8000 9000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(a)
0 1000 2000 3000 4000 5000 6000 7000 8000 9000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(b)
Figure 9: Two separated voices from FPGA simulation; (a) sepa-
rated first voice and (b) separated second voice.
The improvement of SNR after BSS processing, SNRimp
(dB), is defined as
SNRimp (dB) = 10 log
¸
¸
T
i=1
x
2
2
(i)
¸
T
i=1
e
2
1
(i)

. (16)
The result in Figure 13 shows the averaged output SNRs
and the average improvement of SNRs plotted against input
SNRs. It can be seen that as the input SNRs varies, the out-
put SNRs is almost the constant at approximately 35 dB. The
maximum achievable out SNRs is limited by the width of the
datapath implemented inside the FPGA. Due to this reason,
the amount of improvement of SNRs decreases with the in-
creasing input SNRs.
4.2.3. FPGAsimulation using two female voices mixed
using simulated roomenvironment
Next experimentation was carried out to measure separation
performance of the designed FPGA under realistic room en-
vironment using the same two female voices. The room envi-
ronment was simulated using the program “simroommix.m”
downloaded from the same website mentioned earlier. The
coordinates (in meter) of the first and second signal sources
FPGA Hardware for Real-time ICA-Based BSS 3083
0 1000 2000 3000 4000 5000 6000 7000 8000 9000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(a)
0 1000 2000 3000 4000 5000 6000 7000 8000 9000
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
(b)
Figure 10: Error of the two separated voices; (a) error of separated
first voice and (b) error of separated second voice.
are (2, 2, 2) and (3, 4, 2) respectively. The locations of the first
and second microphone are (3.5, 2, 2) and (4, 3, 2) respec-
tively. The room size is 5 × 5 × 5. The simulated room ar-
rangement is shown in Figure 14.
The measurement of separation performance is based on
using (17) (see [20]). Here, S
j
is the separation performance
of the jth separated output where u
j,x j
is the jth output of
the cascaded mixing/unmixing system when only input x
j
is
active; E[u] represents the expected value of u:
S
j
= 10 log

¸
¸
E
¸
¸
u
j,xj

2
¸
E
¸
¸ ¸
i=j
u
j,xi

2
¸

. (17)
The program “bsep.m,” which performs the computation
as shown in (17), was downloaded from the website and used
to test our FPGA. It was found that before the BSS,
S
1
= 17.29 dB, S
2
= 10.63 dB, (18)
and after the BSS operation,
S
1
= 20.29 dB, S
2
= 16.53 dB. (19)
Thus, the BSS hardware improves the separation by 3 dB
and 5.9 dB for channels 1 and 2, respectively. The figures may
not appear very high. However, by listening to the separated
output signals, the improvement was obvious and further
5 10 15 20 25 30 35 40 45 50
Iteration number
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
×10
−3
L
e
a
r
n
i
n
g
s
t
e
p
s
i
z
e
Exponential function
Linear piecewise function
(a)
5 10 15 20 25 30 35 40 45 50
Iteration number
0
0.005
0.01
0.015
A
v
e
r
a
g
e
c
h
a
n
g
e
s
o
f

l
t
e
r
c
o
e

c
i
e
n
t
s
Exponential function
Linear piecewise function
(b)
Figure 11: (a) Learning step sizes using exponential and linear
piecewise functions and (b) averaged changes of filter coefficients
∆w
12
and ∆w
21
using the two functions.
White Gaussian
noise source
with adjustable
variance
First female
voice wave file Mixing
matrix
¸
0.6 1.0
1.0 0.6

Delay
FPGA
design
of BSS
algorithm
u
1
e
1
− +
+
u
2
x
1
x
2
Figure 12: FPGA simulation to test BSS using one female voice
mixed with white Gaussian noise with adjustable variance σ
2
.
improvement can be made by increasing the filter lengths.
Note also that the measurements of separation performance
and the improvement after the BSS depend very much on the
room arrangement.
4.2.4. FPGAsimulation using convolutive
mixture of voices
In order to test the FPGA using convolutive mixtures
recorded in a real cocktail party effect, two samples voices
were downloaded from a website (T-W Lee’s website
3084 EURASIP Journal on Applied Signal Processing
−10 −8 −6 −4 −2 0 2 4 6 8
Input SNRs (dB)
20
25
30
35
40
45
O
u
t
p
u
t
S
N
R
s
a
n
d
i
m
p
r
o
v
e
m
e
n
t
o
f
S
N
R
s
Output SNRs
Improvement of SNRs after BSS
Figure 13: Results of SNR measurements using one female voice
mixed with white Gaussian noise. The figure shows the output SNRs
and the improvement of SNRs against the input SNRs.
5
4
3
2
1
0
L
e
n
g
t
h
(
5
m
)
0
1
2
3
4
5
W
id
th
(5
m
)
0
1
2
3
4
5
H
e
i
g
h
t
(
5
m
)
Voice 2
Voice 1
Microphone 2
Microphone 1
Figure 14: Arrangement of female voice sources and microphones
in simulated room environment using program “simroommix.m.”
at http://inc2.ucsd.edu/∼tewon/) and used in the FPGA
simulation. The two wave files used were from two speak-
ers recorded speaking simultaneously. Speaker 1 counts
the digits from one to ten in English and speaker 2
counts in Spanish. The recording was done in a nor-
mal office room. The distance between the speakers and
the microphones was about 60 cm in a square ordering.
A commercial program was used to resample the original
sampling rate of 16 kHz down to 8000 Hz. The separation re-
sults from the developed FPGA can be found at our website
(http://www.ntu.edu.sg/home/ecchara/—click project on the
left frame). Note that we present a real-time experimentation
using these convolutive mixtures in Section 4.4. We have also
posted the separation results of the same convolutive mix-
tures using MATLAB program at the same website for com-
parison.
Because the original wave files (before the convolutive
mixing) were not available, we could not perform the mea-
Table 1: Detailed gate requirement of the BSS FPGA design.
Number of slices for logic 550
Number of slices for flip flops 405
Number of 4 input LUTs 3002
used as LUTs 2030
used as a route-thru 450
used as shift registers 522
Total equivalent gate count for the design 100 213
Table 2: Maximum combinational path delay and operating fre-
quency of the FPGA design for BSS.
Maximum path delay from/to any node 15.8 ns
Maximum operating frequency 71.2 MHz
surement of the separation performance. However, by listen-
ing to the separated outputs, we notice approximately the
same level of separation as in our earlier experimentations.
4.3. FPGAsynthesis result
After the successful simulation, the VHDL codes were auto-
matically generated from the design using system generator.
The VHDL codes were then synthesized using Xilinx ISE 5.2i
and targeted for Virtex-E, 600 000 gates. The optimization
setting for the ISE is for maximum clock speed. Table 1 de-
tails the gate requirement of the FPGA design. The total gate
requirement reported by the ISE is approximately 100 kgates.
The price of the FPGA device in this range of gate size is very
low. Note that all of the buffers are implemented using exter-
nal memory.
Table 2 shows the reported maximum path delay and the
highest FPGA clock frequency.
4.4. Real-time testing of FPGAdesign
The real-time testing of the FPGA was done using a proto-
type board equipped with a 600 000-gate Virtex-E FPGA de-
vice. The systemsetup is shown in Figure 15. The wave files of
the convolutive mixtures used in Section 4.2.4 were encoded
into the left and right channels of a stereo MP3 file which is
then played back repeatedly using a portable MP3 player. The
prototype board is equipped with 20-bit A/D and D/A con-
verters and the sampling frequency was set to 8000 samples
per second. Only the highest 16 bits of the sampled signals
were used by the FPGA.
The FPGA streamed out the separated outputs which
were then converted into analog signals, amplified, and
played back on the speaker. By listening to the playback
sound, it was concluded that we had achieved the same level
of separation as found in earlier simulations.
5. SUMMARY
In this paper, the hardware implementation of the modi-
fied BSS algorithm was realized using FPGA. A set of com-
promised specification for the BSS algorithm was proposed
FPGA Hardware for Real-time ICA-Based BSS 3085
Figure 15: System setup for real-time testing of the blind source
separation in real time.
taking into consideration the separation performance and
hardware resource requirements. The design implements the
modified Torkkola’s BSS algorithm using noncausal unmix-
ing filters which reduce filter length and provides faster con-
vergence. There is no whitening process of the separated
sources involved except that there is a scaling applied in the
mixed inputs proportional to their variances.
The FPGA design was carried out using a system level
approach and the final hardware achieves the real-time oper-
ation using minimal FPGA resource. Many FPGA functional
simulations were carried out to verify and measure the sepa-
ration performance of the proposed simplified architecture.
The test input signals used include additive mixtures, convo-
lutive mixtures, and simulated room environment. The re-
sults show that the method is robust against noise; that is,
producing a small variation of the output SNR with respect
to a large variation in the input SNR. Note that here we have
considered the sensors to be almost perfect, or high quality
with negligible sensor error.
A relatively short filter length of 161 tap is first attempted
here due to the limitation of the maximum clock speed of
the FPGA. The FPGAcan performthe separation successfully
when the delay is small, that is, less than 161/8000 = 20 ms.
In the environment where the delay is longer, a much longer
filter tap is needed and this can be realized. In this case, we
propose that, in order to keep the FPGA clock frequency the
same, multiple MAC engines should be used together with
the implementation of polyphase decomposition. For exam-
ple, if the tap length of 161 ∗16 = 2576 is needed, 16 MACs
engines are to be implemented with the 16-band polyphase
decomposition. Since one MAC engine is made up of only
one multiplier and one accumulator, the additional MAC en-
gines will not lead to much additional gates.
The application of block mode separation leads to the
side effect of a long processing delay. It was shown in
Section 3.2 that our current design poses a long delay of
0.62 s. A practical solution to this long delay is to apply over-
lapped processing windows. For example, if the processing
delay is to be reduced to 0.62/32 = 20 ms, the 2500-sample
windows will have to be overlapped by 31/32 = 97%, that is,
the BSS has to be performed for every 78 input samples.
In this paper, we consider the case of 2 sources (or 2
voices) and 2 sensors (or 2 microphones). In the future,
we will carry out further improvements in our FPGA archi-
tecture to tackle the situation when the number of sources
is higher, or lower, than the number of sensors. Using our
existing design, we have done some FPGA simulation us-
ing 3 voices with 2 microphones. The separation results are
good (please visit the website http://www.ntu.edu.sg/home/
ecchara/ for listening test). In this situation, two of the three
voices are successfully separated (from each other) while the
third suppressed voice is still present at both of the outputs.
We will improve on our current FPGA design to handle this
situation. Considering the fact that redesigning the FPGA
takes much time, we will carry out the above improvements
in our future works.
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Charayaphan Charoensak received the
M.A.S. and Ph.D. degrees in electrical en-
gineering from the Technical University
of Nova Scotia, Halifax, NS, Canada, in
1989 and 1993, respectively. He is currently
an Assistant Professor with the School
of Electrical and Electronic Engineering,
Nanyang Technological University, Singa-
pore, in the Division of Information Engi-
neering. His research interests include ap-
plications of FPGAs in digital signal processing, sigma-delta signal
processing, pattern recognition, face recognition, adaptive signals,
speech/audio segmentation, watermarking, and image processing.
Farook Sattar is an Assistant Professor
at the Information Engineering Division,
Nanyang Technological University, Singa-
pore. He has received his Technical Licen-
tiate and Ph.D. degrees in signal and im-
age processing from Lund University, Swe-
den, and M.Eng. degree from Bangladesh
University of Technology, Bangladesh. His
current research interests include blind sig-
nal separation, watermarking, speech/audio
segmentation, speech enhancement, 3D audio, image feature ex-
traction, image enhancement, wavelets, filter banks, and adaptive
beamforming. He has training in both signal and image processing,
and has been involved in a number of signal and image processing-
related projects sponsored by the Swedish National Science and
Technology Board (NUTEK) and Singapore Academic Research
Funding (AcRF) Scheme. His research has been published in a
number of leading journals and conferences.
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Image Perception
Call for Papers
Perception is a complex process that involves brain activities
at different levels. The availability of models for the represen-
tation and interpretation of the sensory information opens
up new research avenues that cut across neuroscience, imag-
ing, information engineering, and modern robotics.
The goal of the multidisciplinary field of perceptual signal
processing is to identify the features of the stimuli that deter-
mine their “perception,” namely “a single unified awareness
derived from sensory processes while a stimulus is present,”
and to derive associated computational models that can be
generalized.
In the case of vision, the stimuli go through a complex
analysis chain along the so-called “visual pathway,” start-
ing with the encoding by the photoreceptors in the retina
(low-level processing) and ending with cognitive mecha-
nisms (high-level processes) that depend on the task being
performed.
Accordingly, low-level models are concerned with image
“representation” and aim at emulating the way the visual
stimulus is encoded by the early stages of the visual system as
well as capturing the varying sensitivity to the features of the
input stimuli; high-level models are related to image “inter-
pretation” and allow to predict the performance of a human
observer in a given predefined task.
A global model, accounting for both such bottom-up and
top-down approaches, would enable the automatic interpre-
tation of the visual stimuli based on both their low-level fea-
tures and their semantic content.
Among the main image processing fields that would take
advantage of such models are feature extraction, content-
based image description and retrieval, model-based coding,
and the emergent domain of medical image perception.
The goal of this special issue is to provide original contri-
butions in the field of image perception and modeling.
Topics of interest include (but are not limited to):
• Perceptually plausible mathematical bases for the
representation of visual information (static and dy-
namic)
• Modeling nonlinear processes (masking, facilitation)
and their exploitation in the imaging field (compres-
sion, enhancement, and restoration)
• Beyond early vision: investigating the pertinence and
potential of cognitive models (feature extraction, im-
age quality)
• Stochastic properties of complex natural scenes
(static, dynamic, colored) and their relationships with
perception
• Perception-based models for natural (static and dy-
namic) textures. Theoretical formulation and psy-
chophysical validation
• Applications in the field of biomedical imaging (med-
ical image perception)
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due December 1, 2005
Acceptance Notification April 1, 2006
Final Manuscript Due July 1, 2006
Publication Date 3rd Quarter, 2006
GUEST EDITORS:
Gloria Menegaz, Department of Information Engineering,
University of Siena, Siena, Italy; menegaz@dii.unisi.it
Guang-Zhong Yang, Department of Computing,
Engineering Imperial College London, London, UK;
gzy@doc.ic.ac.uk
Maria Concetta Morrone, Università Vita-Salute San
Raffaele, Milano, Italy; concetta@in.cnr.it
Stefan Winkler, Genista Corporation, Montreux,
Switzerland; stefan.winkler@genista.com
Javier Portilla, Department of Computer Science and
Artificial Intelligence (DECSAI), Universidad de Granada,
Granada, Spain; javier@decsai.ugr.es
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Music Information Retrieval Based on Signal Processing
Call for Papers
The main focus of this special issue is on the application of
digital signal processing techniques for music information
retrieval (MIR). MIR is an emerging and exciting area of re-
search that seeks to solve a wide variety of problems dealing
with preserving, analyzing, indexing, searching, and access-
ing large collections of digitized music. There are also strong
interests in this field of research from music libraries and the
recording industry as they move towards digital music distri-
bution. The demands from the general public for easy access
to these music libraries challenge researchers to create tools
and algorithms that are robust, small, and fast.
Music is represented in either encoded audio waveforms
(CD audio, MP3, etc.) or symbolic forms (musical score,
MIDI, etc.). Audio representations, in particular, require ro-
bust signal processing techniques for many applications of
MIR since meaningful descriptions need to be extracted
from audio signals in which sounds from multiple instru-
ments and vocals are often mixed together. Researchers in
MIR are therefore developing a wide range of new meth-
ods based on statistical pattern recognition, classification,
and machine learning techniques such as the Hidden Markov
Model (HMM), maximum likelihood estimation, and Bayes
estimation as well as digital signal processing techniques such
as Fourier and Wavelet transforms, adaptive filtering, and
source-filter models. New music interface and query systems
leveraging such methods are also important for end users to
benefit from MIR research.
Although research contributions on MIR have been pub-
lished at various conferences in 1990s, the members of the
MIR research community meet annually at the International
Conference on Music Information Retrieval (ISMIR) since
2000.
Topics of interest include (but are not limited to):
• Automatic summarization (succinct representation of
music)
• Automatic transcription (audio to symbolic format
conversion)
• Music annotation (semantic analysis)
• Music fingerprinting (unique identification of music)
• Music interface
• Music similarity metrics (comparison)
• Music understanding
• Musical feature extraction
• Musical styles and genres
• Optical music score recognition (image to symbolic
format conversion)
• Performer/artist identification
• Query systems
• Timbre/instrument recognition
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due December 1, 2005
Acceptance Notification April 1, 2006
Final Manuscript Due July 1, 2006
Publication Date 3rd Quarter, 2006
GUEST EDITORS:
Ichiro Fujinaga, McGill University, Montreal, QC, Canada,
H3A 2T5; ich@music.mcgill.ca
Masataka Goto, National Institute of Advanced Industrial
Science and Technology, Japan; m.goto@aist.go.jp
George Tzanetakis, University of Victoria, Victoria, BC,
Canada, V8P 5C2; gtzan@cs.uvic.ca
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Visual Sensor Networks
Call for Papers
Research into the design, development, and deployment
of networked sensing devices for high-level inference and
surveillance of the physical environment has grown tremen-
dously in the last few years.
This trend has been motivated, in part, by recent techno-
logical advances in electronics, communication networking,
and signal processing.
Sensor networks are commonly comprised of lightweight
distributed sensor nodes such as low-cost video cameras.
There is inherent redundancy in the number of nodes de-
ployed and corresponding networking topology. Operation
of the network requires autonomous peer-based collabora-
tion amongst the nodes and intermediate data-centric pro-
cessing amongst local sensors. The intermediate processing
known as in-network processing is application-specific. Of-
ten, the sensors are untethered so that they must commu-
nicate wirelessly and be battery-powered. Initial focus was
placed on the design of sensor networks in which scalar phe-
nomena such as temperature, pressure, or humidity were
measured.
It is envisioned that much societal use of sensor networks
will also be based on employing content-rich vision-based
sensors. The volume of data collected as well as the sophis-
tication of the necessary in-network stream content process-
ing provide a diverse set of challenges in comparison with
generic scalar sensor network research.
Applications that will be facilitated through the develop-
ment of visual sensor networking technology include auto-
matic tracking, monitoring and signaling of intruders within
a physical area, assisted living for the elderly or physically dis-
abled, environmental monitoring, and command and con-
trol of unmanned vehicles.
Many current video-based surveillance systems have cen-
tralized architectures that collect all visual data at a cen-
tral location for storage or real-time interpretation by a hu-
man operator. The use of distributed processing for auto-
mated event detection would significantly alleviate mundane
or time-critical activities performed by human operators,
and provide better network scalability. Thus, it is expected
that video surveillance solutions of the future will success-
fully utilize visual sensor networking technologies.
Given that the field of visual sensor networking is still in
its infancy, it is critical that researchers from the diverse dis-
ciplines including signal processing, communications, and
electronics address the many challenges of this emerging
field. This special issue aims to bring together a diverse set
of research results that are essential for the development of
robust and practical visual sensor networks.
Topics of interest include (but are not limited to):
• Sensor network architectures for high-bandwidth vi-
sion applications
• Communication networking protocols specific to vi-
sual sensor networks
• Scalability, reliability, and modeling issues of visual
sensor networks
• Distributed computer vision and aggregation algo-
rithms for low-power surveillance applications
• Fusion of information from visual and other modali-
ties of sensors
• Storage and retrieval of sensor information
• Security issues for visual sensor networks
• Visual sensor network testbed research
• Novel applications of visual sensor networks
• Design of visual sensors
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due December 1, 2005
Acceptance Notification April 1, 2006
Final Manuscript Due July 1, 2006
Publication Date 3rd Quarter, 2006
GUEST EDITORS:
Deepa Kundur, Department of Electrical Engineering,
Texas A&M University, College Station, Texas, USA;
deepa@ee.tamu.edu
Ching-Yung Lin, Distributed Computing Department,
IBM TJ Watson Research Center, New York, USA;
chingyung@us.ibm.com
Chun Shien Lu, Institute of Information Science, Academia
Sinica, Taipei, Taiwan; lcs@iis.sinica.edu.tw
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Multirate Systems and Applications
Call for Papers
Filter banks for the application of subband coding of speech
were introduced in the 1970s. Since then, filter banks and
multirate systems have been studied extensively. There has
been great success in applying multirate systems to many ap-
plications. The most notable of these applications include
subband coding for audio, image, and video, signal anal-
ysis and representation using wavelets, subband denoising,
and so forth. Different applications also call for different fil-
ter bank designs and the topic of designing one-dimensional
and multidimentional filter banks for specific applications
has been of great interest.
Recently there has been growing interest in applying mul-
tirate theories to the area of communication systems such as,
transmultiplexers, filter bank transceivers, blind deconvolu-
tion, and precoded systems. There are strikingly many duali-
ties and similarities between multirate systems and multicar-
rier communication systems. Many problems in multicarrier
transmission can be solved by extending results from mul-
tirate systems and filter banks. This exciting research area is
one that is of increasing importance.
The aim of this special issue is to bring forward recent de-
velopments on filter banks and the ever-expanding area of
applications of multirate systems.
Topics of interest include (but are not limited to):
• Multirate signal processing for communications
• Filter bank transceivers
• One-dimensional and multidimensional filter bank
designs for specific applications
• Denoising
• Adaptive filtering
• Subband coding
• Audio, image, and video compression
• Signal analysis and representation
• Feature extraction and classification
• Other applications
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due January 1, 2006
Acceptance Notification May 1, 2006
Final Manuscript Due August 1, 2006
Publication Date 4th Quarter, 2006
GUEST EDITORS:
Yuan-Pei Lin, Department of Electrical and Control
Engineering, National Chiao Tung University, Hsinchu,
Taiwan; ypl@mail.nctu.edu.tw
See-May Phoong, Department of Electrical Engineering
and Graduate Institute of Communication Engineering,
National Taiwan University, Taipei, Taiwan;
smp@cc.ee.ntu.edu.tw
Ivan Selesnick, Department of Electrical and Computer
Engineering, Polytechnic University, Brooklyn, NY 11201,
USA; selesi@poly.edu
Soontorn Oraintara, Department of Electrical
Engineering, The University of Texas at Arlington,
Arlington, TX 76010, USA; oraintar@uta.edu
Gerald Schuller, Fraunhofer Institute for Digital Media
Technology (IDMT), Langewiesener Strasse 22, 98693
Ilmenau, Germany; shl@idmt.fraunhofer.de
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Multisensor Processing for Signal Extraction
and Applications
Call for Papers
Source signal extraction from heterogeneous measurements
has a wide range of applications in many scientific and tech-
nological fields, for example, telecommunications, speech
and acoustic signal processing, and biomedical pattern anal-
ysis. Multiple signal reception through multisensor systems
has become an effective means for signal extraction due to its
superior performance over the monosensor mode. Despite
the rapid progress made in multisensor-based techniques in
the past few decades, they continue to evolve as key tech-
nologies in modern wireless communications and biomedi-
cal signal processing. This has led to an increased focus by the
signal processing community on the advanced multisensor-
based techniques which can offer robust high-quality sig-
nal extraction under realistic assumptions and with minimal
computational complexity. However, many challenging tasks
remain unresolved and merit further rigorous studies. Major
efforts in developing advanced multisensor-based techniques
may include high-quality signal extraction, realistic theoret-
ical modeling of real-world problems, algorithm complexity
reduction, and efficient real-time implementation.
The purpose of this special issue aims to present state-of-
the-art multisensor signal extraction techniques and applica-
tions. Contributions in theoretical study, performance analy-
sis, complexity reduction, computational advances, and real-
world applications are strongly encouraged.
Topics of interest include (but are not limited to):
• Multiantenna processing for radio signal extraction
• Multimicrophone speech recognition and enhance-
ment
• Multisensor radar, sonar, navigation, and biomedical
signal processing
• Blind techniques for multisensor signal extraction
• Computational advances in multisensor processing
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due January 1, 2006
Acceptance Notification May 1, 2006
Final Manuscript Due August 1, 2006
Publication Date 4th Quarter, 2006
GUEST EDITORS:
Chong-Yung Chi, National Tsing Hua University, Taiwan;
cychi@ee.nthu.edu.tw
Ta-Sung Lee, National Chiao Tung University, Taiwan;
tslee@cc.nctu.edu.tw
Zhi-Quan Luo, University of Minnesota, USA;
luozq@ece.umn.edu
Kung Yao, University of California, Los Angeles, USA;
yao@ee.ucla.edu
Yue Wang, Virginia Polytechnic Institute and State
University, USA; yuewang@vt.edu
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Search and Retrieval of 3DContent and Associated
Knowledge Extraction and Propagation
Call for Papers
With the general availability of 3D digitizers, scanners, and
the technology innovation in 3D graphics and computa-
tional equipment, large collections of 3D graphical mod-
els can be readily built up for different applications (e.g.,
in CAD/CAM, games design, computer animations, manu-
facturing and molecular biology). For such large databases,
the method whereby 3D models are sought merits careful
consideration. The simple and efficient query-by-content ap-
proach has, up to now, been almost universally adopted in
the literature. Any such method, however, must first deal
with the proper positioning of the 3D models. The two
prevalent-in-the-literature methods for the solution to this
problem seek either
• Pose Normalization: Models are first placed into a
canonical coordinate frame (normalizing for transla-
tion, scaling, and rotation). Then, the best measure of
similarity is found by comparing the extracted feature
vectors, or
• Descriptor Invariance: Models are described in a
transformation invariant manner, so that any trans-
formation of a model will be described in the same
way, and the best measure of similarity is obtained at
any transformation.
The existing 3D retrieval systems allow the user to perform
queries by example. The queried 3D model is then processed,
low-level geometrical features are extracted, and similar ob-
jects are retrieved from a local database. A shortcoming of
the methods that have been proposed so far regarding the
3D object retrieval, is that neither is the semantic informa-
tion (high-level features) attached to the (low-level) geomet-
ric features of the 3D content, nor are the personalization
options taken into account, which would significantly im-
prove the retrieved results. Moreover, few systems exist so
far to take into account annotation and relevance feedback
techniques, which are very popular among the correspond-
ing content-based image retrieval systems (CBIR).
Most existing CBIR systems using knowledge either an-
notate all the objects in the database (full annotation) or
annotate a subset of the database manually selected (par-
tial annotation). As the database becomes larger, full anno-
tation is increasingly difficult because of the manual effort
needed. Partial annotation is relatively affordable and trims
down the heavy manual labor. Once the database is partially
annotated, traditional image analysis methods are used to de-
rive semantics of the objects not yet annotated. However, it
is not clear “how much” annotation is sufficient for a specific
database and what the best subset of objects to annotate is.
In other words how the knowledge will be propagated. Such
techniques have not been presented so far regarding the 3D
case.
Relevance feedback was first proposed as an interactive
tool in text-based retrieval. Since then it has been proven to
be a powerful tool and has become a major focus of research
in the area of content-based search and retrieval. In the tra-
ditional computer centric approaches, which have been pro-
posed so far, the “best” representations and weights are fixed
and they cannot effectively model high-level concepts and
user’s perception subjectivity. In order to overcome these
limitations of the computer centric approach, techniques
based on relevant feedback, in which the human and com-
puter interact to refine high-level queries to representations
based on low-level features, should be developed.
The aim of this special issue is to focus on recent devel-
opments in this expanding research area. The special issue
will focus on novel approaches in 3D object retrieval, trans-
forms and methods for efficient geometric feature extrac-
tion, annotation and relevance feedback techniques, knowl-
edge propagation (e.g., using Bayesian networks), and their
combinations so as to produce a single, powerful, and domi-
nant solution.
Topics of interest include (but are not limited to):
• 3D content-based search and retrieval methods
(volume/surface-based)
• Partial matching of 3D objects
• Rotation invariant feature extraction methods for 3D
objects
• Graph-based and topology-based methods
• 3D data and knowledge representation
• Semantic and knowledge propagation over heteroge-
neous metadata types
• Annotation and relevance feedback techniques for 3D
objects
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of
their complete manuscript through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due February 1, 2006
Acceptance Notification June 1, 2006
Final Manuscript Due September 1, 2006
Publication Date 4th Quarter, 2006
GUEST EDITORS:
Tsuhan Chen, Carnegie Mellon University, Pittsburgh, PA
15213, USA; tsuhan@cmu.edu
Ming Ouhyoung, National Taiwan University, Taipei 106,
Taiwan; ming@csie.ntu.edu.tw
Petros Daras, Informatics and Telematics Institute, Centre
for Research and Technology Hellas, 57001 Thermi, Thessa-
loniki, Greece; daras@iti.gr
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Robust Speech Recognition
Call for Papers
Robustness can be defined as the ability of a system to main-
tain performance or degrade gracefully when exposed to
conditions not well represented in the data used to develop
the system. In automatic speech recognition (ASR), systems
must be robust to many forms of signal degradation, includ-
ing speaker characteristics (e.g., dialect and accent), ambient
environment (e.g., cellular telephony), transmission channel
(e.g., voice over IP), and language (e.g., new words, dialect
switching). Robust ASR systems, which have been under de-
velopment for the past 35 years, have made great progress
over the years closing the gap between performance on pris-
tine research tasks and noisy operational data.
However, in recent years, demand is emerging for a new
class of systems that tolerate extreme and unpredictable vari-
ations in operating conditions. For example, in a cellular
telephony environment, there are many nonstationary forms
of noise (e.g., multiple speakers) and significant variations
in microphone type, position, and placement. Harsh ambi-
ent conditions typical in automotive and mobile applications
pose similar challenges. Development of systems in a lan-
guage or dialect for which there is limited or no training data
in a target language has become a critical issue for a new gen-
eration of voice mining applications. The existence of mul-
tiple conditions in a single stream, a situation common to
broadcast news applications, and that often involves unpre-
dictable changes in speaker, topic, dialect, or language, is an-
other form of robustness that has gained attention in recent
years.
Statistical methods have dominated the field since the early
1980s. Such systems tend to excel at learning the characteris-
tics of large databases that represent good models of the op-
erational conditions and do not generalize well to new envi-
ronments.
This special issue will focus on recent developments in this
key research area. Topics of interest include (but are not lim-
ited to):
• Channel and microphone normalization
• Stationary and nonstationary noise modeling, com-
pensation, and/or rejection
• Localization and separation of sound sources (includ-
ing speaker segregation)
• Signal processing and feature extraction for applica-
tions involving hands-free microphones
• Noise robust speech modeling
• Adaptive training techniques
• Rapid adaptation and learning
• Integration of confidence scoring, metadata, and
other alternative information sources
• Audio-visual fusion
• Assessment relative to human performance
• Machine learning algorithms for robustness
• Transmission robustness
• Pronunciation modeling
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of
their complete manuscript through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due February 1, 2006
Acceptance Notification June 1, 2006
Final Manuscript Due September 1, 2006
Publication Date 4th Quarter, 2006
GUEST EDITORS:
Herve Bourlard, IDIAP Research Institute, Swiss Federal In-
stitute of Technology at Lausanne (EPFL), 1920 Martigny,
Switzerland; herve.bourlard@idiap.ch
Mark Gales, Department of Engineering, University of
Cambridge, Cambridge CB2 1PZ, UK; mjfg@eng.cam.ac.uk
Maurizio Omologo, ITC-IRST, 38050 Trento, Italy; omol-
ogo@itc.it
S. Parthasarathy, AT&T Labs - Research, NJ 07748, USA;
sps@research.att.com
Joe Picone, Department of Electrical and Computer Engi-
neering, Mississippi State University, MS 39762-9571, USA;
picone@cavs.msstate.edu
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Signal Processing Technologies for Ambient
Intelligence in Home-Care Applications
Call for Papers
The possibility of allowing elderly people with different kinds
of disabilities to conduct a normal life at home and achieve
a more effective inclusion in the society is attracting more
and more interest from both industrial and governmental
bodies (hospitals, healthcare institutions, and social institu-
tions). Ambient intelligence technologies, supported by ad-
equate networks of sensors and actuators, as well as by suit-
able processing and communication technologies, could en-
able such an ambitious objective.
Recent researches demonstrated the possibility of provid-
ing constant monitoring of environmental and biomedical
parameters, and the possibility to autonomously originate
alarms, provide primary healthcare services, activate emer-
gency calls, and rescue operations through distributed as-
sistance infrastructures. Nevertheless, several technological
challenges are still connected with these applications, rang-
ing from the development of enabling technologies (hard-
ware and software), to the standardization of interfaces, the
development of intuitive and ergonomic human-machine in-
terfaces, and the integration of complex systems in a highly
multidisciplinary environment.
The objective of this special issue is to collect the most
significant contributions and visions coming from both aca-
demic and applied research bodies working in this stimulat-
ing research field. This is a highly interdisciplinary field com-
prising many areas, such as signal processing, image process-
ing, computer vision, sensor fusion, machine learning, pat-
tern recognition, biomedical signal processing, multimedia,
human-computer interfaces, and networking.
The focus will be primarily on the presentation of origi-
nal and unpublished works dealing with ambient intelligence
and domotic technologies that can enable the provision of
advanced homecare services.
This special issue will focus on recent developments in this
key research area. Topics of interest include (but are not lim-
ited to):
• Video-based monitoring of domestic environments
and users
• Continuous versus event-driven monitoring
• Distributed information processing
• Data fusion techniques for event association and au-
tomatic alarm generation
• Modeling, detection, and learning of user habits for
automatic detection of anomalous behaviors
• Integration of biomedical and behavioral data
• Posture and gait recognition and classification
• Interactive multimedia communications for remote
assistance
• Content-based encoding of medical and behavioral
data
• Networking support for remote healthcare
• Intelligent/natural man-machine interaction, person-
alization, and user acceptance
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of their
complete manuscripts through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due March 1, 2006
Acceptance Notification July 1, 2006
Final Manuscript Due October 1, 2006
Publication Date 1st Quarter, 2007
GUEST EDITORS:
Francesco G. B. De Natale, Department of Information
and Communication Technology, University of Trento, Via
Sommarive 14, 38050 Trento, Italy; denatale@ing.unitn.it
Aggelos K. Katsaggelos, Department of Electrical and
Computer Engineering, Northwestern University, 2145
Sheridan Road, Evanston, IL 60208-3118, USA;
aggk@ece.northwestern.edu
Oscar Mayora, Create-Net Association, Via Solteri 38,
38100 Trento, Italy; oscar.mayora@create-net.it
Ying Wu, Department of Electrical and Computer Eng-
ineering, Northwestern University, 2145 Sheridan Road,
Evanston, IL 60208-3118, USA;
yingwu@ece.northwestern.edu
Hindawi Publishing Corporation
http://www.hindawi.com
EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING
Special Issue on
Spatial Sound and Virtual Acoustics
Call for Papers
Spatial sound reproduction has become widespread in the
form of multichannel audio, particularly through home the-
ater systems. Reproduction systems from binaural (by head-
phones) to hundreds of loudspeaker channels (such as wave
field synthesis) are entering practical use. The application
potential of spatial sound is much wider than multichan-
nel sound, however, and research in the field is active. Spa-
tial sound covers for example the capturing, analysis, coding,
synthesis, reproduction, and perception of spatial aspects in
audio and acoustics.
In addition to the topics mentioned above, research in vir-
tual acoustics broadens the field. Virtual acoustics includes
techniques and methods to create realistic percepts of sound
sources and acoustic environments that do not exist natu-
rally but are rendered by advanced reproduction systems us-
ing loudspeakers or headphones. Augmented acoustic and
audio environments contain both real and virtual acoustic
components.
Spatial sound and virtual acoustics are among the ma-
jor research and application areas in audio signal processing.
Topics of active study range from new basic research ideas to
improvement of existing applications. Understanding of spa-
tial sound perception by humans is also an important area,
in fact a prerequisite to advanced forms of spatial sound and
virtual acoustics technology.
This special issue will focus on recent developments in this
key research area. Topics of interest include (but are not lim-
ited to):
• Multichannel reproduction
• Wave field synthesis
• Binaural reproduction
• Format conversion and enhancement of spatial
sound
• Spatial sound recording
• Analysis, synthesis, and coding of spatial sound
• Spatial sound perception and auditory modeling
• Simulation and modeling of room acoustics
• Auralization techniques
• Beamforming and sound source localization
• Acoustic and auditory scene analysis
• Augmented reality audio
• Virtual acoustics (sound environments and sources)
• Intelligent audio environments
• Loudspeaker-room interaction and equalization
• Applications
Authors should follow the EURASIP JASP manuscript
format described at http://www.hindawi.com/journals/asp/.
Prospective authors should submit an electronic copy of
their complete manuscript through the EURASIP JASP man-
uscript tracking system at http://www.mstracking.com/asp/,
according to the following timetable:
Manuscript Due May 1, 2006
Acceptance Notification September 1, 2006
Final Manuscript Due December 1, 2006
Publication Date 1st Quarter, 2007
GUEST EDITORS:
Ville Pulkki, Helsinki University of Technology, Espoo,
Finland; ville@acoustics.hut.fi
Christof Faller, EPFL, Lausanne, Switzerland;
christof.faller@epfl.ch
Aki Harma, Philips Research Labs, Eindhoven, The
Netherlands; aki.harma@philips.com
Tapio Lokki, Helsinki University of Technology, Espoo,
Finland; ktlokki@cc.hut.fi
Werner de Bruijn, Philips Research Labs, Eindhoven, The
Netherlands; werner.de.bruijn@philips.com
Hindawi Publishing Corporation
http://www.hindawi.com
NEWS RELEASE
Nominations Invited for the Institute of Acoustics
2006 A B Wood Medal
The Institute of Acoustics, the UK’s leading professional
body for those working in acoustics, noise and vibration, is
inviting nominations for its prestigious A B Wood Medal for
the year 2006.
The A B Wood Medal and prize is presented to an individ-
ual, usually under the age of 35, for distinguished contribu-
tions to the application of underwater acoustics. The award
is made annually, in even numbered years to a person from
Europe and in odd numbered years to someone from the
USA/Canada. The 2005 Medal was awarded to Dr A Thode
from the USA for his innovative, interdisciplinary research in
ocean and marine mammal acoustics.
Nominations should consist of the candidate’s CV, clearly
identifying peer reviewed publications, and a letter of en-
dorsement from the nominator identifying the contribution
the candidate has made to underwater acoustics. In addition,
there should be a further reference from a person involved
in underwater acoustics and not closely associated with the
candidate. Nominees should be citizens of a European Union
country for the 2006 Medal. Nominations should be marked
confidential and addressed to the President of the Institute of
Acoustics at 77ASt Peter’s Street, St. Albans, Herts, AL1 3BN.
The deadline for receipt of nominations is 15 October 2005.
Dr Tony Jones, President of the Institute of Acoustics,
comments, “A B Wood was a modest man who took delight
in helping his younger colleagues. It is therefore appropriate
that this prestigious award should be designed to recognise
the contributions of young acousticians.”
Further information and an nomination form
can be found on the Institute’s website at
www.ioa.org.uk.
A B Wood
Albert Beaumont Wood was born in Yorkshire in 1890 and
graduated from Manchester University in 1912. He became
one of the first two research scientists at the Admiralty to
work on antisubmarine defence. He designed the first direc-
tional hydrophone and was well known for the many contri-
butions he made to the science of underwater acoustics and
for the help he gave to younger colleagues. The medal was
instituted after his death by his many friends on both sides of
the Atlantic and was administered by the Institute of Physics
until the formation of the Institute of Acoustics in 1974.
PRESS CONTACT
Judy Edrich
Publicity & Information Manager, Institute of Acoustics
Tel: 01727 848195; E-mail: judy.edrich@ioa.org.uk
EDITORS NOTES
The Institute of Acoustics is the UK’s professional body
for those working in acoustics, noise and vibration. It was
formed in 1974 from the amalgamation of the Acoustics
Group of the Institute of Physics and the British Acoustical
Society (a daughter society of the Institution of Mechanical
Engineers). The Institute of Acoustics is a nominated body of
the Engineering Council, offering registration at Chartered
and Incorporated Engineer levels.
The Institute has some 2500 members from a rich di-
versity of backgrounds, with engineers, scientists, educa-
tors, lawyers, occupational hygienists, architects and envi-
ronmental health officers among their number. This multi-
disciplinary culture provides a productive environment for
cross-fertilisation of ideas and initiatives. The range of in-
terests of members within the world of acoustics is equally
wide, embracing such aspects as aerodynamics, architectural
acoustics, building acoustics, electroacoustics, engineering
dynamics, noise and vibration, hearing, speech, underwa-
ter acoustics, together with a variety of environmental as-
pects. The lively nature of the Institute is demonstrated by
the breadth of its learned society programmes.
For more information please visit our site at
www.ioa.org.uk.
HIGH-FIDELITY MULTICHANNEL
AUDIO CODING
Dai Tracy Yang, Chris Kyriakakis, and C.-C. Jay Kuo
T
his invaluable monograph addresses the specific needs of
audio-engineering students and researchers who are either
learning about the topic or using it as a reference book on
multichannel audio compression. This book covers a wide range
of knowledge on perceptual audio coding, from basic digital signal
processing and data compression techniques to advanced audio
coding standards and innovative coding tools. It is the only book
available on the market that solely focuses on the principles of high-
quality audio codec design for multichannel sound sources.
This book includes three parts. The first part covers the basic topics
on audio compression, such as quantization, entropy coding,
psychoacoustic model, and sound quality assessment. The second
part of the book highlights the current most prevalent low-bit-rate
high-performance audio coding standards—MPEG-4 audio. More
space is given to the audio standards that are capable of supporting
multichannel signals, that is, MPEG advanced audio coding (AAC),
including the original MPEG-2 AAC technology, additional MPEG-
4 toolsets, and the most recent aacPlus standard. The third part of
this book introduces several innovative multichannel audio coding
tools, which have been demonstrated to further improve the coding performance and expand the available
functionalities of MPEG AAC, and is more suitable for graduate students and researchers in the advanced
level.
Dai Tracy Yang is currently Postdoctoral Research Fellow, Chris Kyriakakis is Associated Professor, and C.-C. Jay
Kuo is Professor, all affiliated with the Integrated Media Systems Center (IMSC) at the University of Southern
California.



























































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EURASIP Book Series on Signal Processing and Communications
The EURASIP Book Series on Signal Processing and Communications publishes monographs,
edited volumes, and textbooks on Signal Processing and Communications. For more information
about the series please visit: http://hindawi.com/books/spc/about.html
For more information and online orders please visit: http://www.hindawi.com/books/spc/volume-1/
For any inquiries on how to order this title please contact books.orders@hindawi.com
EURASIP Book Series on SP&C, Volume 1, ISBN 977-5945-08-9
The EURASIP Book Series on Signal Processing and Communications publishes monographs,
edited volumes, and textbooks on Signal Processing and Communications. For more information
about the series please visit: http://hindawi.com/books/spc/about.html
For more information and online orders please visit: http://www.hindawi.com/books/spc/volume-2/
For any inquiries on how to order this title please contact books.orders@hindawi.com
EURASIP Book Series on SP&C, Volume 2, ISBN 977-5945-07-0
R
ecent advances in genomic studies have stimulated synergetic
research and development in many cross-disciplinary areas.
Genomic data, especially the recent large-scale microarray gene
expression data, represents enormous challenges for signal processing
and statistics in processing these vast data to reveal the complex biological
functionality. This perspective naturally leads to a new field, genomic
signal processing (GSP), which studies the processing of genomic signals
by integrating the theory of signal processing and statistics. Written by
an international, interdisciplinary team of authors, this invaluable edited
volume is accessible to students just entering this emergent field, and to
researchers, both in academia and industry, in the fields of molecular
biology, engineering, statistics, and signal processing. The book provides
tutorial-level overviews and addresses the specific needs of genomic
signal processing students and researchers as a reference book.
The book aims to address current genomic challenges by exploiting
potential synergies between genomics, signal processing, and statistics,
with special emphasis on signal processing and statistical tools for
structural and functional understanding of genomic data. The book is partitioned into three parts. In part I, a
brief history of genomic research and a background introduction from both biological and signal-processing/
statistical perspectives are provided so that readers can easily follow the material presented in the rest of the
book. In part II, overviews of state-of-the-art techniques are provided. We start with a chapter on sequence
analysis, and follow with chapters on feature selection, clustering, and classification of microarray data. The
next three chapters discuss the modeling, analysis, and simulation of biological regulatory networks, especially
gene regulatory networks based on Boolean and Bayesian approaches. The next two chapters treat visualization
and compression of gene data, and supercomputer implementation of genomic signal processing systems. Part
II concludes with two chapters on systems biology and medical implications of genomic research. Finally, part
III discusses the future trends in genomic signal processing and statistics research.



























































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GENOMIC SIGNAL PROCESSING
AND STATISTICS
Edited by: Edward R. Dougherty, Ilya Shmulevich, Jie Chen, and Z. Jane Wang
EURASIP Book Series on Signal Processing and Communications

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