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# Explanation of LOP logic in SEL-751A

The LOP logic in the instruction manual data code 20111028 & data code 20090501 are working on
the same principle.
The LOP logic in the instruction manual data code 20111028 & data code 20090501 is the
simplified snapshot of attached master diagram (Refer Figure 1), to make it simple to
understand.

Figure 1 Master diagram

The instruction manual data code 20111028 is taken from master diagram in Fig1.1.

Figure 1.1
The Red colour marked Block 1, Block 2 and Block 3 output is Delta angle I1> 10 degree, Delta
angle I2> 10 degree and delta angle Io> 10 degree, respectively.

The simplified representation in Manual data code 20111028, as shown in Figure 2 below

Figure 2 LOP logic in IM data code 20111028

The instruction manual data code 20090501 was taken from master diagram in Fig.1.2,

Figure 1.2
The red colour marked OR gates were not highlighted in instruction manual data code 20090501,
but it is assured that the LOP logic will operate in less than 10 % of I
nom
also. (Working remains
same as logic in 20111028 manual)
Since, the LOP logic in the manuals have been updated, we recommend use of manual data code
20111028.

LOP logic:
Considering a real-time condition as following[Refer Figure 1.3]
1) Three phase MCB on PT secondary/ 3Ph fuse fail
2) Load is less than 10% of I nominal
When the above condition occurs,
a) The delta V1 is more than 25% [Difference between present sample(|V1
k
|) and the sample
of one cycle before(|V1
k-4
)] and at the same time the condition |V1
k-4
| > 5V is also
satisfied

b) The difference between the current sample of one cycle before (
Ik-4
) and the current
sample of present cycle (I
k
) is less than 0.1* I
nominal
. The angle of change of I1 is ANDed
with [comparison between 0.1* I
nominal
value and sample(I
k
), as well as, sample (
Ik-4
)]
Please note that both current values, (I
k
) and (
Ik-4
), are less than 0.1* I
nominal
(As per the
condition)

c) Change in corresponding Negative sequence current (I2) and zero sequence current(I0),
should not be present.

d) So the relay declares LOP, because the voltage change is satisfying and current changes
are less 0.1 * I nominal also LOP reset condition is not high. (3Inputs to the AND Gate)

Taking all the above conditions into account, the logical values of each signal can be
represented as in Figure 1.3-

Figure 1.3
The above result is same for upstream breaker trips (Similar to tripping of MCB on PT
secondary/3Ph fuse fail), when the load is less than 10% of I
nom.
The relay will assert LOP logic in no load condition also. Because the rate of change of
sequence current (I1, I2, I0) values and present cycle values are less than 0.1*I
nom
The rate of change of sequence components of current values (I1, I2, I0) are used to
prevent LOP to assert, when the change is more than 0.1 * I
nom
.
This is the same happening in Reliance Samalkot.
Let us assume the next condition
A) The load is more than 0.1 *I
nom
, then up stream breaker trips due to an actual system
fault/manual tripping.
In this condition the rate of change of current delta I1 will be more than 0.1* I
nom,
which will
prevent LOP logic to latch. It will allow to trip breaker on under voltage. The second input of AND
gate is 1. So the LOP will not assert. Please refer Fig.1.4 -

Figure 1.4
In above case, change in sequence components I2 and/or I0 may also be present, to
give similar result and prevent LOP from asserting.

Possible solution to trip down stream breaker (When the Load is less than 0.1* I
nom
)
1) Allow under voltage tripping if the downstream breaker side PT MCB is healthy. (By
sensing MCB auxiliary contact status)
2) Trip down stream breaker by sensing the status of upstream breaker status, downstream
intertripping.
3) Allow trip when both BUS PT voltage and line PT voltage are less than set value
(But when the both Line and BUS PT MCB fails, which is an extreme case, this may not be
useful)