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DESIGN OF ARITHMETIC AND LOGICAL UNIT

The ALU is the part of the microprocessor that handles all Boolean and mathematical
operations. However, exploring an actual ALU from one of the current microprocessors is too
complex. Thus, I have taken a more simplified design that, although limited in functionality, will
show you the general picture. I have divided the diagram into three sections: Logical Unit,
Decoder, and Full Adder. The inputs are A, B, F0, F1, and Carry In. There are also 3-input AND
gates and a 4-input OR gate. They are basically the same as the 2-input gates, except that the 3-
input AND gate only outputs a 1 if all 3 inputs are 1s, and the 4-input OR gate always outputs a
1, except when all inputs are 0s.

1 bit Arithmetic and logical unit

The F inputs control the enable lines. As you can see, no matter which of the four
possible combinations of F inputs is put in, only one (and each time different) enable line will be
"turned on." Thus, the function of the decoder subpart is to figure out which of the 4 operations
will be done. The A and B are used as the regular inputs for all operations.

A full adder is a logical circuit that performs an addition operation on three binary digits. The
full adder produces a sum and carries value, which are both binary digits.

Full adder circuit diagram


Inputs: {A, B, CarryIn} → Outputs: {Sum, CarryOut}

Input Output
A B Ci Co S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Note that in the above diagram the final OR gate before the carry-out output may be replaced by
an XOR gate without altering the resulting logic.

Now referring to the I bit ALU diagram, all output is ANDed with the corresponding
enable line. The logical unit is simply a collection of three Boolean operations, AB, A+B, NOT
B. As with the full adder, each of their outputs is ANDed with the corresponding enable line. On
the very right, all of the outputs are ORed together. However, only one of the four inputs could
potentially be a 1 because of the enable lines.
Most likely, an 8-bit ALU is more convenient for useful operations. To create an 8-bit
ALU, this diagram needs to be repeated 8 times, linking the Carry-Out to the Carry-In of the next
one each time. For e.g. the inputs are A=1, B=0, F0=1, F1=0, and we will not worry about the
Carry In. Going to the decoder. We can see that this will enable the third enable line. By
following this enable line, we find out that it is going to be ANDed with the NOT, thus we will
only explore the NOT (since all the other outputs will be ANDed with 0, automatically
producing a 0 output). The NOT takes in only B. Since B is 0, NOT B is 1. When that 1 is
ANDed with the enable line, it produces a 1, since both are 1. This then goes to the output, where
the 1 is ORed with 3 other 0s. Thus the output will be 1, and the carry out will be 0.