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1
ECE-GATE 2014 Topic Test-Digital

Duration: 90 Minutes Maximum Marks: 50

Read the following papers instructions carefully:

1. There are a total of 33 questions carrying 50 marks. Questions are of multiple choice type or numerical
answer type. A multiple choice type question will have four choices for the answer with only one correct
choice. For numerical answer type questions, the answer is a number and no choices will be given. A
number as the answer should be entered by writing approximate value.

2. Q.1- Q.13 are of multiple choice type and carries 1 mark each. Q.14- Q.16 are of numerical answer type
and carries 1 mark each. Q.17- Q.24 are of multiple choice type and carries 2 marks each. Q.25- Q.29
are of numerical answer type and carries 2 marks each.Q.30-Q.31 include one pair of common data
questions which are of numerical answer type and carries 2 marks each and Q.32-Q.33 include one pair
of linked answer questions which are multiple choice type and carries 2 marks each. The answer to the
second question of the linked answer questions depends on the answer to the first question of the pair. If
the first question in the linked pair is wrongly answered or is not attempted then the answer to the second
question in the pair will not be evaluated.

3. Questions not attempted will result in zero mark. Wrong answers for multiple choice type questions will
result in NEGATIVE marks. For all 1 mark questions, 1/3 mark will be deducted for each wrong
answer. For all 2 marks questions, 2/3 mark will be deducted for each wrong answer. However, in the
case of the linked answer question pair, there will be negative marks only for wrong answer to the first
question and no negative marks for wrong answer to the second question. There is no negative
marking for questions of numerical answer type.

4. Objective questions must be answered on Objective Response Sheet (ORS) by marking (A, B, C, D)
using HB pencil against the question number on the left hand side of the ORS. For Numeric data
questions answer must be marked in form of numerical value only. Each question has only one correct
answer. In case you wish to change an answer, erase the old answer completely. More than one answer
marked against a question will be treated as a wrong answer.


5. Calculator is allowed. Charts, graph sheets or tables are NOT allowed in examination hall

6. Do the rough works in scribble pad provided/ In case of offline it can be done on paper itself?









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Q.1. Consider the logic function in Min terms form as f (A, B, C, D) (1, 3, 5,8, 9,11,15) d(2,13) = +

what
are the numbers of complemented literals in the expression of SOP form for f (A, B,C,D)?
(A) 3 (B) 4 (C) 5 (D) 6
Q.2. For a Boolean function Y AB AC = + the POS form will be:
(A) (0, 2, 4) H (B) (1, 2, 5, 7) H (C) (2, 3, 5, 7) H (D) (0, 2, 4, 5) H
Q.3. What is the value of
1 2 3
f (A, B, C) (f .f ) f = + if Min-terms of expressions are given as follows?

1
2
3
f (A, B, C) (0, 2, 3, 4)
f (A, B, C) (1, 2, 3)
f (A, B, C) (4, 5, 6)
= E
= E
= E

(A) (0, 2, 3, 4) E (B) (2, 3, 4, 5, 6) E (C) (0,1, 2, 3, 4, 5, 6) E (D) (2, 3) E
Q.4. Which of the following identity is not correct?
(A) A B C A (B C) (A B) C = = (B) A B C A (B C) (A B) C = =
(C) A B AB A B AB A B = = + (D) A B C A (B C) (A B) C = =
Q.5. A 1 bit full adder takes 5 ns to generate carry out bit and 10 ns for the sum bit. What is the maximum
rate of addition per second when four 1-bit full adders are cascaded?
(A)
7
10 (B)
6
6.25 10 (C)
7
4 10 (D)
7
6.25 10
Q.6. Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean
function of n-variables. What is the Minimum size of Multiplexer needed??
(A) 2
n-2
line to 1 line (B) 2
n
line to 1 line (C) 2
n+1
line to 1 line (D) 2
n-1
line to 1 line
Q.7. Which of the following statement is not correct?
(A) Half adder can be implemented by use of five two input NAND gate & five two input NOR gate
(B) Full adder can be implemented by use of nine two input NAND gate & nine two input NOR gate
(C) Half subtractor can be implemented by use of five two input NAND gate & five two input NOR
gate
(D) Half adder can be implemented by use of two 2:1 MUX (inverter is not available)
Q.8. Consider the following statements. A 4 16 decoder can be constructed with enable inputs by
1. Using 4, 2 4 decoders (each with enable input)
2. Using 5, 2 4 decoders (each with enable input)
3. Using 2, 3 8 decoders (each with enable input)
4. Using 2, 3 8 decoders (each with enable i/p & inverter)
Which statements are correct?
(A) Only 1 & 4 (B) Only 2 & 4 (C) Only 1 & 3 (D) Only 2 & 3
Q.9. A 5 bit serial adder is implemented using two 5 bit shift registers, a full adder and a D Flip-flop. The
two binary words to be added are 11011 and 11011.The sum of the two numbers is stored in one of
the shift registers and the carry in the D Flip-flop. Assuming that D Flip-flop is set initially the
contents of the sum shift register and D Flip-flop respectively are:
(A) 10111 and 0 (B) 11011 and 1 (C) 11101 and 0 (D) 10111 and 1





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3
A
B
C
D
D
0
Q
0
D
1
Q
1
Q
1
Q
0
CLK
T
0
Q
0
Q
0
T
1
Q
1
Q
1
T
2
Q
2
Q
2
1
1 1
CLK
Q.10. In circuit shown in figure, when inputs A = B = 0, Then possible logic states of C & D are







(A) C = 0, D = 1 or C = 1, D = 0 (B) C = 1, D = 1 or C = 0, D = 0
(C) C = 1, D = 0 (D) C = 0, D = 1
Q.11. In the circuit shown below initially






Q
0
= Q
1
= 0 Then what are the values of Q
0
and Q
1
after 335
th
clock pulse.
(A) 00 (B) 01 (C) 10 (D) 11
Q.12. An X Y Flip-flop, whose characteristic table given below is to be implemented by use of a JK Flip-
Flop. This can be done by using

X Y Q
n+1

0
0
1
1
0
1
0
1
1
Q
n

Q
n

0

( ) ( ) ( ) ( ) A J X K Y B J X K Y C J Y K X D J Y K X = = = = = = = =
Q.13. Figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the
counter is Q
2
Q
1
Q
0
= 100 then its next state (Q
2
Q
1
Q
0
) will be:





(A) 011 (B) 100 (C) 111 (D) 101






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4
Q.14. Consider
b
X (54) = where b is the base of the number system. If X 7 = then value of base b is?
Q.15. In a 8 variable K-Map if 32 number of 1s are forming a group then number of literals in that group
after minimization will be?
Q.16. How many essential prime implicates are available in expression of f (A, B, C) (0, 2,3, 4,5, 7) = E ?
Q.17. A combinational circuit accepts a 2 bit binary number and output is square in binary. To design this
circuit using a ROM the minimum size of ROM required is:
(A) 2 2 (B) 4 2 (C) 4 4 (D) 8 4
Q.18. For the circuit shown in figure, which statements are correct, initially it is assumed that Q
0
Q
1
= 00






1. It is a Mod-3, counter 2. It is a Mod-4 counter
3. After 334 clock pulses output will be zero
4. After 339 clock pulses output will be zero
A. 1, 3, 4 B. 1, 4 C. 2, 3 D. 1, 3
Q.19. What is the value of output voltage for a given R - 2R ladder as shown in figure?
A. 1 Volt B. 2 volt C. 3 volt D. 4 volt







Q.20. The 4 1 MUX is shown in figure what is the value of output f(x, y, z)
A. x y z B. x y z C. xyz D. x y z + +













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5

+5v
o/p
A
B

S
0
S
1
S
2
2R 2R 2R 2R
R R
v
0
T
2
Q
2
T
1
Q
1
MSB LSB
CLK
X
Q.21. Consider the partial implementation of a 2-bit counter using T Flip-Flops following the sequence 0-
2-3-1-0 as shown below. To complete the circuit input X should be







A.
2
Q B. Q
2
+ Q
1
C.
1 2
(Q Q ) D. (Q
1
Q
2
)
Q.22. In 8085, Microprocessor the contents of the accumulator, after the following instructions are
executed will become
XRA A
MVI B FOH
SUB B
A. 01 H B. 0F H C. F0 H D. 10 H
Q.23. Let A = 11111010 and B = 0000 1010 be two 8, bit 2s complement numbers, then their product in
2s complement is
A. 11000100 B. 10011100 C. 10100101 D. 11010101
Q.24. A Boolean function f(x, y, z) = xyz is to be implemented by use of universal gates only. If
complement inputs are not available then Min
m
no. of 2-input, universal gate required are.
A. 1 B. 2 C. 3 D. 4
Q.25. An R 2R ladder type DAC is shown in Figure, if a switch status is 0 then 0 volt is applied and if a
switch status is 1 then 5 volt is applied to the corresponding terminal of DAC.






What is the step size of DAC in volt?
Q.26.







In the I.C. logic gate shown in figure. If threshold voltage V
BE
is o.75 volt and V
CE
(sat) = 0.2 V
calculate value of output voltage in volt. If V
A
= V
B
= 4.5 volt



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6
Q
0
Q
1
Q
2
Q
3
D
1
0
21
MUX
1
0
21
MUX
1
0
21
MUX
x
x
z
z
z
y
f
1
f
2
y
Q.27. In a dual slope integrating type digital voltmeter the 1
st
integration is carried at for 10 periods of
supply frequency of 50Hz. If reference voltage used is 2 volt then total conversion time in second for
an output of 1 volt is?
Q.28. Consider the following data in respect of a certain digital gate:
I
OH
= 0.2 mA, I
IH
= 40 A
I
OL
= 16 mA, I
IL
= 1.6 mA
Symbols have their usual meaning, what is the value of its fan-out?
Q.29. What is the Minimum number of gates required to implement the Boolean function (AB+C) if we
have to use only 2-input NOR, gate
Common data for question 30&31:






A 4-bit shift register which shifts 1 bit to right at every clock pulse is initialized to values (1000) for Q
0
Q
1

Q
2
Q
3
. The D input is derived from Q
0
, Q
2
and Q
3
through two XOR gates as shown in figure.
Q.30. After how many clock pulses Q
0
Q
1
Q
2
Q
3
will reappears as 1000.
(a) 4 (b) 6 (c) 7 (d) 8
Q.31. To what values should the shift register be initialized so that pattern (1001) occurs after the 1
st
clock
pulse??
(a) 0001 (b) 0010 (c) 1000 (d) 1001

Data for linked questions (32 33)
For a given MUX network as shown in fig.








32. The values of f
1
and f
2
are:
A. x y z & x
1
y + yz + x
1
z respectively B.
1 1
& x y z x y yz x z + + respectively
C. & x y z xy yz zx + + respectively. D. xy + yz + zx &xy+yz+zx respectively.
33. Above circuit can acts as a:
A. Full adder B. Full subtractor C. Comparator D. Parity checker





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1 1
1
1
1 1 1
00 01 11 10
CD
AB
00
01
10
11
1 1
00 01 11 10
BC
A
1 1
A
B
C
ECE-GATE 2014 Topic Test-Digital Solution

1. (B)





Y ABC AD BD CD = + + +
2. (D)

A AB AC = +



POS will be ( ) 0, 2, 4, 5 [

3. (B)




AND operation means Intersection of Min terms and OR operation means Union of Min terms

4. (D) 3Input EX OR



If in i/p even no of 1s are present then o/p = 0
If in i/p odd no of 1s are present then o/p will be 1.
Truth table

( )( ) A B C A B C A B C A B C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1





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A
B
C
A
B
C
A
B
C
A
B
C
(1)
(2) (3)
A
B
C
A
B
C


( ) ( ) ( ) ( ) A B C A B C A B C A B C A B C
0 0 1 1 1
1 1 0 0 0
1 1 0 0 0
0 0 1 1 1
1 1 0 0 0
0 0 1 1 1
0 0 1 1 1
1 1 0 0 0



( )
( )
A B C A B C
A B C
=
=

Conclusion for 3 input XOR:






Conclusion for 3 input XNOR:



5. (C)






2 1 0
3 2 1 0
3 2 1 0
3 3 2 1 0
C C C
A A A A
B B B B
C S S S S

( )
for n-bit propagation delay
= n 1 C S +

7
9
T 3 5 10 25nsecond
1
Rate = 4 10 /second
25 10

= + =
=

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9
0
1
21 C =AB
y
A
0
1
A
0
B
B
B
0
1
21
B
1
0
B
416
0
7
416
8
15
I
2
I
1
I
0
I
3
I
2
I
1
I
0
0
3
4
0
7
3
0
3
1
2
E
I
1
I
0
I
1
I
0
I
1
I
0
I
1
I
0
12
15
8
11
416
6
15
6. (D)
n
2 1 MUX it can express up to (n+1) variable (When inverter is given)
n 1
2 1 MUX

n variable
For dual MUX.
( )
n
2 1 n 2 variable +
If inverter is not given then there is a need of an extra 2:1 MUX
7. (D) S A B AB AB = = +
C = AB




But if inverter is not given then




So for Half adder there will be need of 3 MUX.

8. (B) 4 16, decoder
























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10
A
B
D
C
9. (D)
1 1 0 1 1
1 1 0 1 1
1 for carry
1 1 0 1 1 1
C

+

10. (A)


A = B = 0
Let C = 0 then D = 1, C = 0
Let C = 1 then D = 0, C = 1
Either C = 0 & D = 1 or C = 1 & D = 0.
11 (B) MOD 4-Jhonson Counter

1 0 0 1
1 0
Q Q D Q 1
0 0 D Q 0
= =
= =

335
83 4 3
4
= + +
0 1
0 1 1 0
Q 1 , Q 0
D Q 1, D Q 1
= =

= = = =

0 1
0 1
Q 1, Q 1
D 0, D 1
= =

= =

After 3
rd

{
0 1
Q 0, Q 1 = =
12. (D) JK Table

n 1
n
n
Y Y Q
0 0 1
0 1 Q
1 0 Q
1 1 0
+

n 1
n
n
J K Q
0 0 Q
0 1 0
1 0 1
1 1 Q
+

Take J Y = &K = X











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11
J
2
K
2
Q
2
Q
2
V
CC
J
1
K
1
Q
1
Q
1
V
CC
J
0
K
0
Q
0
Q
0
i
SB
V
CC
V
CC
CLK CLK CLK
Q
0
V
CC
CLK CLK CLK
By OR Gate
V
CC
Pr
V
CC
Q
0 Q
2
Pr Pr
Q
0
f
Pr
V
CC
Q
0 Q
2
Pr Pr
Q
2
V
CC
Q
1
Q
1
K
0
J
0 J
1
K
1
J
2
K
2
1 1
1 1
1 1
00 01 11 10
00
01
11
10
1 1
13. (D) Clock edge O/P given O/P Taken
1 0 1 up Counter
Mod 5 UP Counter:








2 1 0
Q Q Q
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

MOD-5 Down counter:

1 1 1 7
1 1 0 6
1 0 1 5
1 0 0 4
0 1 1 2
0 1 0 2 101
0 0 1
0 0 0

14. Ans=9
( )
1 0
b
X 54 5.b 4.b 5b 4 = = + = +

x 7 x 49 5b 4 49
5b 45 b 9
= = + =
= =

15. Ans=3






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12
ROM
if P add. lines
N is the no of O/P bit
b
3
b
2
b
1
b
0
2 4
= 44 should be
2
A B
1
1 1
1
00 01 11 10
CD
AB
00
01
11
10
1
1
1
00 01 11 10
0
1
1
1 1
1 1
1

Rule: Let n = variable of K-Map
2
m
= 8 m = 3.
number of terms in minimised group = nm
m no of bits for pairing.

=

m
n 8 2 32&m 5
n m 8 5 3
= = =
= =

16. Ans=0
( ) ( ) f A, B, C, D 4, 5,8,12,13,14,15 =

It has 3 prime Implicates




A prime implicate is said to be EPI if it covers at least one minterm which is not covered by other prime
implicates. ( ) ( ) f A, B, C, D 0, 2, 3, 4, 5, 7 =

This prime implicates is also known as cyclic prime implicates
17. (B) Size of ROM = MN
P
M 2 : P Address Lines =
3 2 1 0
A B b b b b
0 0 0 0 0 0
0 1 0 0 0 1
1 0 0 1 0 0
1 1 1 0 0 1




Size of ROM =
P
M N 2 N =








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13
f
z
y
x
size of ROM = 4 2
For 3 bit Square ROM Size of ROM must be = 8 4
For 4 bit Square ROM

18. (B) Q
1
Q
0

0 0
J
0
= 1, K
0
= 1, J
1
= 0, K
1
= 1 Q
0
= 1, Q
1
= 0
J
0
= 1, K
0
= 1, J
1
= 1, K
1
= 0 Q
0
= 0, Q
1
= 1
J
0
= 0, K
0
= 1, J
1
= 0, K
1
= 1 Q
0
= 0, Q
1
= 0
So 00 01 10 00 (MOD 3)
339/3=113 so after 339 clock cycles it will be reset to zero.

19. (A) A value of output voltage V
o
is given by

( )
( )
1 2
1 2 0
1
.2 .2 ......... .2
2
4
1.2 1.0
8
N N R
N N N
V
b b b
volt


+ + +
= =

20. (D) f = x y x y x y xyz + + +
By K Map f x y z = + +

21. (D) It is a synchronous counter and then use K-Map.
22. (D) XRAA Accumulator has zero value
MVI B F0 B will have F0
SUB B 00 F0
00 + 10 = 10
23. (A)
A 11111010 (-6)
B 00001010 (+10)
A.B (-60) 11000100
24. (B)


( )
( )
.
f xy z
xy z
= +
=










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14
R R
2R 2R 2R 2R
S
0
S
1
S
2
1 0 0
Put here (100)
V
0
5v
low
Q
3
Q
2
High
Q
1
A
B
V = V
for cut off
0 CC
V = 2.0 low
0

25. Ans=0.625




For valid R2R ladder
Last should be R2R

( )
n 1 n 2 0 R
0 n 1 n 2 0 n
R
V
V b .2 b .2 .......b 2
2
V Reference Voltage
n = no of bits
L.S.B Step size or Resolution are same thing


= + +
=
=

( )
0
0 3
5
5
V 1.2 0.625V
8
2
= = =

26. Ans=0.2


TTL always works as NAND Gate








27. Ans=0.1
In a dual slope integrating type digital voltmeter

1
in ref
T
v v
T
= where T
1
is first integration time

1
1
2
1
10 0.2sec
50
1 , 2
1 0.2
0.1sec
2
in ref
in
ref
T
v v v v
v T
T
v
= =
= =

= = =

28. Ans=5 Fan-out =
0.2
5
0.04
=



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15
Fan-in =
16
10
1.6
=
Smaller of both Fan-in & Fan-out will be required Fan-out

29. Ans=3
f(A, B, C) = (A+C) (B+C)






30. B
31. B
32. A
33. B