Computer Organization and Design

Homework 5 – Due Date:31/10/2014
1) This series of 32-bit WORD addresses is accessed (Memory with Word Addressing scheme):
2, 3, 11, 16, 21, 13, 64, 48, 19, 11, 3, 22, 4, 27, 6, 11
Assume a direct-mapped cache with 16 one-word blocks that is initially empty. Label each
address request and show the final contents of the cache.
Address

Hit or Miss

Block

2

M

0

3

M

1

11

M

2

16

M

3

21

M

4

13

M

5

64

M

6

48

M

7

19

M

8

11

M

9

3

M

10

22

M

11

4

M

12

27

M

13

6

M

14

11

H

15

Data at Address

Final contents of cache

Class 11ECE Name:

Page 1

2) Like Problem 1. but now assume that the cache is direct-mapped. Address Block Address Hit or Miss Block 2 0 3 1 11 2 16 3 21 Data at Block Final contents of cache 13 64 48 19 11 3 22 4 27 6 11 Class 11ECE Name: Page 2 . 4-word blocks. total 16 word capacity.

but assume that the cache is: a. one-word blocks. 2-way set associative. total 16 word capacity Assume a Least Recently Used (LRU) replacement policy where applicable. Fully associative. total 16 word capacity b. one-word blocks.3) Like Problem 1. Address 2 3 11 16 21 13 64 48 19 11 3 22 4 27 6 11 2-way SA H or M Set 0 1 2 3 4 5 6 7 Data at Block Address 2 3 11 16 21 13 64 48 19 11 3 22 4 27 6 11 FA H or M Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Data at Block Class 11ECE Name: Data at Block Page 3 .

b) Calculate the number of memory bits required to implement each cache. Indicate the width of each field including data. Our layout team has given us the three options shown below: Level 1 Cache Type 8KB Fully-Associative 16 KB 4-way SA 16KB Direct Mapped Write Policy Write-Back Write-Through Write-Back. and any necessary valid or dirty bits. c) Calculate the average memory access time for the whole system with each cache. We indicate the miss rate for all accesses that enter a given level). Class 11ECE Name: Page 4 . FetchOn-Write-Miss Other Parts of Memory System Type Miss Rate 128 KB L2 Cache 2% 512 MB Main Memory 0% Block Size 128 Bytes 64 Bytes 32 Bytes Miss Rate 10% 5% 8% Access Time 1 clock cycle 1 clock cycle 1 clock cycle Access Time 10 clock cycles 100 clock cycles For each: a) Draw a picture showing how many rows and columns the cache has.4) We are designing a new embedded processor with word addressing scheme (32-bit) used for main memory and we are trying to decide what kind of L1 cache to include in our existing memory hierarchy (the L2 and main memory have already been designed. tag.