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Set No.

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Code No: V3121/R07

III B.Tech I Semester Supplementary Examinations, May 2010
DIGITAL IC APPLICATIONS
( Common to Electronics & Communication Engineering and Electronics &
Instrumentation Engineering)
Time: 3 hours
Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????
1. (a) Design CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and
function table.
(b) Draw the resistive model of a CMOS inverter and explain its behavior for
LOW and HIGH outputs.
[8+8]
2. (a) What is the necessity of separate interfacing circuit to connect CMOS gate to
TTL gate? Draw the interface circuit and explain the operation.
(b) Design a TTL three-state NAND gate and explain the operation with the help
of function table.
[8+8]
3. (a) Write a VHDL Entity and Architecture for the following function.
F (x) = (a + b) (c ⊕ d)
Also draw the relevant logic diagram.
(b) Write a VHDL Entity and Architecture for a 3-bit ripple counter using FlipFlops?
[8+8]
4. (a) Write a process based VHDL program for the prime-number detector of 4-bit
input and explain the flow using logic circuit.
(b) Explain data-flow design elements of VHDL.

[10+6]

5. (a) Show the logic diagram of 74X283 binary adder. Explain the principle of
generating sum and carry at every stage using the logic diagram.
(b) Design a 24-bit group ripple adder using 74x283 ICs?

[8+8]

6. A simple floating-point encoder converts 16-bit fixed-point data using four high
order bits beginning with MSB. Design the logic circuit and write VHDL data-flow
program.
[16]
7. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit
counter in both modes and estimate the propagation delay.
(b) Design a modulo-88 counter using 74X163 Ics.

[8+8]

8. (a) Design an 8x4 diode ROM using 74X138 for the following data starting from
the first location.
1, 4, 9, B, A, 0, F, C
of remove
2
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. 1 Code No: V3121/R07 (b) Draw the internal structure of synchronous SRAM and explain its operation? [8+8] ????? of remove 2 Please purchase PDF Split-Merge on www.com2 to this watermark.Set No.verypdf.

5V and CL = 10P F . VL = 2. (a) Discuss the steps in VHDL design flow.Set No. (a) Explain how to estimate sinking current for low output and sourcing current for high output of CMOS gate. iv.D (1. 9. [8+8] 4. i.C. Voltage levels for logic ‘1’ & logic ‘0’ DC Noise margin Low-state unit load High-state fan-out [8+8] 3.B. Assume VL as stable state voltage. ii. 7. Design the logic circuit and write VHDL data-flow program. (a) Design a TTL three-state NAND gate and explain the operation with the help of function table. iii. (b) Explain the following terms with reference to TTL gate.verypdf.com1 to this watermark. [16] of remove 2 Please purchase PDF Split-Merge on www. May 2010 DIGITAL IC APPLICATIONS ( Common to Electronics & Communication Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ????? 1. . [8+8] 2. 5. (b) Analyze the fall time of CMOS inverter output with RL = 100Ω.Tech I Semester Supplementary Examinations. A simple floating-point encoder converts 16-bit fixed-point data using four high order bits beginning with MSB. 13) + d (4. (a) Design a logic circuit to detect prime number of a 4-bit input? Write the VHDL program for the above design? (b) Design the logic circuit and write a data-flow style VHDL program for the following function? [8+8] F (P ) = ΣA. 2 Code No: V3121/R07 III B. 6. F(x) = (a+b)(c+d)(e+f) Also draw the relevant logic diagram. (b) Write a VHDL Entity and Architecture for the following function. (a) Draw the digits created by 74x49 seven-segment decoder for non-decimal inputs 1010 through 1111. (b) Realize the following expression using 74×151 IC [8+8] f (X) = ABC + ABC + ABC 6. 15) 5.

9. [8+8] 8.Set No.com2 to this watermark. F. (b) Design a modulo-88 counter using 74X163 Ics. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit counter in both modes and estimate the propagation delay. . C. 2 Code No: V3121/R07 7. E.verypdf. 1. With the help of timing waveforms discuss DRAM access. (a) Explain the internal structure of 64K×1 DRAM. 2. [8+8] F. A ????? of remove 2 Please purchase PDF Split-Merge on www. (b) Design an 8×4 diode ROM using 74×138 for the following data starting from the first location.

Explain the circuit with the help of logic diagram and function table? (b) Explain the following terms with reference to CMOS logic. (a) Draw the circuit diagram of basic TTL NAND gate and explain the three parts with the help of functional operation. iv. (a) Design a switch debouncer circuit using 74×109 IC. [8+8] 6. iii. (b) Explain the use of Packages Give the syntax and structure of a package in VHDL [8+8] 4.Tech I Semester Supplementary Examinations. i. (b) Using the above subtractor design a 8-bit ripple subtractor and write the corresponding VHDL program in structural style of modeling.verypdf. Explain the operation using timing diagram. 3 Code No: V3121/R07 III B. Logic ‘0’ and Logic ‘1’ Noise margin Power supply rails Propagation delay [10+6] 2. power consumption. ii. of remove 2 Please purchase PDF Split-Merge on www. [8+8] 3. (a) Write a VHDL Entity and Architecture for the following function? F(x) = a ⊕ b ⊕ c Also draw the relevant logic diagram. (a) Design a 4-input CMOS OR-AND-INVERT gate. . May 2010 DIGITAL IC APPLICATIONS ( Common to Electronics & Communication Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ????? 1. (a) Design a barrel shifter for 8-bit using three control inputs? Write a VHDL program for the same in data flow style. (b) Write a behavioral VHDL program to compare 16-bit signed and unsigned integers [8+8] 7. (a) Design a full subtractor with logic gates and write VHDL data flow program for the implementation of the above subtractor.com1 to this watermark. (b) List out TTL families and compare them with reference to propagation delay. [16] 5. speed-power product and low level input current. Write the structural VHDL program for the same. Design a logic circuit to detect prime number of a 5-bit input.Set No.

(b) Explain the internal structure of 64K×1 DRAM. (a) With the help of timing waveforms. explain read and write operations of SRAM. Write a VHDL program for the same in structural style.verypdf. 3 Code No: V3121/R07 (b) Discuss the logic circuit of 74×377 register.com2 to this watermark. With the help of timing waveforms discuss DRAM access. [8+8] 8.Set No. . [8+8] ????? of remove 2 Please purchase PDF Split-Merge on www.

Explain the operation with the help of function table. [8+8] F (X) = ΣA. Provide the logic diagram.Tech I Semester Supplementary Examinations. (b + c) Also draw the relevant circuit diagram (b) Design CMOS 4-input OR-AND-INVERT gate. [8+8] of remove 2 Please purchase PDF Split-Merge on www. DC Noise margin. 12. A simple floating-point encoder converts 16-bit fixed-point data using four high order bits beginning with MSB. [8+8] 4. (b) It is necessary to generate 6 control lines in regular intervals sequentially. (b) Design the logic circuit and write a data-flow style VHDL program for the following function. Design the necessary circuit using 74×163 and 74×138. Using this principle design a 6-bit carry look ahead adder.C. 5. (a) What is importance of Entity and Architecture in VHDL? Explain with suitable examples. May 2010 DIGITAL IC APPLICATIONS ( Common to Electronics & Communication Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks ????? 1. (a) Explain data-flow design elements of VHDL. 15) + d (3. [8+8] 3.Set No. . 4.B.com1 to this watermark. 11) 5. (a) Design an Excess-3 decimal counter using 74×163 and explain the operation with help of timing waveforms.D (1. (b) What are the different data objects supported by VHDL? Explain scalar types with suitable examples. (a) Design a transistor circuit of 2-input ECL NOR gate. 7. [16] 7. 14. Explain the circuit with the help of logic diagram and function table? [10+6] 2. TTL and ECL with reference to logic levels. 4 Code No: V3121/R07 III B. Explain the principle of carry look ahead Adder. (a) Design a CMOS transistor circuit that has the functional behavior as f (x) = (a + c). Write the data flow VHDL program for the same. propagation delay and fan-out.verypdf. [16] 6. Design the logic circuit and write VHDL data-flow program. (b) Compare CMOS.

.verypdf.Set No. 4 Code No: V3121/R07 8. (b) With the help of timing waveforms. EPROM and EEPROM technologies differ from each other. [8+8] ????? of remove 2 Please purchase PDF Split-Merge on www. (a) Discuss how PROM. explain read and write operations of SRAM.com2 to this watermark.