ECE 4514


LAB #7

DUE: 4/5/2007


In this lab you will lay the foundation for a graphics application by implementing a simple VGA controller producing a stable, static test pattern of your choosing. All eight colors available on the Spartan-3E board should be used. Hopefully you have access to a CRT or LCD monitor that can accept VGA input (640x480 resolution, 60 Hz non-interlaced refresh rate). If not, there are VGA monitors available in the CEL. You should first check that the monitor works with your Spartan board by copying the vga_test.bit configuration file from Blackboard to your Lab7 project directory. Run iMPACT, right click on the XC3S500E icon, select Assign New Configuration File, and choose vga_test.bit. The monitor should display a static pattern of ten vertical bars using all eight colors. Be sure to set the configuration file back to vga_top.bit after the test. Part 1: Synthesis and Implementation Two files are provided for you on Blackboard: vga_top.v and vga_top.ucf. You should create a file named vga_controller.v that contains your vga_controller module and any other modules that vga_controller instantiates. All three files (vga_top.v, vga_top.ucf and vga_controller.v) should be added to your Lab7 project created in WebPack. The vga_top module instantiates vga_controller and connects it to the FPGA pins specified in vga_top.ucf. The vga_top module also instantiates a Digital Clock Manager to convert the 50 MHz Spartan-3E board clock to a 25 MHz clock used by the vga_controller module. A DCM is the preferred way of deriving one clock from another. Your vga_controller module should have the following interface:
module vga_controller(red, green, blue, hsync, vsync, led, clock, reset); output reg red; // one bit controlling the red color output reg green; // one bit controlling the green color output reg blue; // one bit controlling the blue color output hsync; // active-high VGA horizontal sync signal output vsync; // active-high VGA vertical sync signal output [7:0] led; // available for debug output input clock; // should be close to VGA spec's 25.175 MHz input reset; // active-high synchronous reset

The vga_top module inverts the hsync and vsync signals produced by the vga_controller. The reset signal is connected to the bottom push button, and the led’s are available for displaying any debug information that you wish. The VGA DB-15 connector is on the top left of the board, nearest the power jack and switch. Your VGA controller needs to generate the hsync and vsync waveforms shown at the beginning of, except that within the vga_controller module the hsync and vsync signals are active high since they are inverted in vga_top. First focus on getting the hsync and vsync signal timing correct with a single color that fills the screen. Later you can make the color a function of the horizontal and perhaps vertical position to produce a pattern. The heart of the VGA controller is a horizontal pixel counter and a vertical line counter; a general finite state machine structure is not necessary. According to the VGA Industry Standard 640x480 pixel mode section of, the horizontal counter should increment modulo 800 and the vertical counter should increment modulo 525 to account for operations that occur before and after drawing each line and each field (screen). Both counters use the 25 MHz clock. The horizontal counter is incremented every clock cycle, while the vertical counter is enabled when there is a high-to-low transition on the hsync (i.e. when hsync is high in one clock cycle and low during the next clock cycle). The hsync (respectively vsync) signal is asserted when the horizontal (respectively vertical) counter is within the horizontal (respectively vertical) sync range indicated in the VGA Industry Standard 640x480 pixel mode section. For the sake of future labs, the red, green and blue signals should be non-zero only when visible pixels are being displayed. Part 2: The Report Create a directory containing vga_controller.v, vga_top.bit and a PDF document briefly describing the test pattern generated. A picture of the pattern taken with a digital camera would be ideal, but the pattern can be illustrated with a drawing tool if you do not have access to a digital camera. Do not submit any other files generated by ISE. A ZIP archive of the directory should be submitted to Blackboard’s Digital Dropbox before the start of class on Thursday April 5. The archive should be named, where your_pid is replaced with your PID.

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