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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 4, April 2012)

CNTFET based Logic Circuits: A Brief Review


Sanjeet Kumar Sinha1, Saurabh Choudhury2
1,2

Department of Electrical Engineering, NIT Silchar, Assam-788010, India


sanjeetksinha@gmail.com,
saurabh1971@gmail.com

Nanoscaled alternatives to bulk silicon transistors are


therefore being pursued. Ultrathin body devices such as
FinFETs have received an increasing attention in recent
years.
These limits can be overcome to some extent and
facilitate further scaling down of device dimensions by
modifying the channel material in the traditional
MOSFET structure with a single carbon nanotube.
Despite all the challenges associated with scaling, silicon
based semiconductor technology will continue to scale
down in the future. However, research is progressing
toward improving carrier transport in the transistor
channel region [3]. One possible option is to use carbon
nanotubes (CNTs) to realize high channel mobility
devices

Abstract In this paper at first a brief review of carbon


nanotubes (CNTs) is given and then an extensive survey of
CNTFET (carbon nanotube field effect transistor) based
logic circuits are discussed with the most recently reported
CNTFET logic circuits.
Keywords MOSFETs, technology scaling, CNTFETs,
carbon nanotubes (CNT), chiriality.

I. INTRODUCTION
The scaling down of devices has been the driving
force towards technological advancements. Dimension of
individual devices in an integrated circuit followed
Moores law [1]. Today silicon based MOSFETS (Metal
Oxide Transistor Field effect transistor) have technology
sizes less than 60nm are common in the world of
electronics. As the size become smaller, scaling the
silicon MOSFET becomes increasingly harder. Further
scaling has faced serious limits related to fabrication
technology and device performances. This limits include
quantum mechanical tunneling of carriers through the
thin gate oxides, quantum mechanical tunneling of
carriers from source to drain and from drain to body,
control of the density and location of dopant atoms in the
MOSFET channel and source drain region to provide
high on off current ratio, the finite sub-threshold slope.
Many solutions are proposed to overcome these
limitations. Some solutions include modifications on the
existing structures and technologies with a hope of
extending their scalability. Other solutions involve using
new materials and technologies to replace the existing
silicon MOSFETs. Researchers currently focused on
identifying alternatives which would enable continued
improvement in the performance of electronics systems
are high dielectric constsnt (HighK), metal gate
electrode, double gate FET. High-K dielectric materials
are useful for gate insulators as they can provide efficient
charge injection into transistor channels and reduce direct
tunnelling leakage currents. The very large scale
integration (VLSI) systems depends on silicon MOS
technology,
Industry Technology Road Map has
predicted that in the nano regimes, the expected high
density will encounter substantial difficulties in terms of
physical phenomena and technology limitations, possibly
preventing the continued improvements in figures of
merit, such as low power and high performance.

II. CARBON NANOTUBE (CNT)


Carbon Nanotubes are graphene strips rolled up into
tubular shapes. Planar graphite is arranged in a hexagonal
structure due to its sp2 junctions, carbon nanotubes also
display this honeycomb structure on a molecular level
(Figure 1). Iijima who observed first in 1991, that carbon
nanotubes constitute a class of macromolecules with
unique mechanical thermal and electrical properties.
Some of these properties stem from the close relation
between carbon nanotubes and graphite, and other from
their one-dimensional aspects [4]. Figure 1 shows the
microscopic view of a carbon nanotube as illustrated in
[5].

Figure 1: Microscope Image [5] of a Carbon Nanotube

500

International Journal of Emerging Technology and Advanced Engineering


Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 4, April 2012)
Carbon nanotubes offer alternative uses in various
applications. These applications include their use as
electron source in field emission devices, interconnects
and FETs [6].
The CNTs shown in Figure comprised of one layer
of carbon atoms, this is called Single Walled Carbon
Nanotubes (SWCNT). There are also Multi Walled
Carbon nanotubes (MWCNT) that are constituted by cocentric SWCNTS of different diameters. The diameters
of SWCNTs can be as small as 0.4nm [7]. The typical
diameters change between 0.7-3nm with mean diameter
at 1.7nm [8]. The importance of the CNT diameter is that
it determines the bandgap energy of the tube. The
following relation expresses the SWCNT bandgap energy
[9].

An SWCNT can act as either a conductor or a


semiconductor, depending on the angle of the atom
arrangement along the tube. This is referred to as the
chirality vector and is represented by the integer pair (n
,m). A simple method to determine if a CNT is metallic
or semiconducting is to consider its indexes (n, m). The
nanotube is metallic if n = m or n m = 3i, where i is an
integer. Otherwise, the tube is semiconducting [10]. The
diameter of the CNT can be calculated based on the
following.

=
where a0 = 0.142 nm is the inter-atomic distance between
each carbon atom and its neighbor.
The IV characteristics of the CNTFET are similar to
MOSFET. The threshold voltage is defined as the voltage
required to turn-on the transistor. The threshold voltage
of the intrinsic CNT channel can be approximated to be
of first order as the half band-gap is an inverse function
of the diameter [11]. Similar to the traditional silicon
device, the CNTFET also has four terminals. As shown
in Figure 3, the undoped semiconducting nanotubes are
placed under the gate as channel region, while heavily
doped CNT segments are placed between the gate and the
source/drain to allow for a low series resistance in the
ON-state [12]. As the gate potential increases, the device
is electro-statically turned on or off via the gate.

=2
Where Egap is the bandgap, 0 is the carbon-to-carbon
distance (0.142nm) and d is the diameter of the nanotube.
As d gets larger the bandgap becomes smaller and the
nanotube becomes more conducting. This can be thought
as the tube with reduced curvature looking more like
planar graphene. Electrical transport inside the CNTs is
affected by scattering caused by defects and lattice
vibrations that lead to resistance, similar to that in bulk
materials. The one dimensional nature of the CNTs and
their strong covalent bonding drastically affect the
processes. Semiconducting behaviour of nanotubes is
affected by their chiralities. In a nanotube chirality is the
angle difference between the graphene strips orientation
and the axis of the resulting nanotube (Figure 2).
Chirality

Figure 2: Chirality of a CNT [9]

Semiconducting behavior of CNT is the main reason for


the strive to build CNT Field effect Transistors
(CNTFET)
III. THE CNTFET
Carbon nanotube field effect transistor (CNTFET) uses
CNT as their semiconducting channels. A single-wall
CNT (SWCNT) consists of one cylinder only, and the
simple manufacturing process of this device makes it
very promising for alternative to MOSFET.

Figure 3: Schematic diagram of a CNT transistor [12] (a) Cross


sectional view. (b) Top view

501

International Journal of Emerging Technology and Advanced Engineering


Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 4, April 2012)
The gate-to-source voltage that generates the same
reference current is taken as the threshold voltage for the
transistor that has different chirality. CNTFETs provide a
unique opportunity to control threshold voltage by
changing the chirality vector, or the diameter of the CNT.
Figure 4 shows the threshold voltage of both P-CNTFET
and N-CNTFET obtained from simulation for various
chirality vectors (various n for m = 0) [13]. A synthesis
process for fabricating SWCNTs with the desired (n, m)
chirality structure has been proposed in [14]. The
CNTFETs are particularly attractive due to possibility of
near ballistic channel transport, easy application of high
k gate insulator and novel device physics. Although most
of the work on CNTFETs has concentrated so far on their
d.c. properties, the a.c. properties are technologically
most relevant. Theoretically, it is predicted that a short
nanotube operating in the ballistic regime, and the
quantum capacitance limit should be able to provide gain
in the THz range [15].

The first logic circuits with field-effect transistors


based on single carbon nanotubes were built as resistiveload circuits [16]. Electrostatic doping of the nanotube
from p-doping to n-doping and integration of multiple
devices on a single chip were also attempted for the first
time. One, two, and three-transistor circuits were
demonstrated experimentally to exhibit a range of digital
logic operations such as NAND gate, NOR gate, inverter,
SRAM cell and ring oscillator. For complementary logic,
technologies described in [17] were used to build the first
reported complementary CNTFET logic gates. The
growth of nanotubes on sapphire or quartz substrates was
also reported recently.
The design of elementary circuits based on such nano
devices is thus a growing domain necessary to extend the
semiconductor industry beyond CMOS. The potential of
CNTFETs in the context of advanced MOS technologies
for the realization of elementary logic functions, their
physical characteristics such as current density,
theoretical transition frequency, as well as their
versatility and maturity`, CNTFETs among the most
promising nanodevices in line to succeed the MOS
transistor. CNTFET replaces the MOSFET, existing logic
functions directly to a new technology. It is proved that a
significant performance gain can be achieved justifying a
shift in fabrication technologies to CNTFET based logic
circuits. Specific properties of the CNTFET allowing the
creation of completely new logic functions, inaccessible
to MOSFET based circuits.
Reconfigurable logic circuits are recognized as the
main way to achieve high performance systems on chip.
Current reconfigurable systems however are inefficient in
terms of number of devices used to realize a single
function. The double gate CNTFETS can be used to build
a dynamically reconfigurable 8- function logic gate
(CNT-DR8F) that offers reconfigurability not available
with MOSFET technology, at comparable or better speed
and power figures[18]. The double-gate CNTFET was
proposed in [19] to improve channel mobility and control
of the off-state in CNTFETs.

Figure 4: Threshold voltage of CNTFETs versus n (for m = 0) as


reported in [13]

Comparison of CNTFET-based logic circuits to CMOS


logic circuits, is necessary to establish means of
evaluation for performance metrics such as current
density, device switching speed , propagation delay
through the gates, switching energy, operating
temperature, cost. However, the technology is not
sufficiently mature to enable meaningful comparisons as
the positioning techniques must still evolve to enable
high-yield volume manufacturing and contact technology
must be improved to reduce the impact of contacts on
circuit performance.
IV. CNTFET- BASED LOGIC CIRCUITS
The CNTFET is a promising alternative to the silicon
transistor for low-power and high-performance design
due to its ballistic transport and low OFF-current
properties.

(a)

502

International Journal of Emerging Technology and Advanced Engineering


Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 4, April 2012)
Recently, ambipolar devices have been reported,
which conduct under both positive and negative gate
voltages. Ambipolar behavior has been reported in
CNTFETs [21]. The electrostatic field applied at the back
gate of the CNT-to-metal contacts is responsible for
controlling the device polarity. The ambipolar library
outperforms the unipolar library by reducing the number
of logic levels by 42%, the delay by 26%, and the power
consumption by 32%, based on the predictions of the
performance of defect-free CNTFETs versus MOSFETs
in [22]. When intrinsic CNTs are used as the channel
material in CNTFETs, then the fabricated devices have a
Schottky barrier at the contacts and exhibit ambipolar
behavior, i.e., they conduct both electrons and holes. The
device has two gates G and PG. The gate G turns the
device on or off, as the regular gate of a MOSFET, while
the polarity gate (PG) controls the type of polarity setting
to p-type or n-type. If a large positive voltage is applied
at PG, the device behaves as a n-type transistor, while a
large negative voltage applied at PG would set the
polarity to p-type.

(b)
Figure 5: Double gate CNTFET. (a) Top view (b) Cross-sectional
view

A resistive-load CNTFET-based ternary logic design


has been proposed to implement ternary logic based on
CNTFET [20]. A novel design technique for ternary logic
gates based on CNTFETs is proposed and compared with
the existing CNTFET logic gate designs. The proposed
ternary logic gate design technique combined with the
conventional binary logic gate design technique provides
an excellent speed and power consumption
characteristics in datapath circuit such as full adder and
multiplier.
Ternary logic functions are defined as those functions
having significance if a third value is introduced to the
binary logic. The ternary values to represent false,
undefined, and true are 0, 1, and 2 respectively. One of
the main advantages of ternary logic is that it reduces the
number of required computation steps. Since each signal
can have three distinct values, the number of digits
required in a ternary family is log3, 2 times less than
required in binary logic.

Figure 7: Ambipolar Transistor [21]. (a) Layout. (b) Symbol. (c) ntype and p-type

The logic 0 at PG is defined as the required positive


voltage to set the n-type polarity, while the logic 1 is
defined as the required negative voltage to set the p-type
polarity. the combination of the ambipolar design
methodology with the CNT technology results, on
average, in 7 lower delay, 57% less power consumption,
and 20 less energy delay product (EDP) in comparison
to circuits mapped in CMOS technology [23].
Classical single-gate CNTFETs exhibit unfavorable
features that constrain their usefulness in CMOS-like
circuits [24]. Double gate CNTFET (DG-CNTFET) was
created to mitigate these problems [25]. Reconfigurable
computing is recognized today as the main way to
achieve high performance systems on chip in the context
of costs .Specific electrical properties of the DGCNTFET to build a reconfigurable logic block. A
dynamically reconfigurable logic gate (CNT-DR8F) is
presented in [26]. The CNT-DR8F is made up of 7
CNTFETs shared in two logic layers, the first layer
performs an elementary logical operation and the second
layer works in an inverter mode. The realization of a
dynamically reconfigurable 8- function logic gate using
this device is described, with its characteristics as power
consumption.

Figure 6: Transient delay of CNTFET-based Ternary HAs [20]

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International Journal of Emerging Technology and Advanced Engineering


Website: www.ijetae.com (ISSN 2250-2459, Volume 2, Issue 4, April 2012)
V. CONCLUSIONS
In this paper a literature review on Carbon nanotube
field effect transistors (CNTFETs) is presented first,
followed by a brief assessment on CNTFET based logic
circuits. The results presented in figure 6, the design
approach using the ternary logic gate combined with
binary gates is a viable solution for low-power and highperformance very large-scale integrated (VLSI) design
with CNTFETs. A power saving of 57% can be achieved with

[14]

[15]
[16]
[17]

the ambipolar CNTFET library over a conventional CMOS


library. The dynamically reconfigurable universal cells

[18] J. Liu, I. OConnor, D. Navarro


, F. Gaffiot 2007,
Novel CNTFET-based Reconfigurable
Logic Gate
Design, DAC 2007, California, USA.
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Ternary
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an arithmetic
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[22] A P. Dhande and V. T. Ingole 2005, Design &
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exhibit the possibility to realize dense, regular and highly


reconfigurable circuits in platform-based system on chip
design.
One of the major challenges faced by the CNFET is
the presence of unwanted metallic tubes that has an
unfavourable impact on the delay, power, and functional
yield of carbon nanotube based circuits. The unwanted
growth of metallic tubes during the fabrication of CNTs
is a major challenge that will affect the fabrication of
robust CNT-based circuits.
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