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loads (Part 1) BJT Current Sources

Preamble Biasing BJT Circuits to Achieve Forward-active

Mode

Single Base Resistor Biasing

Advantages

Simple

Disadvantages No bias stabilisation,

i.e. Q-point varies

with

Requires large

resistors (Ms), i.e.

uses large area,

which is an

important issue in IC

design.

design

Advantages

Simple

Disadvantages No bias stabilisation,

i.e. Q-point varies

with

Requires large

resistors (Ms), i.e.

uses large area,

which is an

important issue in IC

design.

Figure 1: Common-emitter circuit

with a single bias resistor in the base.

Advantages

Disadvantages

Figure 2: Common-emitter circuit

with an emitter resistor and voltage

divider bias circuit in the base.

Smaller resistors

required (k

range)

RE has provided

bias stabilisation

and negative

feedback

Resistor size is

still undesirable

for IC design

Advantages

Disadvantages

Figure 3: Simple transistor circuit

biased with both positive and

negative dc voltages.

Used for

differential

amplifier biasing

Allows, in

certain

application, for

elimination of CC

and allows use of

dc input voltages

as input signals

Resistor size is

still undesirable

for IC design.

Bias stabilisation

Avoiding devices consuming large area, i.e. avoiding the use of

moderate and large resistors

Can be a current source that establishes the

quiescent collector current ICQ as shown in

Figure 4.

Advantages:

o Emitter current becomes independent of

and RB

o Collector current and C-E voltage are

independent of transistor gain, for

reasonable values

o Value of RB (hence Rin) can be increased

Figure 4: Bipolar

circuit affecting

with ideal bias stability

without

current-source biasing.

Two-Transistor Current Source a.k.a Current Mirror

Basic building block in IC current

source design

Q1 is diode-connected

Q1 and Q2 are matched, i.e.

identical,

IB1 = IB2

IC1 = IC2

Connected as a

diode; when X

supplies are

connected, BEjunction is

forward biased.

Figure 5: Two-transistor current

source with reference resistor R1.

I REF

V VBE V

R1

(1.1)

Current relationship:

o At collector node of Q1, i.e. at point X: I REF I C 2 2 I B 2

o Therefore, output current is

IO IC2

I REF

1 2

(1.2)

Output resistance, ro:

o When Early effect is taken into account,

VA and ro is finite.

o Stability of IO is affected by the bias

conditions in the load circuit. (Remember,

want IO = IREF for biasing)

dI O

I

1

O

dVCE 2 V A ro 2

dI

O

o A more general equation to calculate dIO: dVCE 2 RO

(1.3)

different for different types of current sources.

**Exercise 10.2, Ex. 10.2

Mismatched Transistors

In most IC fabrication of current sources, Q1 and Q2 will be directly adjacent

to each other. Hence, they can be very well matched.

However, if Q1 and Q2 are mismatched and >>1, base currents can be

neglected to give:

I REF I C1 I S1eVBE / VT and I O I C 2 I S 2 eVBE / VT

Therefore,

IO

I REF

IS2

I S1

(1.4)

reverse-saturation currents for Q1 and Q2 respectively

functions of cross-sectional area of the B-E junctions

Hence, (1.4) allows scaling of IO with respect to IREF by having transistors

of different sizes.

Lets look at current source circuits that have improved load current stability

against:

changes in

changes in output transistor collector voltage

i.

Source

Assume all transistors identical.

VBE1 = VBE2 = VBE

IB1 = IB2

IC1 = IC2

1 = 2 =

I E 3 1 3 I B 3 2 I B 2

Figure 6: Basic three-transistor

current source.

smaller

< .

I REF

(1.5)

VBE3

The

Usually assume

= reference current is given by:

V . Hence, the term

V 2V BEBE V

2VBE.

(1.6)

R1

Current relationship:

o Summing the currents at point X: I REF I C 2 I B 3

o Therefore, output current is

I REF

IO IC2

2

1 3

(1.7)

Advantage:

1. Better approximation of IO to IREF

2. IO less sensitive to variation in

o Looking into the collector of the output transistor Q2 in the threetransistor current source, ro is the same as in the two-transistor

current source:

1

dI O

dVCE 2

ro

VA

IO

(1.8)

If there exists any mismatch between Q1 and Q2, the bias current deviation

from the ideal is as given in eq. (1.4).

**Example 10.3, Ex. 10.3

1.

Cascode Current Source

Designed such that RO is greater than that of the two-transistor

circuit.

Assumption: all the transistors are matched. Hence, IO IREF.

K

L

L

Figure 7: (a) Bipolar cascode current mirror; (b) small-signal equivalent circuit

(Note: Voltage source Vx is connected to the output to enable calculation of output

resistance RO).

and L in Figure 7) are signal ground.

Figure 7(b) can be rearranged to give Figure 8.

V x Vbe 4

ro 4

I x g m 4Vbe 4

RO

Vx

ro 4 1 r 4 ro 4

Ix

(1.9)

the two-transistor current source.

Advantage: Increases current source stability with changes in output

voltage.

1.

Another configuration of a threetransistor current source.

Assume all transistors identical.

Y

IB1 = IB2

IC1 = IC2

Current levels in all three transistors are nearly the same, therefore

1 =2 =3 =

At point X:

I REF I C1 I B 3 I C 2 I B 3

current source.

(1.10)

2

I E 3 I C 2 2 I B 2 I C 2 1

(1.11)

IC2

I E3

1

I

1 2 2 C 3

(1.12)

1

I O I C 3 I REF

(1.13)

current source (given by eq. 1.7). The difference is in the higher output

resistance of Wilson current source.

The output resistance for the Wilson current source, looking into the

collector of Q3:

RO

ro 3

2

(1.14)

In all the previous current source circuits, the load current and reference

currents have been nearly equal.

10A is required, for V+ = 5V and V- = 5V, the resistance value needed is:

R1

V VBE V 5 0.7 5

930k

I REF

10

Resistors in the order of 1M require large area and are difficult to fabricate

accurately for IC application. Hence, the resistor values are limited to the

low kilohm range.

The Widlar current source, shown below, meets the above requirement.

Voltage difference across RE enables

VBE2 < VBE1

Hence, IO < IREF.

Q1 and Q2 are identical and >>1

for both transistors.

Hence, I REF I C1 I S eVBE1 / VT .

Thus,

I REF

IS

VBE1 VT ln

(1.15)

rearranges to give:

I

VBE 2 VT ln O

IS

(1.15)

IO

1

VBE1 VBE 2

RE

(1.16)

relationship of the Widlar current source is:

IO

I

1

VT ln REF

RE

IO

(1.17)

**Design Example 10.5, Ex. 10.5

The output resistance looking into the collector of Q2 is given by:

dI O

Ro

dVC 2

Figure 11(a).

The output resistance looking into the base of Q1 is given by

RO1 r 1

1

ro1 R1 r 2

g m1

RO1 is in series with r 2 , and since RO1 r 2 , the effect of RO1 can be

10

Figure 11: (a) Small-signal equivalent circuit for determining output resistance of

Widlar current source, (b) simplified equivalent circuit for determining output

resistance, and (c) equivalent circuit after a Norton transformation.

Figure 11(b) or 11(c) to give:

Vx

RO ro 2 1 RE r 2

Ix

Normally, 1 ro 2 g m , therefore

g m2

1

ro 2

(1.18)

RO ro 2 1 g m 2 RE'

(1.19)

where RE' RE r 2 .

Hence, the output resistance of the Widlar current source is a factor

1 g m2 RE' larger than that of the simple two-transistor current source.

Multitransistor Current Mirrors

The reference transistor VBE voltage can also be applied to multiple

transistors to generate multiple load currents as shown below.

11

The relationship between each load current and the reference current,

assuming all transistors are matched and VA = , is:

I O1 I O 2 I N

I REF

1 N

1

(1.20)

changing the load current versus current relationship. An example of such a

circuit is shown in Figure 13.

transistor current source

(assuming all transistors are

matched and is very large such

that the base currents can be

neglected, I1 = I2 = I3 = IREF ).

Equivalent circuit symbol

of three transistors in

parallel

mirror.

currents (IOs) from a

single reference current

IREF.

pnp transistors to source

currents

npn transistors to sink

currents

12

= 3IREF

Effect of finite - IO to be less than IREF since IREF supplies all base

currents. It becomes more severe as more transistors are added.

Output Voltage Swing

The minimum output voltage, VO (min), of the current mirror influences

the maximum symmetrical output voltage, VOUT , swing of the load

circuit being biased.

VOUT

VO

The minimum output voltage for the two-transistor current source (see

Figure 5):

VO (min) VC 2 V VCE 2 (sat)

(1.21)

where VCE 2 (sat) may be in the order of 0.1 to 0.3 V

For the cascode and Wilson current sources (see Figures 7(a) and

respectively):

VO (min) V VBE VCE (sat)

(1.22)

13

In this case, VBE VCE (sat) may be in the order of 0.7 to 0.9 V.

Therefore, VO (min) in the cascode and Wilson current sources are higher

compared to the two-transistor circuit.

Note: Increase in VO (min) means reduced maximum output voltage

swing of the load circuit, which is critical in low-power applications.

14

Load current,

IO

Twotransistor

Threetransistor

(Figure 5)

(Figure 6)

I REF

I REF

1 2

2

1

1 3

Cascode

Wilson

Widlar

(Figure 7a)

(Figure 9)

(Figure 10)

I REF

I REF

2

1

1 4

I

1

VT ln REF

RE

IO

Multiple

transistor

ro 3

Output

ro 2 1 g m 2 RE r 2

ro 4

ro2

ro2

resistance, RO

2

Finite

2 2

2 2

4

2

error*

*Finite error = discrepancy between IO and IREF since the reference current supplies all base currents.

(Figure 12)

I REF

1 N

1

ro

N

o Sum currents at the various nodes in the circuit to find the relation between the reference current and the bias

current.

o To find the output resistance, place a test voltage at the output node and analyse the small-signal equivalent

circuit. Keep in mind that the reference current is constant, which may make some of the base voltage

constant or at signal ground.

15

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