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ABSTRACT
The Performance of a memory device plays a vital role in a computing system. The Processor
architecture decides the performance of system. Also the memory device has contribution to the
systems performance. Some aspects related to memory viz. hit, miss, latency, etc. are the key terms
which has impact to the systems performance. Now a day, the advanced processor architecture
revolution has become crucial and is ceasing in the improvement of faster fetching, decoding and
execution. The New concept of three dimensionally integrated memories tends to give a better
performance than the two dimensionally integrated memory. The Approach of 3DI is to stack the
multiple dies of a memory which gives shorter interconnections; low resistance and low power
consumption, faster passage of control signals and reduction of a die area as compared to the
previous integration technology at the cause of increasing the cost and system complexity. Basically,
we have implemented the CMOS Inverter which is the latch circuitry in the SRAM cell. We have
simulated a 3D integrated CMOS Inverter in 40nm process technology.
Keywords: 3DI, CMOS, Memory etc.
I. INTRODUCTION
Three dimensional integration of a circuit or a complete system brings a new approach in the
VLSI stream. The SiP type of 3DI is simple, inexpensive and straight forward. The Other type i.e.
Through Silicon Vias (TSV) based 3D integration give more benefits. Some of them are short
connection, reduced RC delays, small area etc[2]. 3DI using the TSV is a promising approach to
coping with the challenges faced by the current 2D technology. A TSV-based 3D IC is implemented
by stacking multiple dies which are vertically connected by TSVs. This may shorten the global
interconnects of a 3D IC and greatly improve its performance and power consumption. High
bandwidth is achieved by the increase of IO channels provided by the TSVs, which also reduces the
unnecessary waste of energy during data movement.
1
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 6472(Online), Volume 5, Issue 11,
1 November (2014), pp. 011-05 IAEME
Fig.3: 3D Inverter
Fig.1. explains you the parameters to be defined in the process file for 3D model i.e.
thicknesses of STI, ILD and M1 and also the z-coordinates
z
of specific layers (z0, zSTI, Zbottom etc.)
respectively whereas Fig.2. Explain the layout design of Inverter.
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 6472(Online), Volume 5, Issue 11,
1 November (2014), pp. 011-05 IAEME
class CMOS004Params()
[ ('lmd', 0.02),
('Tsub',2),
('TBOX',0.03),
(TSTI,0.01),
('Tox',3e-3'),
('Tpoly',0.20),
('TTiSi2',0.02),
('TM0',0.2),
('TILD',1),
# sub doping
('Nsub', 2e17')
# S/D extention doping
('Nsde_n', 2.06338e2'),
('Nsde_p',
2.87375e19')]
Table 1
self.z0 = 0.0
self.zbottom = self.z0 - Tsub
self.zBOX = self.z0 - TSTI - TBOX
self.zSTI = self.z0 - TSTI
self.zpoly = self.z0 + Tpoly
self.zTiSi2n = self.z0 + TTiSi2
self.zTiSi2p = self.zGe + TTiSi2
self.zpolyTiSi2 = self.zpoly + TTiSi2
self.zM0t = self.zpoly + TTiSi2 +TM0
self.zM1b = self.z0 + TILD
self.zM1t = self.zM1b + TM1
self.zM2b = self.zM1t + TIMD2
self.zM2t = self.zM2b + TM2
self.zmax = self.zM2b + TPass
ss
self.Tpad = 0.1*TILD
Table 1 (a) and (b) give the details about the definition of the process parameters and the
process of making a 3D structure respectively.
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 6472(Online), Volume 5, Issue 11, November (2014), pp. 01-05 IAEME
International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976
6464(Print), ISSN 0976 6472(Online), Volume 5, Issue 11, November (2014), pp. 01-05 IAEME
Values
Lambda
20nm
Gate length
40nm
Supply Voltage
0.1 volts
Threshold Voltage
0.035 volts
Chip Area
0.342um
0.21nsec
Static power
9nWatts
Dynamic power
0.25f Watts~0.5nWatts
IV. CONCLUSION
Thus, this new concept of 3DI brings a new turn in the vlsi systems optimizing the above
parameters as compared to previous integrations from 2D to 2.9D.
ACKNOWLEDGEMENT
The Authors would like to thank Dr. Surendra Rathode from SPIT for the lab provision for
the Genius simulator, Mr. Amit Saini from Cadre Design Systems for his valuable support to this
work and Mr. Ajay Koli, Fr CRCE for his technical support.
REFERENCES
[1] Koyanagi et al, Future System-on-Silicon LSI Chips, IEEE Micro, July/August 1998.
[2] S. Borkar, et al, 3D Integration for Energy Efficient System Design, DAC June 2011.
[3] Yangdong Deng and W.P. Maly. 2.5-dimensional vlsi system integration. Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on, 13(6):668677, June 2005.
[4] S. Tarzia, A Survey of 3D Circuit Integration, March 14, 2008.
[5] G. T. Goele et al., Vertical Single Gate CMOS Inverters on Laser-Processed Multilayer
Substrates, Proceedings of the IEEE International Electron Device Meetings, Vol. 27,
pp. 554-556, December 1981.
[6] P. Vasilis, Interconnect-Based Design Methodologies for Three-Dimensional Integrated
Circuits, PhD report at University of Rochester, New York, 2008.
[7] Rajinder Tiwari and R K Singh, An Optimized High Speed Dual Mode CMOS Differential
Amplifier for Analog VLSI applications, International Journal of Electrical Engineering &
Technology (IJEET), Volume 3, Issue 1, 2012, pp. 180 - 187, ISSN Print: 0976-6545,
ISSN Online: 0976-6553.
[8] P.Sreenivasulu, Krishnna veni, Dr. K.Srinivasa Rao and Dr.A.VinayaBabu, Low Power
Design Techniques of CMOS Digital Circuits, International Journal of Electronics and
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