International Journal of Semiconductor

Science & Technology (IJSST)

ISSN(P): 2250-1576; ISSN(E): 2278-9405
Vol. 4, Issue 1, Oct 2014, 1-4
TJPRC Pvt. Ltd.

FOREIGN MATTER REDUCTION IN HIGH DENSITY PLASMA

CHEMICAL VAPOR DEPOSITION PROCESS
VIVEK KRISHNAMOORTHY
Ellora, Chhedanagar, Mumbai, Maharashtra, India

ABSTRACT
This paper describes the aspects of foreign matter reduction in the High Density Plasma chemical vapor
deposition (HDP-CVD) process. Methodologies to reduce foreign matter were verified experimentally. Based on the
results obtained a correlation between process parameters and foreign matter was obtained. The analysis of such data led to
accuracy in determination the causes of foreign matter in a HDP-CVD process. The yield and productivity of equipments
were increased by employing methods to reduce foreign matter contamination. A correlation was also drawn between
particle counts and causes of foreign matter. Experiments were carried out for numerous tool sets. All the activities were
carried out in a real time semiconductor fab.

KEYWORDS: Foreign Matter, HDP CVD, Semiconductor

INTRODUCTION
In Semiconductor industry frequent analysis of wafers is carried out to measure foreign matter contamination.
Foreign matter contamination can arise due to different reasons. Foreign matter tests are carried out which determine
nature of particles as well as number of particles. Size of particles can also be determined from foreign matter tests.
The equipments which detect such foreign matter are easily available and deployable in a semiconductor fab or
environment. Due to shrink in dimensions, sophisticated equipments are available for the size range of particles to be
evaluated. A few causes of foreign matter contamination to start of with are unclean gas feed, unclean wafers used to
measure foreign matter, improper handling of wafers and improper handling of wafer caskets. GMP practices should be
strictly followed while working in semiconductor fabs and environment. For example poor indoor air quality could lead to
widespread contamination in semiconductor fabs and environment.

DISCUSSIONS
A tool or equipment in a semiconductor fab runs many processes designed by engineers. While the tool or
equipment runs many recipes designed by the engineer it does different work each time but the tool set yet is not confused
by the variety of the processes being run. After running multiple recipes and ending a cycle, a tool may undergo changes in
which some of them are deposition of material on chamber walls, changes in the electrostatic chuck parameters, changes in
flow rates of gases and inerting agents and power and plasma conditions. These changes were prevalent for every tool set
that operates in the semiconductor fabs and environment. When equipment process parameters defined deviate from the set
parameters, a deviation from the observed result may cause a rise in foreign matter contamination. In a High Density
Plasma Chemical Vapor Deposition (HDP-CVD) process, an equipment or tool had material deposited on the chamber
walls before the designated semiconductor process commences. An equipment or tool undergoes frequent temperature

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Vivek Krishnamoorthy

cycles. The outcome of this resulted in flaking of chamber walls contributing to foreign matter contamination. Frequent
change in electrostatic chuck parameters resulted in contribution to foreign matter contamination due to inconsistent
conditions of the wafer placed on the electrostatic chuck. Rust/ dust in the cylinders supplying gases for deposition or
etching or inerting could have contributed to foreign matter contamination. Another source of contamination could have
been variable changes in plasma conditions like plasma temperature and ionizing power. Variable ionizing power altered
the mechanisms in a tool set and could lead to foreign matter. Major contribution to foreign matter contamination could
have been determined by the size of the particles or foreign matter and their counts. A systematic analysis prevented the
cause of such foreign matter. There was an increase in foreign matter because of continuous runs or when cleaning is not
performed frequently. The size range of the foreign matter was obtained through particle measuring systems. A blanket
wafer was used for foreign matter (spot) determination before the start of the process recipe. It was used for spot
determination before the tool ran the cleaning recipe. It was also used after the tool ran the cleaning recipe but before the
process recipe. This would give an indication how the tool performed in the last run and indicated if there were any major
problems in the tool. When the tool failed spot determination limits, it gave an indication how the tool performed in the
run. Spot determination failure by a large number and size indicated that either cleaning of the tool was not performed or a
major process parameter in the recipe was changed. Many experiments were performed in the semiconductor fab with
respect to foreign matter contamination without disturbing the manufacturing output. Nozzles which let in the gases for
deposition or etching were thoroughly cleaned of any deposits. Orientation of these nozzles was an important factor in
accurate deposition or etching. When the wafer in the tool set was subject to different temperature conditions in the
HDP-CVD process, spot determination varied. Thus accurate temperature control of the substrate is of great importance in
the HDP-CVD process. EDX was performed to detect the constituents or elemental nature of foreign matter deposited on
substrates. This helped in deciding which part of the process failed when the recipe was run in the tool. For example higher
amount of Aluminium indicated that etching of the chamber wall had taken place. Higher amount of oxygen indicated that
the insulator SiO2 was significant in the process run. A spot determination test after each of the recipe run indicated
whether the process parameters and the condition of the tool set were right. Some tools failed spot determination tests after
a few continuous runs while other tools failed after many continuous runs. These results did not indicate the nature of
failure neither did they improve the performance of the tools. In such conditions yield of the equipment was drastically
reduced. By conducting regular spot determination tests productivity of the tool sets were increased. The precoat layer
duration or precoat layer deposition rate was modified to prevent flaking of layers from chamber walls. These many
changes, tests and methodology when put in place helped reduce foreign matter contamination in the HDP-CVD process.

CONCLUSIONS
Foreign matter in HDP CVD process can be reduced by the methodologies employed. While the most prevalent
conditions have been taken care of, methodologies of reducing foreign matter may differ say for example in the reactive
ion etching process. Process parameters and other conditions mentioned were based on real time manufacturing conditions
in a semiconductor fabrication unit. Experiments carried out based on the above description resulted in a decrease in
foreign matter for HDP-CVD conditions.

REFERENCES
1.

Luoh, T, Ta, Su. -C. (2008) HDP-CVD process, filling-in process utilizing HDP-CVD, and HDP-CVD system.
US patent 8034691 B2

Impact Factor (JCC): 3.8869

Index Copernicus Value (ICV): 3.0

Foreign Matter Reduction in High Density Plasma Chemical Vapor Deposition Process

2.

Cheng, L, Y. (2003) Method for improved cleaning in HDP-CVD process with reduced NF3 usage. US patent
6584987 B1

3.

Huang, L. (2005) Two-step, low argon, HDP CVD oxide deposition process. US 6211040 B1

4.

Li, D. (2005) HDP-CVD dep/etch/dep process for improved deposition into high aspect ratio features. US
6908862 B2

5.

Ziaul, M. (2007) HDP-CVD multistep gap fill process. US 7205240 B2

6.

Cleemput, P. (2002) High density plasma (hdp) chemical vapor deposition (cvd); gas mixture of
silicon-containing and oxygen-containing components and replacing argon with helium so the sidewall sputtering
and redeposition effect is greatly reduced.US 6395150 B1

7.

Nguyen, S. (1999) High-density plasma chemical vapor deposition of silicon-based dielectric films for integrated
circuits. IBM Journal of research and development, 43 (1-2), 109-126

8.

Li, D. (2003) Hydrogen assisted undoped silicon oxide deposition process for HDP-CVD. US 6596653 B2

9.

Wang, R. (2009) Low-frequency bias power in HDP-CVD processes. US 7571698 B2

10. Redeker, F. (2001) Symmetric tunable inductively coupled HDP-CVD reactor. US 6170428 B1

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