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# Analog CMOS

Integrated Circuit
Zou Zhige
Spring, 2010

Chapter 5
Passive and Active
Current Mirrors
Zou Zhige
Spring, 2010

DD

Calculate the

## Output voltage swing

(Vx, Vy, Vout=Vx-Vy)
low frequency Av

out

AV = g m ( ron // rop )

in

2
SS

## Vin ,com Vthn < Vx , y < VDD Vod ,mp

Vin ,com = VGS 1 + VP
Vod ,mn < VP
Zou Zhige

VLSI, EST

Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors

Introduction
Large-signal analyses
Small-signal analyses
Common response

Zou Zhige

VLSI, EST

Introduction
We have learned current source:
Current source can act as a large resistor without consuming excessive
MOS in saturation can act as current source.
All the amplifier need current source or resistor for load current.

## Current source has many applications:

current source load for common source amplifiers
tail current source for differential pairs
bias currents for folded cascode amplifier
DAC
Current count and so on.
This Chapter we will learn current mirror for bias elements and signal
processing components.

Zou Zhige

VLSI, EST

Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors

Introduction
Large-signal analyses
Small-signal analyses
Common response

Zou Zhige

VLSI, EST

Zou Zhige

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## Basic Current Mirrors

The simplest current source is as follows:

1
W
I out = nCox (VGS VT )2 ,
2
L

VGS

R2
=
VDD
R1 + R2

## Is this current source

always constant ?

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## The problem of Basic CM

Influence of: power supply, process, temperature
Vgs and Vth are not constant.

Why?

## Even if the Vgs is precisely defined, the Id is not constant.

, Vth will change due to different process or temperature
We must seek other method of biasing MOS current
sources.
Current copy from a constant current reference!
But how to
copy?
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Copying Current

Current
Mirror

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## Both in saturation and Neglecting the Lambda, We get:

Iout

W W
= ( )2 /( )1 Iref
L
L

## It allows precise copying of the current with no dependence on process

and temperature !
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DD

current source

REF
out2

out1

current sink

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## All the MOS should have the same channel length!

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Another Example
Av=?
(W / L) 3
AV = g m1 RL
(W / L) 2
Current Transfer!

1
AV = g m1 (ro1 ||
|| ro 2 ) g m 3 (ro 3 || RL )
gm2
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Introduction
Basic Current Mirrors
Cascode Current Mirrors
Active Current Mirrors

Introduction
Large-signal analyses
Small-signal analyses
Common response

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Drawback of Basic CM
Consider the channel length modulation effect:
I OUT =

1
W
u n C ox (VGS VTH ) 2 (1 + V DS )
2
L

I D 2 (W / L)2 (1 + VDS 2 )
=
I D1 (W / L)1 (1 + VDS1 )

## Because the load is not constant, so:

VDS1 VDS 2
We should reduce the channel length modulation. Or there is
other method?
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## Simple cascode amplifier

Large signal behavior (Vin fixed to VG1, Vout (VDS) sweeping from 0 to 3V)

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## Cascode Current Mirror

V X = VY ,then

Choose Vb , let

I out I REF

Output resistance:

Rout p = gm3ro3ro2
R Y = ro 2
ro 2
1
Vy =
V p =
V p
g m3 ro 3 ro 2
g m 3ro 3

How to get Vb ?
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To ensure:

V X = VY
We should have :

Vb = VGS 3 + V X

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## Cascode Current Mirror

Choose proper dimension of M0 and M3 for VGS3=VGS0
If

W
W
W W
( )o /( )3 = ( )1 /( )2
L
L
L
L

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Then:

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V X = VY

21

Region of M2 and M3

## M2 in sat, and M3 in triode

M2 and M3 both are in triode

## When Vout if M2 triode first, but Vgs2 constant

so Vds2 and Id2,3
Vb constant, Vgs3 its impossible for M3 still in saturation.
Conclusion: M3 enter triode zone first, then M2
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## V p min = VGS 3 Vod 2 VTH 3

= Vod 1 + Vod 3
= 2Vod
Notice:
So:
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V X VY
I out I REF
24

V p min = Vod 3 + VGS 2
= Vod 3 + VGS 2 VTH 2 + VTH 2
= 2Vod + VTH
To ensure:
So:

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V X = VY

I out I REF
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## Low voltage Cascode CM

In Sub-micro process, the ro is
very small. Cascode is useful.
In sub-micro process, the voltage
supply is very low.
So, we should reduce the voltage

DD

out
2

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## Low voltage Cascode CM

M1 in satu

V A = Vb VGS 2 VGS1 VT H 1
V X = VGS1

DD

## Vb = VGS 2 + VA VGS 2 + VX VTH 1

M2 in satu

Vx Vb VTH 2

Range of Vb

V x + VTH

out
2

Vb VGS 2 + V x VTH 1

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## Vb of Low voltage Cascode CM

M1 at the edge of satu:
DD

## Vb = VGS 2 + (VGS1 VTH 1 )

Vout reaches the lowest level (headroom)

out
2

1

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## How to generate Vb?

Vb = VGS 2 + (VGS 1 VTH 1 )
The left figure:

I*R=VTH1
VGS2=VGS5
The right figure:
We need big (W/L)7 for VGS7=VTH1
VGS2=VGS5

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## General Advantages of MOS Current Sources

Effective current gain
( Unlike the BJT multi-stage current mirrors)

## Current ratio MOS channel geometric ratio

Iout can be as small as several nA
The ratio is not constant any more

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Design Considerations
Work with integer ratios and unit devices as much as possible.
Using a unit device of size 1
Keep mirror ratio (IOUT/IREF) reasonably small
Typically no larger than 1020

## Typically, we'll only have one single reference current

generator on a chip
Can generate/distribute currents across chip in two different
ways
Distribute gate voltage
Can cause big problems due to IR drop
Usually limited to local distribution

Distribute currents

Have one global bias cell close to reference that sends currents into local
biasing sub-circuits
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Class Exercise
Ignore the output
voltage of IREF
All W/L, except M4:
W/4L
Iout And the min Vp
and VDD

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DD

REF

A
4

2
3

out
6

B
2

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Thanks!