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1100 Sequence Detector

I have to design a 1100 sequence detector using Mealy model and JK Flip-Flops. Here is the state diagram:

And based on this diagram, I obtain following input statements for flip-flop inputs (A and B flip-flops):
JA = A and X
KA = B
--------------JB = A xor X
KB = A nand X

Finally, VHDL implementation gives these result:

But it catches "110" instead of "1100". When I implement same state diagram using case...when structure, it gives correct result but
I have to use logic gates & JK flip-flops.
How should I change this design? Is there something wrong or something I missed?
EDIT: I need obtain functions JA, KA, JB, KB (which are inputs of JK flip-flops) in terms of present states A,B and input sequence X.



vhdl - 1100 Sequence Detector - Electrical Engineering Stack Exchange


edited Dec 1 4 '1 3 at 1 4 :52

asked Dec 1 4 '1 3 at 1 3 :2 8

1 03

X denotes sequence input, A is output of first JK, and B is for second one.

oozel Dec 1 4 '1 3 at 1 3 :3 2

1 Answer
Going through the tables and K-Maps, I came up with a completely different result than what
you got. Here are my tables and K-Maps.

Y our equations also seem much too simple. Can you post a picture of your K-Maps?
Okay, looks like everything you posted is correct. I didn't know this until I read around today,
but it looks like Mealy machines have this interesting situation with their output.
From a page of University of Pennsylvania's Electrical Engineering:



vhdl - 1100 Sequence Detector - Electrical Engineering Stack Exchange

So the output is correct. I built the circuit according to my equations and confirmed it does
work this way. The output goes high on 110, and then back low again on the 2nd 0, so the
output is a pulse. That makes sense, because Mealy machines don't have constant outputs
while residing in states like Moore Machines do, only in between the states. Unfortunately my
laptop died so I can't link you the circuit.
This is also consistent with your output waveform, as your output goes low again after the 2nd
0 in 1100.
Now you might be wondering that if you input the sequence 1101, then the output still goes
high for a brief moment. That's true, and they cover that situation in the U-penn website as
well, in the 2nd picture where they talk about the "glitch" in the output.
From their page:
One notices that there is a glitch in the output after the input sequence 10111010. However
this occurs at a moment that the output is not valid (the output is valid just before the positive
clock edge). The valid output sequence is than 000100000 as expected.
Remember their sequence detects 1011, so the last 4 bits of their input sequence, 1010, is the
same glitch situation as if 1101 was input to yours. Looks like nothing is wrong.
edited Dec 1 4 '1 3 at 1 6 :4 4

answered Dec 1 4 '1 3 at 1 4 :2 6

krb6 86
7 48

I'v e added state assignm ent/truth table.


oozel Dec 1 4 '1 3 at 1 4 :54

Thanks for y our help! And the key word is: "Sy nchronous Mealy Machine". The result that we desire is sim ply
obtained when current output pass through an additional D-FlipFlop (or a JK that is conv erted to D, for this
exam ple). Details are here. oozel Dec 1 5 '1 3 at 8:59