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[Art. 4.14]

Thvristors

In the range of power freguencies,

voltage is given by

it may be empirically shown [3] that

r99

RC for zero output

ncr_ff=l

...(4.25)

T =Lf =period of ac line frequency in seconds.

where

The SCR will trigger when u" =Vrr+ u4, where ua is the voltage drop across diode Dl. At the
instant of triggering, lf u" is assumed constant, the current.Ir, must be supplied by voltage
source through R, Dl and gate to cathode circuit. Hence the maximum value of R is given by

...(4.26)

where u" is the source voltage at which thyristor turns on. Approximate values of lR and C
can be obtained from Eqs. (4.25) and (4.26).
us

-lt 12 0

V6 sin rrrt

_+!
|/"

*'a
I

Fq
I

I
I

2r
I

ift

(a)

(b)

Fig. 4.67. Waveforms for RC half-wave trigger circuit of

Fig. 4.66 (o) high value of E (b) low value of R.

When SCR triggers, voltage drop acro.ss it falls to 1 to 1.5 V. This, in turn, lowers the voltage
across.R and C to this low value of 1 to 1.5 V. Low voltage across SCR during conduction period
keeps C discharged in positive half cycle until negative voltage cycle across C appears. This
charges C to maximum negative voltage -V^as shown in Fig. 4.67 by dotted line. In Fig.4.67
(a), F is more, the time taken for C to charge from - oa to (Vs1+ u) V", is more, frring angle is
=
more and therefore average output voltage is low. In Fig. 4.67 (b), R is less, frring angle is low
and therefore average output voltage is more.
(ii) RC fult-wave trigger circuit. A simple RC trigger circuit giving full-wave output voltage
is shown in Fig, 4.68. Diodes D1-D4 form a full-wave diode bridge. In this circuit, the initial

206

Power

[Art. 4.14]

Flectrorb

Rr
ir.f

,^
,l:
..,

DI

R2

f--

vc ..= L.

Pulse

\ ''i t;-

D4

Tt

t:

Fig. 4.73. Synchronised UJT trigger circuit.

on. As soon as the capacitor discharges, it starts to recharge as shown. Rate ofrise ofcapacitor
voltage can be controlled by varying ,R. The frring angle can be controlled up to about 150". This
method of controlling the output power by varying charging resistor.R is called ramp control,
qpm'Joop control or manual control.

As the zener diode voltage V" goes to zero at the end of each half cycle, the synchronization
of the trigger circuit with the supply voltage across SCRs is achieved. Thus the time f, equal to
crlo, when the pulse is applied to SCR for the frrst time, will remain constant for t\e same value
of R. Small variations in the supply voltage and frequency are not going to effect the circuit

operation.
v.

v.
Vo.

...Y d,

Vd.

vd.

Pulse
voltog8
q

(a)

-lfit

J,fL
(b)

Fig. 4.74. Generation of output pulses for the circuit of Fig. 4.73. Here, t = a/a.

In case R is reduced so that u" reaches UJT threshold voltage twice in each half cycle as
shown in Fig. 4.74 (b\, then there will be two pulses in each half cycle. As the first pulse will be
able to turn-on the SCR, second pulse in each cycle is redundant.
Ramp-and'pedestal triggering. Ramp and pedestal triggering is an improved version of
synchronized-UJT-oscillator triggering. Fig. 4.75 shows the circuit for ramp-and-pedestal
triggering oftwo SCRs connected in antiparallel for controlling power in an ac load. This trigger
circuit can also be used for triggering the thyristors in a single-phase semicohverter or a
single-phase full converter. The various voltage waveforms are shown in Fig. 4.26.
Zener diode voltage V, is constant at its thresh-hold voltage. R, acts as a potential divider.
Wiper of .R2 controls the value of pedestal voltage Voa. Diode D allows C to be quickly chdrged
to Voa through the low resistance of the upper portion of Rr. The setting of wiper on R, is such