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Lecture 9:

ESD
Oh, Kwang-Hoon, Ph. D.
okhoon@fairchildsemi.com

Purpose

To provide an understanding of the ESD phenomena associated with


device failures

To understand implications of the impacts on device and circuit


reliability

To present an insight into the future reliability issues for ESD

Outline

1.

Introduction - What is ESD? Why is it important?

2.

EOS/ESD Failure and Their Impact

3.

ESD Stress Models

4.

ESD related Failure Modes

5.

Protection Scheme

6.

Measurement of ESD

7.

Issues in ESD
7-1. Advanced Issues

8.

Methods for ESD Design Verification

9.

Protecting IGBTs and MOSFETs

Introduction
z

What is ESD?

ESD is the discharge of static electricity. Static electricity is an excess or deficiency of electrons
on one surface with respect to another surface or to ground. A surface exhibiting an excess of
electrons is negatively charged, and an electron deficient surface is positively charged. Static
electricity is measured in terms of voltage (volts) and charge (coulombs).
When a static charge is present on an object, the molecules are electrically imbalanced.
Electrostatic-Discharge (ESD) takes place. When an ESD-sensitive device, such as a power
MOSFET, becomes part of the discharge path, or is brought within the bounds of an electrostatic
field, it can be permanently damaged.
The transfer of electrostatic charge between bodies or surfaces at different electrostatic
potential. ESD is a subset of EOS.

EOS General
ESD
High voltage (1V-15kV)
Short duration
Very low power
Fast rise time (1-10ns)

EOS Specific
Low voltage (16V)
Longer duration (1-10ms)
Low power

Lightning
Extremely high voltage
Extremely high power

Electrical Overstress (EOS):


The exposure of an object to a current or voltage beyond its maximum ratings.
Electro Static Discharge (ESD):
mild shock to human but lethal to microelectronic components

Common cause of ESD: triboelectric1 charging

Triboelectric series after 2


Positive (+)

Positive (+)

zero

Negative (-)

Si
1

Negative (-)

Human skin
Rabbit fur
Glass
Mica
Human Hair
Nylon
Wool
Fur
Lead
Silk
Aluminum
Paper
COTTON
Steel
Wood
Amber
Sealing Wax
Nickel, copper Brass, silver
Gold, platinum
Sulfur
Acetate rayon
Polyester
Celluloid
Silicon
Teflon
2 ESD

Electrostatic generation arising from friction between two materials


6

Association

Table of Typical Generated Electrostatic Voltages*


Examples of Static Generation Typical Voltage Levels
Means of Generation

10-25% RH

65-90% RH

Walking across carpet

35,000V

1,500V

Walking across vinyl tile

12,000V

250V

Worker at bench

6,000V

100V

Poly bag picked up from bench

20,000V

1,200V

Chair with urethane foam

18,000V

1,500V
*ESD

Association

Reliability for IC Technologies


Electrostatic Discharge
- High current (1.6 Amps) for 1-100 ns
- Human and machine handling damage
- Immediate and visible, as well as latent, failures
- Destructive IC chip design function
- Can be overcome with protection clamps
Electrical Overstress
- Voltage overshoot resulting in high currents for 1 us - 1 ms
- Over voltage during applications
- Very destructive and cannot be recovered
Can be reduced with proper ESD/Latchup design
Latch up
- Interaction between PMOS and NMOS devices
- High power supply current until power disconnected
- Destructive damage to the IC chip
- Can be prevented with design and process
Has a more direct trade-off with ESD
8

Electromigration
- Result of metal transport under high current density through metal leads
- Can lead to malfunction of the chip
- Can be overcome with good design rules and understanding of the metal
process
Can degrade with latent effects from ESD
Hot Carriers
- Degradation of transistors during long-term operation (5-10 years)
- Understanding of the phenomena during technology development is important
- Circuit simulations can be used to predict failures
Direct trade-off with ESD in most cases
Oxide
- Wearout mechanism over long time period
- Can be reduced with technology development
- Defect reduction during process
Vulnerable to ESD damage or latent effects

EOS/ESD Failure and Their Impact


It is estimated that 30~50%3-4 of all component failures are due to Electrostatic
Discharge (ESD) and Electrical Overstress (EOS).
EOS/ESD has been a predominant failure mechanism across all products in many
companies. Pervasive quality and reliability concerns for semiconductor device
technologies
Fabrication
26%

ESD/EOS
38%

Assembly
14%
Unknown
15%

M obile Ion
3%

Good
4%

Typical failure modes in Silicon ICs after 5:

Constantly changing device technologies make the design of proper protection very
challenging.
3. Electrical Overstress
4. T. Green, EOS/ESD Symp. 1988
5. R. Merrill et al., EOS/ESD Symp. 1993
10

Evolution of ESD Protection Circuits


FOD - Field Oxide
Device

8000
Thin Epi Effect

ESD HBM (V)

7000

SCR

6000

STI Effect

NMOS

GCNMOS with
Sub. Trig.

LDD Effect

5000

Re-optimized
SCR

FOD

4000
Silicide
Effect

3000

Silicide + thin
Epi Effect

2000
1000

Abrupt
Junctions

0
1980

Salicides

1990
Year

1995

FOD
SCR
GCNMOS
PTNMOS
NTNMOS
PLTSCR
PTNMOS - PNP
Driven Sub. Trig.

LDD Junctions

1985

GCNMOS - Gate
Coupled Device

2000

NTNMOS - MOS
Driven Sub. Trig.
PLTSCR - Gate
Isolated SCR

ESD protection levels are technology dependent. As technology changes, new protection
devices are necessary to meet the same ESD levels as before:
11
design of ESD protection is NOT transferable
through technology nodes!

z Implications of ESD on IC industry


Major reliability threat in IC industry:
- Cause of approximately 1/3 of IC failures
- ESD protection is very challenging against rapidly changing technologies

Standard model is used to characterize ESD:


- Human Body Model (HBM)
- Machine Model (MM)
- Charged Device Model (CDM)

ESD control is indispensable throughout devices life:


- Eliminating static charges from the workplaces
- Proper handling from manufacturing, shipping and field handling
- On-chip protection (clamp input voltage and bypass ESD current)

12

ESD Stress Models


According to the source of ESD event

Discharge TO the device

Discharge FROM the device

HBM (Human Body Model)


MM (Machine Model)

CDM (Charged Device Model)

ESD Models Comparison


Model

HBM

MM

CDM

Test levels (V)

500, 1000, 2000,


5000V

100,150, 200V

250, 500, 750, 1000V

Pulse width

~ 150ns

~80ns

~1ns

Rise time

2 ~ 10ns

N/A

< 400ps

Typical Failure

Junction damage
Metal penetration
Metal melt
Contact spiking
Gate oxide damage
13

Gate oxide damage


Junction damage

HUMAN BODY MODEL (HBM)


A minimum protection level of 2 kV for HBM (1.3 Amps) is required
Typical HBM Current Waveform

1.5 k

100 pF

The human body model is an attempt to model the ESD event which occurs when
a charged person touches a device.
Finger Resistance

~ 1500 Ohms

Body Capacitance to Ground

~ 100 pF

Charging Potential

several kVolts

Peak current = 1.3 Amps for 2 kV stress; 150 ns time constant

HBM testers are generally well controlled but the test board capacitance can
influence the waveform shape
14

MACHINE MODEL (MM)


A minimum protection level of 100 V for MM (1.8 Amps) is required
Typical MM Current Waveform
0

200 pF

The machine model is aimed at simulating abrupt discharge events which are caused by
contact with equipment and empty sockets (functional test, burn-in, reliability testing, etc.)
The model was developed in Japan and is widely used there.
The model is very sensitive to parasitics and control of testers to comply with standards is
difficult.
The current levels are much higher and for 200 V stress level the peak current is 3.5 Amps.

15

CHARGED DEVICE MODEL (CDM)


A minimum protection for 7 Amps peak current during CDM is required
Typical CDM Current Waveform

7A
I
<0.5 ns

t
The charged device model (CDM) simulates the ESD event occurring when an electrostaticallly
charged device is abruptly discharged to a metallic ground.
The simulated event is most likely to occur in automated manufacturing lines which involve
inadequate grounding or shielding for the IC devices.
The rise time can be less than 500 ps with peak currents of 7-10 Amps.
The testers are very difficult to build and the CDM test method is still evolving.
Device damage can be oxide rupture due to IR drops in the metal and poly lines.
Sub-micron transistors can turn on fast enough to offer CDM protection.
16

ESD Waveforms Comparison


HBM vs CDM vs MM
(5000V)

(500V)

(500V)

Discharge Current, IESD (A)

14
CDM

11
8
5
2

HBM

-1
MM
-4
0

20

40

60

80

100

120

Time, t (ns)
Courtesy of
Horst Gieser
17

ESD REQUIREMENTS (U.S.A.)


1. Human Body Model
+/- 2 kV Required by most customers
Waivers given at 1 KV in some cases
+/- 4 kV Delco (Auto Manufacturer)
+/- 8 kV On Special Automotive Pins (Power Outputs)

2. Machine Model
No Standard for reliable testing
Waivers given to 100 V in some cases

3. Charged Device Model


No clear standard
+/- 1000 V Some customers who require this
+/- 500 V level was generally found to be reliable

18

ESD Related Failure Modes


Catastrophic

Failure: device permanently damaged

- Current Induced
thin film fuse
junction filamentation
junction spiking

- Voltage Induced
charge injection
oxide rupture

Latent Damage: premature failure or malfunction


- significant increase in leakage current after test linked to ESD failure

19

- Current induced: temperature rise by Joule heating under ESD


Permanent failure

Degraded I-V characteristics


Abnormal increase in leakage current

Extreme case of filamentation


Melted metal flow into junction

20

- Voltage induced:
Charge state of dielectric changes
Trapped charge reversible (unbiased bake or
high energy UV irradiation)
Differ from filamentation (irreversible)

With increased amounts of charge, dielectric


ruptures
Resistive current path formed

21

Typical ESD Damage


Junction breakdown

Oxide breakdown

Metal/via damage

Transistor drain to source


melt filament (high leakage
level) under HBM

Transistor gate oxide


damage typical for CDM with
low leakage

Metal melts, leading to


opens under HBM (high
current pulse)

A. Amerasekera et al., ESD in Si


ICs, 1995

Chaine et al., EOS/ESD symp.


1995

K. Banerjee et al., IRPS 1996

22

Protection Schemes
The solutions for avoiding or reducing ESD failures
1) identifying and rectifying possible ESD sources
2) identifying and undertaking adequate prevention measures while
handling the ESD sensitive devices
3) incorporating built-in ESD protection networks in devices
4) providing awareness and training to users at all levels.

Two ways to reduce IC failures under ESD conditions:


reducing the likelihood of the ESD event occurring and improving the robustness of the device against
ESD.
The first approach focuses on reducing the amount of ESD induced charges and redistributing them
through proper handling of devices and controlling the handling environments.
The second approach is to implement on-chip protection circuits in order to improve the circuit
robustness against ESD events by improving ESD performance of the individual circuit components.

23

Typical on-chip protection circuits

Bi-directional I/O circuit

Primary ESD clamp: to protect the driver by limiting the I/O pad voltage below the
failure level of the output driver through bypassing most of the ESD stress current
to the power rail
Secondary ESD clamp: for auxiliary protection and the series resistors, Rs and Rin,
can lower the drain voltage of the output NMOS transistor and gate voltage of the input
receivers
Power ESD clamp network: absorb the ESD energy, protecting the devices in the I/O
circuits from ESD induced damage
24

ESD Protection Devices (I)


z What Should The Protection Device Protect?
CMOS Inputs:
- Gate Oxide Damage
- Gate to Vdd protection
- Input Diffusion to Nearby Diffusions
CMOS Outputs:
- Damage to Drain/substrate or Drain-Source
- Damage to the Drain Contacts
- Drain-Gate or Drain-Source Melt Filaments
Power Pins:
- Damage to Internal Circuits
- Increase in Post-ESD Idd Leakage

25

ESD Protection Devices (II)


zWHAT SHOULD THE PROTECTION DEVICE DO?
- Zero on-resistance; allows the device to shunt large amount of ESD current with no
ohmic voltage drop
- Finite clamping voltage; to avoid unintentional triggering of the protection device, the
sustaining voltage of the protection device has to be higher than the supply voltage (Vdd)
with a safety margin
- occupy minimum area at the bond pad and have minimum capacitance
- Instantaneous turn-on time (~ <1ns) and infinite energy absorption; before the IC chip
fails, protection device has to absorb full ESD induced energy as soon as ESD event
occurs
- Transparent to circuit operation (i.e., no parasitics); the protection device should
activate only under ESD conditions and cause no parasitic effects on the functioning
of IC chip
- survive the burn-in test
26

Resistor
- thin film resistor or diffused resistor

- to drop ESD induced voltage


(isolation in ESD networks)
- series resistance to ensure simultaneous
triggering of multifinger structures

Diode
- good power handling capability
- Multiple diode strings used for high Vdd
(But current handling capability degrades
due to the increase in on-resistance)

27

Silicon Controlled Rectifier (SCR)

- very high current handling capability


- but triggering voltage is relatively large (~ 20V in CMOS technology)

28

NMOS transistor
z

Lateral NPN triggering mechanism in self-biasing mode:

1.
2.
3.
4.
5.
6.

Avalanche multiplication by high VD across drain/substrate junction


Hole current gives Isub and Ib
Voltage drop (Isub*Rsub) across Rsub
Source/substrate junction forward biased: Isub*Rsub~0.7V (NPN turns)
Effective emitter area is defined by junction sidewall
J.E heating at the drain junction causes ESD failure

Bulk conduction occurs in self-biasing mode


(current handling capability increased: ~10 times !!)

29

z Snap-back Behavior of ggNMOS


z Electro-thermal Device Simulation using MEDICI:
Current flowlines under ESD

IESD

High current I-V curve for ggNMOS


8

Current[mA/m]

7
6

Tmax= 525 K

5
4
3
2

Tmax= 337 K

Tmax= 300 K

0
0

Voltage [V]

30

z PROTECTION CIRCUIT ELEMENTS


I(A)

BVox
Lateral NPN
Snapback
~ 2-5 Ohms

Lateral PNP
Snapback
~ 10-15 Ohms

2
Forward
Diode
~ 5 Ohms
PN Diode
Reverse
Biased ~ 50-75
Ohms

SCR latch
~1-2 Ohms

10

Any type of ESD clamp must protect the gate oxide with a breakdown of Bvox.
31

V(Volts)

Measurement of ESD
z Transmission Line Pulsing (TLP) Test:
Z0=50

Discharge
DUT

50

10 M

High voltage
- Automatic TLP setup -

td

Oscilloscope
Probe station
relay
Pulse generator

wafer
HP4156

I-probe

IESD
VD

PC

Measure I and V at each voltage pulse


32

z TLP test generates High current I-V curves of NMOS


A transmission line pulse (TLP) system can be used to characterize the It2 for
an NMOS transistor. This analysis would also give information on the Vt1 or the
drain avalanche of the NMOS.
before triggering

after triggering

It2

Vt1
Vh

VD

IESD

Vt2

Permanent device
failure

Current [mA/ m]

at failure

Vt2, It2

It2 is a technology monitor:


- VHBM 1.5k * It2 (@100ns)

Vh, Ih

Vt1 must be HIGHER than VDD


Vt2 must be LESS than oxide breakdown
voltage

Vt1, It1

0
0

Voltage[V]

10
33

z EMMI Analysis
Emission Microscopy (EMMI):Spatial distribution of ESD current under pulsed current stress

Silicided device
FA-1000

EMMI setup

detector

W=20m

-scope
HP 8114A Pulse
Generator
50

Vmax

509
VP

source
CT

gate
TDS
784A

Td=300ns

=30 mA
I =40
=10
=20

drain

substrate
DUT

Digital
Oscilloscope

Turned-on width Weff increases with


IESD :
Uniform conduction for narrow finger
devices

34

Issues in ESD
zProcess:
Process has a major impact on ESD performance and protection design.
LDD junctions improve CHC but have negative impact on ESD due to increased
power dissipation in the junction.
Silicided diffusions for improved circuit speed have drastic negative effect on ESD
due to reduced resistance and susceptibility to heat damage.
Low resistance substrates improve Latchup but degrade ESD with reduced It2.
Trade-off between ESD, CHC, and Latchup is important during process
development.

35

Cross-Section of an Advanced NMOS Transistor


Gate Oxide
Silicide

Drain

N+

Gate
Sidewall

N-

N-

Surface Implants

Pocket Implant

Source

N+

Lightly Doped Region

P-Well
P-Substrate/Epi Layer
- It2 can be influenced by several process features that are indicated here

36

Process Parameters That Affect It2:


- Drain/Source Implant Levels (LDDs are worse)
- P-well doping (low resistance substrates with epi are worse)
- Silicide (silicide on drain/source causes severe degradation in It2)
Transistor Parameters That Affect It2:
- Parasitic Bipolar Gain (Beta)
- Avalanche Multiplication Factor (M)
- Effective Substrate Resistance (Rsub)
Design Parameters That Affect It2:
- Channel Length (Bipolar Gain)
- Drain to Gate Contact Spacing (for non-silicided) to improve ballasting
- Gate Bias (can degrade It2 because of channel heating, especially in SOI)
- Substrate Bias (improves It2 - lower avalanche current to sustain npn)
- Finger Width (current crowding effects)

37

z NMOS ESD Design:


W

N+

Source

N+
L

SCG

DCG

J.E

Drain

P-Sub
The heating at the drain junction due to J.E determines the It2 of the NMOS
transistor for ESD performance. For non-slicided devices the drain contact to gate
spacing (DCG) provides the ballast resistance necessary for the finger to uniformly
turn on as parasitic npn.
DCG: 1-2 um to provide ballast resistance in non-silicided technologies and minimum with
silicided diffusions
SCG: Minimum(except for SOI with no silicide): NOT always
L: The channel length should be kept minimum for optimum ESD: NOT always
W: Finger length at 100 um for non-silicided and 30-40 um for silicided technologies
38

*Advanced Issues
z Non-uniform Bipolar Conduction
Severe reduction of ESD performance in advanced salicided technologies: localized current
distribution (Weff W)
Non-uniform current distribution under ESD can be seen by It2 [mA/m] with W: Strong width
dependence of It2

Non-silicided device

Silicided device
9

W=20um

W=80um

Current [mA/m]

Current [mA/m]

6
5
4
3

1/Ron

6
5
4
2
1

0
2

10

It2

1
0

W=20um
W=40um
W=80um

12

Drain Voltage[V]

Drain Voltage[V]

*RON: on-resistance in high current regime


*The results are observed from 0.13um CMOS technology
39

10

12

It2 roll-off (@Wmax) depends on process and device rating

1.5V NMOS

9
8
7
6
5
4
3
2
1
0

3.3V NMOS

non-silicided
silicided

non-silicided
silicided

It2 [mA/m]

It2 [mA/ m]

ESD robustness (It2*W) cannot be improved by merely increasing a finger width for very
advanced technologies

Wmax

6
5
4
3

Wmax

2
1
0

10

20 30

40

50

60 70

80

Finger Width [ m]

10 20 30 40

50 60

70 80

Finger Width [m]

z Strong degradation of ESD performance with salicidation due to


severe current localization

40

Wide Finger Devices: Turned-on width (Weff) also increases with IESD, but NOT fully turned-on
Turned on width (Weff):Process dependent, NOT finger width dependent

drain
W= 80m
source
I=20mA

I=60mA

I=20mA

partial failure

I=40mA

Non-silicided Device

gate

failure

Silicided Device

41

z Simulation of Non-uniform Conduction


Mixed-mode transient simulation considering variations:

IESD
S

M1

M2

Single finger NMOS

M1

M2
M1, M2
triggered

10
M1

M2

voltage [V]

Vd_M1
Vd_M2
Id_M1
Id_M2

0.005

Vt1

0.004
0.003

6
0.002

0.001

2
0
1.00E-12

1.00E-11

1.00E-10
time [sec]

42

1.00E-09

0
1.00E-08

current [A/ m]

12

z Simulation of Gate Bias Induced Heating


Current density modulated by Vgs within channel area
local temperature changes through J.E

Tmax=750K

Y
Vgs=0V

X
Y

1.2E+08
1.0E+08
2

J[A/cm ]

Vgs=0V (S/E)
Vgs=3V (S/E)
Vgs=0V (D/E)
Vgs=3V (D/E)

8.0E+07

Y
Vgs=3V

6.0E+07
4.0E+07
2.0E+07
0.0E+00
0.0001

0.001

0.01

0.1

log(Y) [ m]
43

Tmax=775K

zImplications for ESD Protection


Design Window for High Performance ESD Protection Devices

Vsub >> 0V
Compensate for
adverse Vgs effect

It2
Vgs
Heating
Uniform
IESD
Weff = W

Vgs
improved
uniformity

gcNMOS
ggNMOS

Non-uniform
IESD
Weff = Wmax
Wmax

44

Design Consideration
zFor the substrate trigger
protection, ggNMOS can be
used with Vsub
zFor gcNMOS without Vsub,
the gate should be designed
with R & C to maintain gate
bias below It2 roll-off

Methods for ESD Design Verification


1. ESD Design Simulations
2. ESD layout/design rule checks
3. Software programs for automatic checks

zDesign Failures
Bad layouts:
not enough contacts, metal lines too narrow, resistors too narrow, nearby
diffusions too close
Bad design:
wrong protection device for the process, non-optimized protection device, no
clamps at input gates, secondary protection not optimized
Process effects:
a sudden change in the critical process parameters for ESD, scaling down with
of dimensions, protection design on the edge with process, change to a new fab
with different controls
45

z Device Modeling Issues


J.E is a good indicator of thermal effects and can be a predictor for device
performance under ESD.
There are electro-thermal simulators that are available and are useful for
studying the device effects.
The silicon parameters with respect to temperature are not accurately
defined

z Limitations of Simulators
At present, electrothermal simulators cannot be confidently used for
predictive capability since the thermal boundary conditions are not well
defined and the 2-D effects of the process and 3-D effects of the thermal
conditions are not well represented.
3-D effects of the thermal conditions are not well represented
Simple mixed mode simulators that are user-friendly are not available
46

Protecting IGBTs and MOSFETs


z Common

cause of ESD failures in MOS-gated devices


ESD induced dielectric breakdown
Destruction of the gate oxide by ESD is unavoidable for MOS-gated devices
Compared with MOS IC devices, power devices are considered less sensitive to ESD due to relatively
large input capacitance, but ESD becomes more serious threat to power devices as the gate oxide
becomes thinner

Effective ESD Control Program


1. Always store and transport MOSFETs in closed conductive containers.
2. Remove MOSFETs from containers only after grounding at a Static Control
Work Station.
3. Personnel who handle power MOSFETs should wear a static dissipative
outer garment and should be grounded at all times.
4. Floors should have a grounded static dissipative covering or treatment.
5. Tables should have a grounded static dissipative covering.
6. Avoid insulating materials of any kind.
7. Use anti-static materials in one-time applications only.
8. Always use a grounded soldering iron to install MOSFETs.
9. Test MOSFETs only at a static controlled work station.
10. Use all of these protective measures simultaneously and in conjunction
with trained personnel.

When an ESD-sensitive device, such as a power MOSFET, becomes part of the discharge path, or is
brought within the bounds of an electrostatic field, it can be permanently damaged.
47

z Gate contact and geometry design

K. Throngnomchai, TED, 1994

ESD failure threshold depends on the size, shape of gate contact as well as the gate polySi sheet resistance

Limit the gate voltage and ESD current

48

Simulated ESD charge density stored on the gate poly silicon film

Sample A

Sample B

source

gate

gate contact

Zener diodes

The area near the gate contact is sensitive to ESD pulse since ESD charge diffusion
Into inner region is suppressed by the sheet resistance of gate poly silicon

49

ESD failure threshold depends on the size, shape of gate contact as well as the gate polySi sheet resistance
Widening gate contact size and lowering gate sheet resistance increase ESD failure
threshold

Gate sheet resistance

Gate contact width

50

z Gate Protection using Diodes in IGBTs


In order to bypass the ESD current to the gate, current paths are provided
using the back to back diodes
In general, the diodes are made using gate poly silicon
The zener breakdown voltage should be lower than the dielectric breakdown
voltage not to damage the gate
The zener voltage controlled by the number
of back to back diodes for a given process

C
ESD

G
E

51

z BV of Poly diode depending on Boron Dose


( - various diffusion recipes)
20

Process
Process
Process
Process

Poly Diode BV (V)

18

A (950 C)
B (1000 C)
C (1150 C)
D (1100 C)

16
14
12
10
8
6
1E13

1E14

Dose (Boron)

52

1E15

z Poly diode implementation

<SEM photo of a diode on gate pad>

53

zESD Robustness of Power MOSFET


(without protection)
HBM/MM strength increases with the chip size (Ciss=Cgs+Cgd)

8000

2100

HBM[V]

MM[V]

7000
1800

6000
1500

5000
1200

4000
900

3000
600

2000

300

1000
0
1000

2000

3000

4000

5000

6000

7000

8000

9000

Size [um2]

0
1000

2000

3000

4000

5000

6000

Size [um2]
54

7000

8000

9000

HBM/MM strength increases with Gox


(Not always, trade-off with Ciss)
Gox 500
Gox 580
Gox 780
Gox 970
Gox 1480

Gox HBM LEVEL


3000

1480A

2500

970A
580A 780A

HBM[V]

2000
970A

1500
500A
780A

1000
580A

1480A

500
500A

0
2000

4000

55

um

HBM/MM strength increases with Gox


(Not always, trade-off with Ciss)
Gox 500
Gox 580
Gox 780
Gox 970
Gox 1480

Gox MM LEVEL
1400
1200

MM[V]

1000

580A

1480A

800
500A

600

780A 970A

780A

400

580A

970A

1480A

200
0

500A

2000

4000

56

um

zEOS Failures in IGBTs


EOS induced High Current Damage: All terminals short

External Visual Inspection

57

Internal Visual Inspection

58

EOS induced Burnt Failure Modes


1) Burnt marks on gate bus:
Generally, gate failed due to
applied surge voltage to the
G-C or G-E

2) Burnt marks on the active corners:


Generally, junction failed due to
applied surge voltage to the C-E

59

3) Burnt marks on wire bonding area:


Generally, device failed due to
increased junction temperature
caused by surge current
between C-E

4) Burnt marks on normal active area:


Generally, the failure results from
random defects in the device such as
particle, crack, scratch, contamination etc.
when surge voltage is applied to C-E

60