1.

HIGH SPEEDCMOS PRODUCT GUIDE
Type Number
Function OUAD 2.INPUT NAND GATE OUAD 2-INPUT NOR GATE O U A D 2 . I N P U T N A N D G A T E ( O P E ND R A I N ) HEX INVERTER HEX INVERTER H E X I N V E R T E R( S I N G L ES T A G E ) OUAD 2.INPUT AND GATE T R I P L E 3 . I N P U TN A N D G A T E T R I P L E 3 - I N P U TA N D G A T E H E X S C H M I T TI N V E R T E R

Number Page of Pins
14 14 14 14 14 14 14 14 14 14 107 110 113 117 120 123 125 129 132 135

TC74HCOoP/F TCT4HCO2PIF TC74HC03P/F TCT4HCO4PIF TCT4HCTO4P/F TCT4HCUO4P/F TC74HC08P/F TC74HC10PlF TC74HC1lPlF TC74HC14PlF

TC74HC20PlF TC74HC21PlF TC74HC27PlF TC74HC30P/F TC74HC32PlF TC74HC42PlF TC74HC51P/F TC74HC73PlF TC74HC74PlF TC74HC75PlF

DUAL 4-INPUT NAND GATE DUAL 4.INPUT AND GATE TRIPLE 3.INPUT NOR GATE S.INPUT NAND GATE OUAD 2.INPUT OR GATE BCD TO DECIMALDECODER D U A L 2 W - 2 1A N D / O R I N V E R T G A T E W DUAL J-K FLIP.FLOP ITH CLEAR W D U A L D F L I P - F L O P I T H P R E S E TA N D C L E A R 4.BIT D-TYPE LATCH

14 14 14 14 14 16 14 14 14 16

139 142, 145 148 151 154 158 162 167 't72

TC74HC76PlF TC74HC77PiF TC74HC85P/F TC74HC86P/F TC74HC107P/F TC74HC109P/F TC74HC112PlF TC74HC1 13P/F TC74HC123PlF TC74HC125PlF

W D U A L J - K F L I P - F L O P I T H P R E S E TA N D C L E A R 4-BIT D.TYPE LATCH 4.BIT MAGNITUDE COMPARATOR O U A D E X C L U S I V EO R G A T E W DUAL J.K FLIP.FLOP ITH CLEAR W D U A L I - R T L I P - F L O P I T H P R E S E TA N D C L E A R W D U A L J . K F L I P . F L O P I T H P R E S E TA N D C L E A R W DUAL J.K FLIP-FLOP ITH PRESET M DUAL MONOSTABLE ULTIVIBRATOR OUAD BUS BUFFER (3-STATE)

16 14 16 14 14 16 16 14 16 14

177 182 187 192 196 201 206 211 216 224

Type Number
TC74HC126PlF TC74HC131PlF TC74HCr32PlF TC74HC133P/F TC74HC137PlF TC74HCT137PlF Tg74HC138P/F TC74HCT138P/F TC74HC139P/F TC74HC147PlF

Function
OUAD BUS BUFFER (3.STATE} 3-TO€ LINE DECODER/LATCH OUAD 2.INPUT SCHMITT NAND l3-INPUTNAND GATE 3-TOA LINE DECODER/LATCH 3-TO€ LINE DECODER/LATCH 3-TO-8 LINE DECODER 3-TO€ LINE DECODER DUAL 2-TO4 LINE DECODER 1 O . T O 4 L I N E P R I O R I T YE N C O D E R

Number Page of Pins
14 16 14 16 16 16 16 16 16 16

224 229 235 239 ,242 248 254 259 264 268 272 277 282 288 293 297 297 302 302 302 302 512 317 323 329 334 339 344 355 362

TC74HC148PlF TCT4HC1slP/F TC74HC153P/F TC74HC154P TC74HC155P/F TC74HC157PlF TC74HCls8P/F TC74HC160P/F TC74HC161P/F TC74HC162P

8-TO-3 LINE PRIORITY ENCODER S . C H A N N E LM U L T I P L E X E R DUAL 4-CHANNEL ULTIPLEXER M 4.T0-16 LINE DECODER DUAL 2.TO4 LINE DECODER O U A D 2 . C H A N N E LM U L T I P L E X E R O U A D 2 . C H A N N E LM U L T I P L E X E R( I N V . ) , SYNC. DECADE COUNTERWITH ASYNC. CLEAR S Y N C . B I N A R Y C O U N T E RW I T H A S Y N C . C L E A R S Y N C . D E C A D E C O U N T E RW I T H S Y N C . C L E A R

16 16 16 24 16 16 16 16 16 16

TC74HC163P/F TC74HC164PlF TC74HC165P/F TC74HC166P/F TC74HC173PlF TC74HC174PlF TC74HC175PlF TC74HC181P TC74HC182PlF TC74HC190PlF'

S Y N C . B I N A R Y C O U N T E RW I T H S Y N C . C L E A R 8 - B I T S I P OS H I F T R E G I S T E R 8 . B I T P I S OS H I F T R E G I S T E R 8 - B I T P I S OS H I F T R E G I S T E R OUAD D-TYPE REGISTER(3-STATE) HEX D FLIP.FLOP ITH CLEAR W OUAD D FLIP-FLOP ITH CLEAR W A L I T H M E T I CL O G I C U N I T LOOK AHEAD CARRY LOGIC BCD UP/DOWNCOUNTER

16 14 16 16 16 16 16 24 16 16

Type Number
TC74HC191P/F TC74HC192PlF TC74HC193P/F TC74HC194PlF TC74HCl95P/F TC74Hg221PlF TC74HC237PlF TC74HC238PlF TC74HC240PlF TCt4HCT240P 'tc74HC241PlF TC74HCT241P TC74HC242PlF TC74HC243PlF TC74HC244PlF TC74HCT244P TC74HC245PlF TC74HCT245PlF TC74HC251PlF TC74HC253PlF

Function
4-BIT BINARY UP/DOWNCOUNTER SYNC. UP/DOWNDECADE COUNTER

Number Page of Pins
16 16 16 16 16 16 16 16 20 20 362 372 372 381 387 393 401 107 411 117 411 117 122 422 4il 417 127, 432 437 282 442 442 447 453 458 462 466 470 475 475

IFF -"ilYll.g'.-uP/"P.9Jx-,"atNARY,"c.*o",!llf
4 . B I T P I P OS H I F T R E G I S T E R 4.BIT PIPO SHIFT REGISTER DUAL MONOSTABLEMULTIVIBRATOR 3-TO€ LINE DECODER/LATCH 3.TO-8 LINE DECODER OCTAL BUS BUFFER (3.STATE/INV.} OCTAL BUS BUFFER (3-STATE/INV.I OCTAL BUS BUFFER (3-STATE) OCTAL BUS BUFFER (3-STATE) OUAD BUS TRANSCEIVER(3-STATE/INV.) OUAD BUS TRANSCEIVER(3.STATE) OCTAL BUS BUFFER (3-STATE) OCTAL BUS BUFFER (3.STATE} OCTAL BUS TRANSCEIVER(3-STATE) OCTAL BUS TRANSCEIVER(3.STATE) 8-cHANNEL MULTrPueien (3-srATE) DUAL 4-CHANNEL MULTIPLEXER (3.STATE) OUAD 2-CHANNEL MULTIPLEXER (3.STATE) O U A D 2 . C H A N N E LM U L T I P L E X E R( 3 . S T A T E / I N V . ) 8.BIT ADDRESSABLELATCH OCTAL D FLIP-FLOP ITH CLEAR W OUAD S.R LATCH 9-BIT PARITY GENERATOR/CHECKER 4.BIT BINARY FULL ADDER O U A D 2 . C H A N N E LM U L T I P L E X E R / R E G I S T E R 8-BIT PIPOSHIFT REGISTER 8 . B I T P I P OS H I F T R E G I S T E R

20 20 l4 14 20 20 20 20 16 16

TC74HC257PlF TC74HC258PlF TC74HC259PlF TC74HC273PlF TC74HC279PlF 'TC74HC280PlF T.cta{czegplr TC74HC298P/F TC74HC299P TC74HC323P

16 16 16 20 16 14 16 16 20 20

Type Number
TC74HC3ilP/F TC74HC356P/F TC74HC365P/F TC74HC366P/F TC74HC367P/F TC74HC368P/F TC74HC373P/F TC74HCT373PlF TC74HC374PlF TC74HCT374PlF

Function
S.CHANN L MULTIPLEX E ER/REGISTER S.CHANNEL MULTIPLEX ER/REG ISTER HEX BUS BUFFER I3-STATE} HEX BUS BUFFER (3-STATE/INV.I HEX BUS BUFFER (3.STATE) HEX BUS BUFFER (3.STATE/INV.) OCTAL D-TYPE LATCH (3-STATE} OCTAL D.TYPE LATCH (3-STATEI OCTAL D.TYPE FLIP.FLOP (3-STATEI OCTAL D.TYPE FLIP.FLOP (3-STATE}

NumberPage of Pins
20 20 16 16 16 16 20 20 20 20 485 191 497 197 502 502 507 514 519 526

TC74HC375P/F TC74HC377PlF TC74HC386P/F TC74HC390P/F TC74HC393P/F TC74Hc/.23PlF TC74HC533P/F TC74HC534P/F TC74HC540P/F TC74HCT540P/F

OUAD D.TYPE LATCH OCTAL D-TYPE FLIP.FLOP O U A D E X C L U S I V EO R G A T E DUAL DECADE COUNTER

16 20 14 16 14 16 20 20 20 20

532 536 541 545 552

. 3L P.-y. BlNARYCouNrrER.".-.DUAL MONOSTABLEMULTIVIBRATOR OCTAL D.TYPE LATCH (3.STATE/INV.) OCTAL D-TYPE FLIP.FLOP (3-STATE/INV OCTAL BUS BUFFER (3-STATE/INV.) OCTAL BUS BUFFER (3.STATE/INV.) OCTAL BUS BUFFER (3.STATE} OCTAL BUS BUFFER (3.STATE} OCTAL D-TYPE LATCH (3-STATE/INV.) OCTAL D.TYPE LATCH (3.STATE/INV.) OCTAL D.TYPE FLIP-FLOP(3.STATE/INV OCTAL D.TYPE FLIP-FLOP(3-STATE/INV OCTAL D-TYPE LATCH (3-STATE) OCTAL D-TYPE LATCH (3.STATEI OCTAL D.TYPE FLIP-FLOP (3.STATE} OCTAL D-TYPE FLIP.FLOP(3-STATE)

5s8
507 519 566 571 566 571 507 576 519 582 507 576 519 582

TC74HC541PlF TC74HCTs41PlF TC74HC563P/F TC74HCT563P TC74HCs64P/F TC74HCT564P TC74HCs73P/F TC74HCT573P TC74HC574PlF TC74HCT574P

20 20 20 20 20 20 20 20 20 20

Type Number
TC74HC590P TC74HC592P TC74HC593P * TC74HC595P TC74HC597P/F TC74HC620P TC74HC623P TC?4HC640P/F TCT4HCTilOP/F TC74HC643PtF

Function
(3.STATE) 8-BIT BINARY COUNTER/REGISTER 8.BIT REGISTER/BINARY OUNTER C 8.BIT REGISTER/BINARY COUNTER (3-STATE) (3-STATE} 8.BIT SHIFT REGISTER/LATCH 8 . B I T L A T C H / S H I F TR E G I S T E R OCTAL BUS TRANSCEIVER(3.STATE/INV.) OCTAL BUS TRANSCEIVER(3-STATE) OCTAL BUS TRANSCEIVER(3.STATE/INV.} OCTAL BUS TRANSCEIVER{3-STATE/INV.) OCTAL BUS TRANSCEIVER(3-STATE) OCTAL BUS TRANSCEIVER(3-STATE) (3-STATE) OCTAL BUS TRANSCEIVER/REGISTER OCTAL BUS TRANSCEIVER/REGISTER {3-STATE) (3-STATE/INV.} OCTAL BUS TRANSCEIVER/REGISTER (3.STATE/INV.) OCTAL BUS TRANSCEIVER/REGISTER (3-STATE/IITIV.} OCTAL BUS TRANSCEIVER/REGISTER OCTAL BUS TRANSCEIVER/REGISTER f3-STATE/INV.) (3.STATE) OCTAL BUS TRANSCEIVER/REGISTER (3-STATE} OCTAL BUS TRANSCEIVER/REGISTER 4-WORD 4-BlT REGISTERFILE (3-STATEI x

Number of Pins Page 16 16 20 16 16 20 20 20 20 20 20 24 24 24 24 24 24 24 24 16 20 20 20 20 20 20 20 20 20 14
703 604 612 620 620 427 452 127 s88 596

TC74HCT643PlF TC74HC646P TC74HCT646P TC74HCil8P TC74HCT648P TC74HC651P TC74HCT651P TC74HC652P TC74HCT652P TC74HC670P

132 625 633 625 633 611 649 61r 619 657

TC74HC688P/F TC74HC690P TC74HC691P TC74HC692P TC74HC693P TC74HC696P TC74H0697P TC74HO698P r TC74HO699P' TCT4H@,0p,2PIF

8-BIT EOUALITY COMPARATOR DECADE COUNTER REGISTER(3.STATEI 4.BIT BINARY COUNTER REGISTER(3.STATEI DECADE COUNTER REGISTER(3.STATE) 4-BIT BINARY COUNTER REGISTER(3.STATE} (3.STATEI U/D DECADE COUNTER/REGISTER (3.STATE} U/D 4.BIT BINARY CTR./REGISTER (3-STATEI U/D DECADE COUNTER/REGISTCN (3-STATEI U/D 4.BIT BINARY CTR./REGISTER DUAL +INPUT NOR GATE

661 668 668 680 680 692 692

Type Number
TC74HO.l017PlF TC74HC4020PlF TC74HC4022PIF TC74HC4024PlF TC74HC4028PlF TCT4HC40/,OPIF TC74HC4049PlF TC74HC40s0P/F TC74HC4051P* TC74HC4052P * TC74HC4053P r TC74HC4060P/F TC74HC4066P/F TC74HC4072PlF TC74HC4075PlF TC74HC4078PlF TC74HC/,O94PlF TC74HC40102P TC74HC40103P TC74HC4511PlF

Function
D E C A D EC O U N T E R / D I V I D E R 14-STAGE INARY COUNTER B OCTAL COUNTER/DIVIDER 7 - S T A G EB I N A R Y C O U N T E R DECODER BCD-TO-DECIMAL 12.STAGEBINARY COUNTER H E X B U F F E R( I N V . ) HEX BUFFER S . C H A N N E LA N A L O G M U L T I P L E X E R D U A L 4 . C H A N N E LA N A L O G M U L T I P L E X E B

Number Page of Pins
16 16 16 14 16 16 16 16 16 16 706 712 717 723 728 733 738 738

T R I P L E 2 - C H A N N E LA N A L O G M U L T I P L E X E R 14.STAGEBINARY COUNTER/OSCILLATOR OUAD BILATERALSWITCH D U A L 4 - I N P U TO R G A T E T R I P L E 3 - ! N P U TO R G A T E S.INPUT.OR/NOR ATE G ( 8 . B I T S I P O S H I F T R E G I S T E R / L A T C H3 - S T A T E } DUAL BCD PROGRAMMABLE OWNCOUNTER D 8.BIT BINABY PROGRAMMABLE DOWN COUNTER BCD TO 7 SEGMENTL/D/D (LED}

16 16 14 14 14 14 16 16 16 24

u,
748 753 757 761 765 772 772 785 790 790 795 795 802 8r0 816

TC74HC4514P TC74HC4515P TC74HC4518PlF TC74HC4520PtF TC74HU538P/F TC74Hc4il3PlF TC74HCT70o7PlF TC74HC7266P/F TCt4HC7292P TC74HC729ttP

4 - T O - 1 6L I N E D E C O D E R / L A T C H ( 4 . T 0 - 1 6 L I N E D E C O D E R / L A T C H! N V . ) D U A L D E C A D EC O U N T E R DUAL 4.BIT BINARY COUNTER , DUAL MONOSTABLEMULTIVIBRATOR BCD TO 7 SEGMENT LIDID (LCD} HEX BUFFER OUAD EXCLUSIVENOR GATE PROGRAMMABLE DIV IDER/TIMER PROGRAMMABLE IVIDER/TIMER D

24 24 16 16 16 16 l4 14 t6 16

Er9 023 E2g

Note:

1. All DIP 24 pin productsservice an enclosure the narrow type (300mil) as of 2. * denotesthe productsunder development

2.

HIGH SPEEDCMOS SETECTIONGTIIDE
FTJNCTTON

TYPE N['MBER, 74HC{n,74HC'03, 74HC1 74Hc,;O, 0, 74HC30, 4HCl33 7 74H@2,74HC27, 4HC4002, 4HC407 7 7 8 74HC08,74HCll, 74HC2l 2, 74HC32,74HC407 74HC407 74HC407 5, I 74HCI)4, 4HC|O4 7 74HCU04, 74HCt4,74HCt32
266 74HC5 74HC86,74HC386,7 4HC7 l,

GATE

NAND NOR AND OR II{VERTER SCHMITT TRIGGER MULTIFUNCTION

BI,JFFER

74HC4049, 007 74HC4050, 4HCT7 7 3.STATE
7 4HCt25, 7 4HCl26, 7 4HC240, 7 4HCT240, 7 4HC24l, 7 4HCT24t, 7 4HC244, 7 4HCT244, 7 4HC365, 7 4HC366, 74HC367, 4HC54l, 74HCT541 74HC368,74HC540,74HCT540,'.| 74HC242, 7 4HC243, 7 4HC245, 7 4HCT245, 7 4HC620 7 4HC623, 7 4HC640, 7 4Hef 640, 7 4HC643,'t 4HCT643 7 4HC73, 7 4HC7 7 4HCt07, 74 HCI 09, 7 4HCt 12, 74HCl I 3 6, 7 4HC74, 7 4HCt7 4, 7 4HCL75, 7 4HC273,',t 4Hc37'.l 4HC564,7 4HCT5 64, 74HC374,74HCT374 4HC534,',t 7 74HC574,74HCT5747 4HC646, 7 4HCT646, 7 4HC648, 74HCT648,74HC651 74HCT65l, 7 4HC652,7 4HCT652 7 4HC75, 7 4HC77, 7 4HC259, 7 4HC279, 7 4HC37S

BIDIRECTIONAL FLIP.FLOP J-K, FLIP-FLOP D F L IP-FLOP 3.STATE

LATCH

I
MULTIVIBRATOR DECODER

rsrarE

3, 7 4HC37 7 4HCt 373, 74HC533, 7 4HC563, 74HCT563, 't4HC573,74HCT573 7 4HCt23, 7 4HC22t, 7 4HC423, 74HC4538 7 4HC42, 7 4HCl3l, 7 4HCt37, 7 4HCT137, 74HC138, 55, 74HCT1 74HCl 39, 7 4HCr54, 74HC1 7 4HC237, 38, 7 4HC2?8, 7 4HC4028, 7 4HC45 | 4, 74HC45r 5

I z-sncrtrnxr
ENCODER REGISTER COUNTER BINARY

74HC45t1,74HC4543

74HC147,74HC148
7 4HCt 64, 74HCt 65, 7 4HCt 66, 7 4HCt7 3, 7 4HCI94, 74HC1 95, 4 7 4HC299, 7 4HC323, 74HCs95, 7 4HC597, 7 4HC670, 7 4HC409 7 4HCt6t, 7 4HCt 63, 74HCl 9 1, 7 4HCt93, 74HC393,74HC590, 7 4HC592, 74HC59 3, 7 4HC69t, 7 4HC693, 7 4HC697, 7 4HC699, 74HC4520 74HCI 60, 7 4HCt 62, 74HC1 90, 7 4HCt92, 74HC390,74HC690, 7 4HC692, 7 4HC696, 7 4HC698, 74HC45I 8

DECADE DIVIDER
MULTI.PLEXER ANALOG DIGITAL OTHERS CQMPARATOR

74HC4017, 4HC4020, 4HC4022, 4HC4024, 7 7 7 74HC4040, 74HC4060, 4HC40 02, 74HC40 ? I tO3,74HC7 292,74HC7 4 29
74HC4051, 7 4HC4052,74HC4053,7 4HC4066 1, 74HC15 74HCl 5 3, 74HCl 57, 74HC1 8, 7 4HC2SI,7 4HC25?, 5 7 4HC257,74HC258, 7 4HC298,7 4HC354,74HC356 74HC85,74HC688 74HC283

ADDER
ALU

74HC181,74HCt82
74HC280

PARITYTREE

l0

GATE
Type Number 74HC 74HC 74HC 74HC 74HC 00 03 10 20 30 Function QUAD2-INPUT NANDGATE QUAD2-TNPUT NANDGATE (oPEN DMrN ) TRIPLE 3-INPUT NA}ID GATE DUAL 4-INPUT NAND GATE 8-INPUT NAND GATE l3-INPUT NAND GATE QUAD2-INPUT NOR GATE TRIPLE 3-INPUT NORGATE DUAL 4-INPUT NOR GATE 8-INPUT OR/NORGATE QUAD2-INPUT AND GATE TRIPLE 3-INPUT AI{D GATE DUAL 4-INPUT AND GATE QUADz-INPUT OR GATE TRIPLE 3-INPUT OR GATE DUAL 4-INPUT OR GATE 8-INPUT OR/NORGATE HEX INVERTER HEX INVERTER HEX INVERTER(SINGLE STAGE) DUAL 2W-2I AND/OR INVERT GATE QUADEXCLUSIVE0R GATE QUADEXCLUSM NOR GATE QUADEXCLUSIVEOR GATE HEX SCHMITT INVERTER QUAD2-INPUT SCHMITTNAND Equivalent LSTTL LSOO LSO3 LS]-O LS2O LS3O LS133 LSO2 LS27 *LS25 LSOS LS11 LS21 LS32 Equivalent

cMos.

Pin Number

4011, 740O L 4 ,k40107,' 15029 4 T 4023 14 40L2 T4 4068 I4 4001 4025,*4000 4002 4078
4081 4073 4082 4 07 L 16 14 L4 L4 14

TAHC I 3i

7 4HC 02 74HC 27 74HC4002
TLHe.ttOTR

74HC 08 74HC 1 1 74HC 2 L 74HC 32 74HC4075 74HC4072 74HC4078 74HC 04 74HC T04 74HC u04 74HC 51 74HC 86 74HC7266 74HC 386 7 4HC L4 74HC I32

T4 L4 L4
14 14 L4 14 L4 14 I4 L4 14 14 I4 14 14

LS04 LS04 *LS04 LS51 L S 8 6 ,L S 3 8 6 *LS266 L S 8 6. t S 3 8 5 LS14 LS132

407 5 4072 4078 * 4069U * 4069U 4069u.7404u
*4085 4030 4077 4030 4584 4093

* Suggested alternative

GATE 2.INPUT NAND GATE QUAD 00 P o s i t i v e ' l o g i c :Y = A E
3A

NOR z-INPUT GATE QUAD 02 Positiveogic: Y = A+E l

11

GATE (Continued) (0PEN NAND DRArN) 0uAD2-TNPUT GATE 03 Positivelogic:
vcc 4E} 44

f = AB
4Y 3B 3A 3Y

HEXNVERTER I 04 T04 u04 P o s i t i v eo g i c : f : l
vcc 6A 6Y 5/, 5Y

F
4A 4y

2.INPUTANDGATE QUAD 08 P o s i t i v e o g i c : f = AB l
vCC 49 4A ay 38 3A

T R I P L 3 . I N P UN A N G A T E E T D t0 Positivelogic: Y=ABd
vcc 1c LY 3C 38 3A

TRIPLE-3-INPUT ANDGATE l1 Positive 'logic: ABC

HEX SCHMITTINVERTER 14 Positivelogic: Y

r
5Y 4 A

1Y

12

GATE (Continued)

DUAL NAND GATE 4.INPUT 20 'log'ic: = Positive Y IBCD
vcc zD zc Nc pB zA zy

DUAL AND 4-INPUT GATE 21 'logi P o stii v e c: Y = ABCD
vcc 2D 2c Nc ?B 2A

TRIPLE -INPUT OR ATE 3 N G 27 Positive
vcc

'logic:

Y = A+B+C

8-INPUT GATE NAND 30 Positive log'ic: Y =TBCDEFGH
VCCNCHGNCNCY

l-c

lY

z.INPUT GATE OR QUAD 32 Positjvelogic: Y=A+B
VCC 48 4A 4Y 3B 3A 5Y

IN D U A L W ID E -2IN P U T N D /OR V E R T 2 A GA 5l P o s ' i t i v el o g i c : 1 Y = f f i 2Y=2[-291fi.fi

I
i-l '-.; , t--'

:f

'"--f'_!'-

t

i

r, :..i I i ' -j '',-ii t; I

I

13

G ATE (C ont inued) 2 E GA QU AD -IN P UT X CLUS IVE -O RT E 86 Po si ti ve logic : Y = A @ B= A B+ A E
VCC 48 4A 4Y 38 3A 3Y

2-INPUT SCHMITT NAND GATE QUAD 132 Positive logic: Y =TBVCC 48 4A 4Y 3B 3A 3Y

I 3-IN PU TNA ND A T E G .|33

2-INPUTEXCLUSIVE-NOR GATE QUAD 7266 Y=[-@-9=43+ffi
4Y 3Y 3B 3A

Positive logic: Y=ABCDEFGHTJK[]*f Positive logic:
VCCMLKJIHY VCC 48 4A

z-TNPUT EXCLUSTVE-OR GATE QUAD 386 P o si ti ve logic : Y = A O B = AB + AB vcc 48 +t ax 3Y 38 3A

DUAL 4-INPUT GATE NOR 4002 Positive logic: Y=ATBTCTD
vcc 2y 2A 28 2C 2D

14

GATE ( Cont inued)

DUAL 4-INPUT GATE OR 407? Positive logic' Y=A+B+C+D
vcc 2Y 2D 2c 28 2A

T R IPL E 3.IN P U T GA TE OR 4075 Positive logic: Y=A+B+C
vco 3c 3E| 3A 3Y

8 -INP UT R A T E NO G 4078 P o s i t i v e l o g i c : Y=A+B+C+D+E+F+G+H
VCCXH GFENC

NC

GND

15

BUFFER
Type Number 7 4HCr700i 74HC4049 74HC4050 74HC L25 74HC L26 74HC 240 74HCT240 74HC 24L 74HCT24L 74HC 244 74HCr244 74HC 365 74HC 366 74HC 367 74HC 368 74HC 540 74HCT540 74HC 54r 74HCT54L 74HC 242 74HC 243 74HC 245 7 4HCT245 74HC 620 74HC 623 74HC 640 74HCT640 74HC 643 74HCT643
Function Equivalent LSTTL Equivalent

cMos.
4049 4050 5024 5025

Pin Number

HEX BUFFER HEX BUFFER(INVERTING) HEX BUFFER QUADBUS BUFFER QUADBUS BUFFER OCTALBUS BUFFER(II{VERTING) OCTALBUS BUFFER(INVERTING) OCTALBUS BUFFER OCTALBUS BUFFER OCTALBUS BUFFER OCTALBUS BUFFER HEX BUS BUFFER HEX BUS BUFFER (INVERTI}IG) HEX BUS BUFFER HEX BUS BUFFER (INVERTII.IG) OCTALBUS BUFFER(rlrvERTrNG) OCTALBUS BUFFER(INVERTING) OCTALBUS BUFFER OCTALBUS BUFFER QUADBUS TMNSCETVER (INVERTING) QUADBUS TRANSCEIVER OCTALBUS TMNSCEIVER OCTALBUS TMNSCEIVER OCTALBUS TMNSCEIVER (TNVERTTNG) OCTALBUS TRANSCEIVER OCTALBUS TMNSCEIVER (INVERTING) (INVERTING) OCTALBUS TRANSCEIVER OCTALBUS TRANSCEIVER OCTALBUS TMNSCEIVER

* LS0T

LS125 LS126 LS24O

rs240
LS24L LS24I L5244 L5244 LS3654 LS366A LS367A LS368A LS540 LS540 LS541 LS541 L5242 LS243 L5245 L5245 LS62O L5623 LS64O LS640 LS643 LS643

50r_2

L4 16 16 L4 L4 20 20 20 20 20 20 16 16 16 16 20 20 20 20 L4 L4 20 20 20 20 20 20 20 20

* Suggested alternative

B UFFER H EXBUFF E R. T7007 Positivelogic:

Y=A
5A

BUS QUAD BUFFER 125 P o s i t i v e ' l o g i c :Y = A
4Y

vcc

6A

6Y

5 Y 4A

r.-e l,c, t y

zd

zt

2Y

GND

l6

( B U F F E R C o n t in u e d ) B QU AD USB UF F E R 126 'logic: Positive

OCTAL U SB U F F E ( I N V E R T I N G ) B R 240 T240
3G 3Y

vcc

LG

4A

4Y

v"o eo rTr a.g ttezns rW eez lt{ 2A"r

IA

IY

2G

2A

2Y

rE r,c,r z1+ ua ?ft rAs zre t*

e?r el.ro

OCTAL BUFFER BUS 241 T241
20 lYl 2A4 IYz 2A3 1Y5 2|A I.r4 2AI

(I R B T Q U A D U S R A N S C E I V EN V E R T i N G ) 242
vcc
NC

1B

2B

3B

4B

tG

l.Al

2y4 IAZ

zys

l-AS 2y? 1A4 Ayl

oND

BUSTRANSCEIVER QUAD

24s

OCTAL BUFFER BUS 244 T244
v"s zd- t-yt ?A4 lYz 3A3 IW 2A2 r-Yt 2AL

rG

]-A.I ZYL IA?" ?Y3 1A5

?YZ IA4

2Y1 OND

17

( BUFFERContinued) I VER OCTAL BUSTRANSCE 245 T245
vcc c
B1

HEX BUS BUFFER 365

B3

Py'.

B.5

B6

DIR A 1

jtz

Ag

A4

A6

L7

A8

HEX BUS BUFFER( I N V E R T I N G ) 366
Q2 6A 6Y 4A

HEX BUS BUFFER 367

4y

vcc

c2

6A

O Y

5Y

4A

I H E XB U S U F F E(RN V E R T I N G ) B 368

O C T A B U SB U F F E( I N V E R T I N G ) L R 540 T540
v"" Ea ?r Tz -ys T+ yo tb y?
VR

1A

1v

2A

2Y

3Y

Af

AZ

A4

A5

A6 A1

A8

t8

( B U F F E R C o n t in u e d ) OCTALBUS BUFFER 541 T5 4 t
VOc OZ y1 yz Y4 Y5

O C T AB U ST R A N S C E I V EN V E R T I N G ) L (I R 620
ENABLE GBA

olf, al-

az

!|.6 A7

A8

GND

AI ENABLE GAB

OCTALBUS TRANSCEIVER 623

( OCTALBUSTRANSCEIVERI N V E R T I N G ) 640 T640
vcc c Bt 92 B3 84
B5 B? B8

ENABLE GAB DIR A I L2

A3

A4

A5

A6

A7

A8

OCTALBUS TRANSCEIVER 643 T6 4 3

B I TER H E X U F F E R / C O N V E(RN V E R T I N G ) 4049

6Y

6A

NC

5Y

5A

+Y

4A

vcc

1Y

l-A

2Y

2A

3Y

l9

) ":

BUFFER( Cont inued) HEXBUFFER/CONVERTER 4050

20

FL I P - F L O P
lYpe Number 74HC 73 74HC 76
Function Equivalent LSTTL Equivalent CMOS. Pin Number

DUAL J-K FLIP-FLOP DUAL J-K FLIP-FLOP AND CLEAR 74HC rO7 DUAL.J-K FLIP-FLOP 74HC LOg DUAL J-R FLIP-FLOP AND CLEAR 74HC LLz DUAL J-K FLIP-FLOP AND CLEAR 74HC LL3 DUAL J-K FLIP-FLOP t4HC t4 74HC l-74 74HC L75 74HC 273 7 4 H C3 7 7 74HC 374 74HCT374 74EC 534 74HC 564 74HCT564 74HC 574 74HCT57 4 74HC 646 74HCT646 74HC 648 74HCT648 74HC 65L 74HCT651 74HC 652 74HCT652

WITH CLEAR WITH PRESET WITH CLEAR WITH PRESET I^IITHPRESET WITH PRESET

L S 7 3 AL S 1 0 7 t , L S 7 6 A L S l 1 2 d 4027,7 47 ( , L S 1 0 7 AL S 7 3 r , LSlO9A L S 7 6 A , L S 1 1 24027 ,7 47C r LS113A LS744 LSIT 4 L5175 L5273 LS374,L557 4 LS374,L557 4 LS534 'LS564 LS564 LS374 ,L557 4 LS374, S574 L LS646 LS646 LS648 LS648 LS651 LS651 LS652 L5652
* Suggestedalternative

L4 16 L4 L6 I6 L4

DUAL D FLIP-FLOP WITH PRESET AND CLEAR HEX D FLIP.FLOP T{ITH CLEAR QUAD D FLIP-FLOP WITH CLEAR OCTAL D FLIP-FLOP WITH CLEAR OCTAL D-TYPE FLIP.FLOP

4013 4017 4 4017 5

L4 L6 16 20 20

OCTALD-TYPE FLIP.FLOP (3-STATE) OCTALD-TYPE FLIP-FLOP (3-STATE) OCTALD-TYPE FLIP.FLOP (3-STATE/INV. ) OCTALD-TYPE FLIP.FLOP (3-STATE/INV.) OCTALD-TYPE FLIP-FLOP (3-STATE/INV. ) ocTAL D-TYPE FLrP-FLOP (3-STATE) ocTAL P-TYPE FLrP-FLOP (3-SrAru; OCTALBUS TRANSCEIVER/REGISTER OCTALBUS TMNSCEIVER/REGISTER (INV.) OCTALBUS TRAI{SCEIVER/REGISTER (INV.) OCTALBUS TMNSCEIVER/REGISTER (INV.) OCTALBUS TRAI{SCEIVBR/REGISTER (INV.) OCTALBUS TMNSCEIVER/REGISTER OCTALBUS TMNSCEIVER/REGISTER OCTALBUS TRANSCEIVER/REGISTER

20 20 20 20 20 20 20 24 2.4 24 24 24 24 24 24

FLI P-FLOP CLEAR

73

DUALD C L E AR 74

L

vcc eclF eo ecx EFn zQ ZC

rET rdlF rx

vcc Zd zcr,F ar

21

F L I P - F L 0 P( C o n t i n u e d ) T hlI DUALJ-K F LI P - F LO P T HP R E SEAN D CLEAR 76
_

W DUAL - K F LIP -FLOP ITHC LE A R J 107

vcclcLR

lc1( 2K

zcLR-""

9^v

DUAL J-R- FLIP-FLOP t^lITH PRESET CL EAR 109
yqg krcl,R ZJ zK acK zpR ze zq

D U AL -K F LIP -FLOP ITHP R E S E T W J CLEAR 112
vcc LCLRecmZcr ar Z; 'Zen zq

DU AL J-K FLI P - F LO P, J I TH t ll3

H E XD F L IP -FLOP ' | ITH LE A R I' C 174
vcc 6e 6D 5D oe 4D 4e
CI.oCK

ka

CLR

lQ

GND

22

F L I P - F L O P( C o n t i n u e d ) W D QU AD F LI P - F LO P I THC L E AR 175 W OC T AL FLIP -FLOP ITHC LE A R D 273
7D ?Q 6Q 6D

dr.een rq

rE- ro

2D ?0

(3-STATE) OCTAL FLrP-FLoP D 374 T374

OCTAL FLIP-FLOP D 377
5Q CI,oK

3 o c r A LD F L r P - F L 0(P - S T A T E / r N V . ) 534
Q4 CTOCX,

(3 O C T A LF L I P - F L O P. S T A T E / I N V . ) D 564 T564
voo d6 oJ qT G a4 G G GoLosK

Q1

de

23

FLIP-FL0P(Continued)' D 0CTAL F LI P - F L0P ( 3- ST A T E) 574 T57 4
vcc
Ql Q4 Q6 Q7 cIOCK

B ER OC T AL U STR A N S C E IVR E GIS TE R ( 3-STATE ) 646 T646 crc&aBlcr
VccBA I o

Fryryry JAFryFryry tr.' trrrrllllll:J:
Bl BA BS 84

BO 86

87

BB

| |

.'uo.*o

81 Bz Bs 84 Dt, Bc Bry

it-1'*
"i"f"+fl.fi

T l l I * A B D I R AA z A s 4 4 A b A 6 A ? A s I i

'" lIi II

l\-Twl_i
RE O C T AB U S R A N S C E I V I RG I S T T R L T ( 3 - S T A T E / I N)V . 64 8 T 64 8

MG]iTEb-TiIjJA5 46 A A.r A2
43 4

A? A8 GND

ER O C T AB U S R A N S C I I VR E G I S T I R L T ( 3 -s rATEI/ N V ) . 6 5 .| T65l '10:*
Ba Bs 84 B5 86 B? BB

tTl ,t4lTl tTryqqF,Tl FqEtiab=r
CBA SBA cAB SAB DIR A1 A;E A3 A4 A5 A6 A7 Bf 82 B5 84 85 86 B? 88 A8

CLOCK TENABL,E vcc M i GBA Bl-

|

| caecee

II

GBA

B1 82 Bs 84 85 B5 El

lll

ldcAB
lll

*l-JI

5 s A B o A B A r A z A s A 4 A 6 A zA 8 | |

Af . DIRECTION

A2

A3

"T{rt#fffiEAr

Aa As A4 A5 .c'6A? AB GND

BU REG O CTAL ST RA NS CE I V E R S IS T ER ( 3 -STAT)E 652
T652 sELEcr
cTPcK;h'IABLE vcc s llne I ar na Bg 84 E|5 86 B7

CBA SBA C}BA CAB

B1

BA

B3

84

B5

86

gI

8A3

CIAB Af

A2

A5

cl,oq( | ENABLE AL A2 AB I GAB SELECT AB

24

MULTIVIBRATOR
Type Number 74HC l23 74HC 22L 74HC 423 74HC4538
Function Equivalent LSTTL Equivalent CMOS.

Pin Number 16 16 16 16

DUAL MONOSTABLE MULTIVIBMTOR DUAL MONOSTABLE MULTIVIBRATOR DUAL MONOSTABLE MULTIVIBMTOR DUAL MONOSTABLE MULTIVIBMTOR

LSl23 LS22L L5423 :tLS423

rt4538,*4528 *4538,*4528 *4538,x4528 4538, 4528

+ Suggestedalternative

MU L TI V I B M T O R MULTIMONOSTABLE DUALRETRIGGERABLE VIB RA T O R 123
F U N CT I O N T A B I , E INPUTS OU T P U T S B

DUAL MONOSTABLE MULTIVIBRATOR 221
FUNCTION TABIJE I N P U TS
CIJEAR
A

OUTPUTS B

ci.nen
L H H H H

A

ee,
I,H I,H r. JL H .|'f

ce

XX HX XL LJ 1_H
l r n

r

J L 1 r 'rr n

X:

DON'T CA.RE

]*/"*."*

ro zi

!H HX LH XL lrH H H Ll: ft 1r JL 1.r H 1_H 1r -rL _f I,H X : D O N T CA-RE tRdcx lCx 2Q 2Q zCLR 28

L

xx

MU MONOSTABLEL T I . RETRIGGERABLE MONOSTABLEL T I . DUAL MU RETRIGGERABLE DUAL VI BRATOR VI BRATOR 4538 4?3
FUNCT lON TAB,],E FUNCTION TABLE INPUTS AB
IJ H H H H

INPUTS

O U T P U TS

O U T P U TS

e,q
I,H LH I,H 1f Jt JL1r

XX HX XL
! J L

X:DON lpt/cx f0x VCC

CARE

ra Eb 2CLR

-fH X : D O N T CARE ?1I'r ztz aCD 2A

1B lcLR

25

MULT PLEXER I
Dpc Numbcr 74HC405L 74HC4052 74HC4053 74HlC4066 Functlon 8-CHANNELAI.IALOG MULTIPLEXER DUAI 4-CIHNNEI AIIALOGMULTIPLEXER TRIPLE 2-CIIANNEI AI.IAIOGMULTIPLEXER QUADBII.ATEMI ST{ITCH 8-CITANNEL MI'LTIPLEXER DUAI 4-CIIANNEL MULTIPLEXER QUAD2-CHANNELMULTTPLEXER (II\VERTING QUAD2-CIIANNELMULTIPLEXER 8-CTIANNEL MULTIPLEXER(3-STATE) DUAL 4-CHAI{NEI MULTIPLEXER(3-STATE) (3-SrArn) QUAD2-CHANNEI MULTTPLEXER QUAD2-CHANNEI MUTTTPLEXER (3-STATE II\IVERTING) MULTIPTEXER/REGISTER QUAD2-CHANNEL REGISTER 8-CHANNELMULT IPLEXER/ 8-CI{ANNELMULTIPLEXER/ REGISTER Equivdent LSTTL Equivalont

cMos.

Pin ItLmbcr

74rrc151 74HC 153
74HC L57 74HC 158 74HC 25L

405L 4052 4053 4016.4066 {.45L2 LS151 4539 rs153

16 t6 16 14
16 16 15 16 16 16 16 16 16 2Q 20

rsL57
LS158

rs25L
LS253 L5257 LS258 LS298 LS354 LS356

,c45L2
,t4539

74rrc 253 74rrc 257 74HC258 74EC298 74HC354 74HC356

)t.45L2 *45L2

r Suggcsted altcrnativc

MULTI PLEXER 8-CHANNEL MULTIPLEXER l5l DUAL4-CHANNEL MULTIPLEXER 153
vcc 20 A 3cg 2c? zcl 2c0

Ds'c DZDlD0ywS

z-CHANNEL MULTIPLEXER QUAD 157 NONINVERTED OUTPUTS DATA
ffiEE
vcc 4A 48 4Y gA 3B 3Y

z-CHANNEL MULTIPLEXER QUAD .I58 INVERTED OUTPUTS DATA
vo ffi ar ls E g.A,ss

O

4A484Y

3A3B fA 18 lY 2A 28 2Y

2A

2S

2Y

oND

26

M U L T I p L E X( C o n t i n u e d ) ER
(3 -ST 8- CHAN NE L M ULT T P LE XE R A T E) 251 D U A L -C H A N N E L LTTP LE X(3-S TA TE ) 4 MU ER 253

vcc

2G

A zcs 2c2 ?cI ?c0

D4D5D6D?AB D3c D2 D], DO Y ]Y ST

(3-STATE) QUAD z-CHANNEL MULTTPLEXER (3-STATE) z-CNANNEL MULTTPLEXER QUAD 257 NONINVERTED OUTPUTS DATA 258 INVERTED OUTPUTS DATA

3A

oE s3Y

4A 48

4y

3A gB

OE

4A

48

4Y

gA

3B

S3Y

1A 1B lY

2A

?B 2Y

IA

1B

]Y

?A

2B

?Y

SELECT IA

?A

2B

8Y

OND

MULTIPLEXERS WITH QUADz.CHANNEL OU TPURE G I S T E R T 298
IXORD SELECT lm aA aB Qc qP 6-Locx cl

B.CHANNEL MULTIPLEXER WITH LATCH

(3-srATE ) 354

ef

A 2CI A2

QBQC

(D

CKI[s

Y msc

w oS 02 01 so s1s2

AT

BI

C2

D2

D] D6FD4BD2DlDODC

D2

27

(C MULTIPLEXERontinued)

WITH 8-CHANNEL MULTIPLEXER FLIP-FLOP B-CHA.NNEL ANALOG MULTIPLEXER ( 3-STATE ) 4051 356
CONTROL /+

S2

vccz703ABC

Y

w

03G2

G-t SOSlS2

2703AB

F

D5

D4 D3

D2

D]. DO CK

?

o

Il:H

D6

E

+

6

COl ,{ON7

5

y'o

,*rBITt*

MULTIPLEXER DUAL 4-CHANNEL ANALOG 4052
vcc zx rx col9oN
COI\mROL

TRIPLE z-CHANNEL ANALOG MULTIPLEXER 4053

ox

sx

?-

Ix
OY 2Y CO,r-y

co{-x

ox

3x

ccDd-Y coM-x IYC

l-x

ox

A

B

gy

fy

1NH

oY

1Z ^^-. _ oZ Ur rr-1r

I NH

12

oz col"4,,tct'l it'tHlgttwE

BILATERALSWITCH QUAD 4066

tv'o

tq,/t zo/r zy'o

28

C O U N ER T
Type Numbet
Function Equivalent LSTTL E'Cuir.'alent

civlus.
40161 40r63 *4516 40193 *1+520

Pin Number 16 16 16 16 L4 16 16 20 20 20 20 20 L6 16 16 16 16 16 20 20 20 20 16

WITH ASYNC. CLEAR 7 4 H C 1 6 1 SYNC. BINARYCOUNTER WITH SYNC. CLEAR 74HC L63 SYNC. BINARYCOUNTER COUNTER 74HC LgL 4-BIT BINARYUP/DOWN BINARYCOUNTER 7 4 H C 1 9 3 SYNC. UP/DOWN 74HC 393 DUAL BINARY COUNTER (3-STATE) 7 4 H C 5 9 0 8-BIT BINARY COUNTER/REGISTER COUNTER 74HC 592 8-BIT REGISTER/BINARY (3-STATE) COUNTER 7 4 H C 5 9 3 8-BIT REGISTER/BINARY REGISTER(3-STATE) 74HC 69L 4.BIT BINARY COUNTER REGISTER(3-STATE) 74HC 693 4-BIT BINARY COUNTER 74HC 697 U/D 4-BIT BINARYCTR.IREGISTER(3-STATE) 7 4HC 699 U/D 4-BIT BINARYCTR./REGISTER(3-STATE) 74HC4520 DUAL 4-BIT BINARY COUNTER COUNTER WITH ASYNC. CLEAR 7 4 H C 1 6 0 SYNC. DECADE COUNTER WITH SYNC. CLEAR 7 4rrc 162 SYNC. DECADE 74HC L9O BCD UP/DOWN COUNTER DECADE COUNTER 74HC L92 SYNC. UP/DOWN COUNTER 7 4 H C 3 9 0 DUAL DECADE (3-STATE) COUNTER REGISTER 74HC 690 DECADE (3-STATE) REGISTER COUNTER 74HC 692 DECADE COUNTER/nrCrSrrn(3-Sretn) 74HC 696 u/D DECADE (3-STATE) COUNTER/REGISTER 74HC 698 U/D DECADE COUNTER 7 4HC45L8 DUAL DECADE COIJNTER/DIVIDER 74HC40L7 DECADE 74He4020 l4-STAGE BINARY COUNTER 74HC4022 OCTAL COUNTER/DIVIDER. 74HC4024 7-STAGE BINARY COI]NTER 74HC4040 12-STAGE BINARY COUNTER 74HC4060 ].4-STAGE BINARY COUNTER/OSCILLATOR DOWN COUNTER 74HC40L02 DUAL BCD PROGRA},IMABLE COUNTER DOWN 74HC40L03 8-BIT BINARY PROGM},IMABLE DIVIDER/TIMER 74HC7292 PROGM},IMABLE DIVIDER/ TIMER 74HC7294 PROGM},IMABLE

LS161A LS163A LS191 LS193 LS393 rs590 LS592

rs593
LS691 LS693 LS697 LS699
L S 16 OA

LS162A LS19O LS192 LS39O LS69O L5692 LS696 LS698

4520 40150 40L62 *4510 40L92

4518

40L7 4020 4022 4024 4040 40LO2 401_03

*LS2g2 *LSzg4

16 16 r.6 L4 16 16 16 16 l_6 16

* Suggested alternative

COUNTER PR ESE T T A B LEI T C O U N T E R 4.B I 60 I6l 162 I63 DECADE, ASYNCHRONOUS CLEAR BINARY, ASYNCHRONOUS CLEAR DE CA DE ,Y NCH R O NC L EA R S OUS B I N A R Y , Y NCH R O NC L EA R S OUS sYN.4-BIT UP/DO"C0UNTER ,JN 19 0 BC D I9I BINARY
MAVfuIN

QAWOA CL cK A

@

QC

AD

T LOAD

A
6 u

cK

RcoMNT MIN

LOAD C

B

C.D

P

DOWN

CLOCK CLEAR

AB

C

D EMEE P

GND

29

(Continued) COUNTER SYNC. - B I TUP/DOWN COUNTER 4 192 BCD 1 9 3 BINARY

DIVI PROGRAMMABLE DER/TIMER 7292 FRoM b 22 231

ar{ u ru(I,^^* LvAu BORROW COI'NT COUNI UP

c D B

C

DTPS

CLRA

TP2

Q/\ uouN DOml

colrNt ^^ QD VV
UP

B

E

TPl

T cLKT CLKE

DIV PROGRAMMALBEIDER/TIMER 2 7?g4 FR 0 M 2 t o 2I 5
dffiF' NC

DECADE COUNTER DUAL (Br-QUINARYBCD) 0R 390
z-cl,deF fribcKB

TP CLKICLK2

ICLEAR B A TP OIJ(ICLKSNC Q OND

DUAL4-BIT BINARYCOUNTER 393

I^IITH COUNTER OUTPUT 8-BIT BINARY (3-STATE) REGTSTER 590

vcc eA 6 ncncrrnx-coccdilLnnd6

OA e
nP

RoK ccK ccLR CCKEN
RCO

Qc aD @r aF aG arr

QO

30

(Continued) COUNTER 8-BIT BINARY COUNTER }IITH INPUT REGISTER 592
vc A
CI,(h,D CCKBN

8-BIT BII{ARY }IITH COUI{TER INPUT (1,il'LTIPLEXED REGISTER 3-STATE oTJTPUTS) 593
ffint rcrccf,pr COrg.n nE

RcK

6-qn ccx T6-o

A

Rcr.

Ccr

e A

o,/ tl rcf,Er v@

rcr

crxgrf I c{xaN q/@

acr ocLR R0 cLm

C

D

E

F

OE

E&B

a A/eA c/ac E/aE q/@ B/tts Qr'cD F/{OF H/@

SYNCHRoNoUS C0UNTERS/REGTSTER LTITH I'IIJLTIPLEXED 3-STATEOUTPUT 690 691 692 693 DECADE, DIRECT CLEAR BINARY, DIRECT CLEAR DECADE, SYNCHROI{OUS CLEAR BINARY,SYNCHRONOUS CLEAR
RIPPLE vccNqa en ec ENABI,B ADT

HRo]r0r,s Dollr{ sYNC uP/ cor,l{TERs/ r sTE REG R
}IITH II'LTIPLEXED3-STATECI'TPUTS 696 697 698 699 DECADE, DIRECT CLEAR Btrt{ARY, DIRECT CLEAR DECADE, SYNCHR0]{0US CLEAR BINARY,SYNCHRONOI'S CLEAR
ifrfrFi=
vcc
RIFPLF

B/t sBLngt

W\EI^B

ifr

qA qB qc QD T E,m6.srragr

RCO qA

QB

S

QD BNT LOAD O

QA

QB QC

QD

F|

TI)AD

6KA

B

c

DENpRtLRRcK

DECADE COUNTER/DIVIDER 401 7

COUI{TER BINARY I4-STAGE 4020

vcc au

aro aB €

ar*Anclc*-

CARRY Q9 OUT

A{ QI2

Q8

q9

CtR

Cx

Or

ao

@

Ao

qf,

qg

Q13 Qrr

A0 as

(rt

ar

QrS QIr

a0

a5

qt

a+

oND

3l

C O U N T E( C o n t i n u e d ) R

COUNTER/DIVIDER OCTAL 4022
6IIEIE-

7-STAGEBINARYCOUNTER 4024

urocr

vcc oLEAR cr,ocr |

%mt

CLR Ql eO

CK

CE

CARtrQ4 OUT

Q7 CK

Q]

Q2

Q3

Qz

Q5

Q6

Qs

.CLR

Q?

Q6

Q5

Q4

CTOCK CLEAX Q?

I z - S T A GB I N A RC O U N T E R E Y 4040
vcc ett eto eB e9 cluen cr,odn or

I4 .S T AGE A R Y OU N TE R /OS C ILLA TOR C BIN 4060
vcc q1O e8 e9

Q]l
Q]? Q6

QlO

Q8

Q9

CLR

CK
Qf

Q5

qt

Q4

Q3

Q2

12 Q13 QI4 Q6 Q5

Q7

Q4

Q13 Q15 Q14 Q6 Q5

DUALDECADE COUNTER B 15 .| DUALBINARYCOUNTER 4520
26 28 ?Ql zQo

PROGRAMMABLE COUNTER DOL.JN 4O1O? DUALBCD 4OI03 B-BITBINARY
Eonn --' -12 vcc sPE J6

SPE

coy'o

J7

APE

c/cn CLR JO J 1 J 2 J 3

32

ENCODER
Type Number
Function Equivalent LSTTL Equivalent

cMos.
*4532

Pin Number

7 4HC r47 1O-TO-4 LINE PRIORITY ENCODER 7 4HC 1 4 8 8-TO-3 LINE PRIORITYENCODER

LS147 LS148

L6 16

* SUGGESTED ALTERNATIVE

ENCODER I O - T O - 4L I N E P R I O R I TE N C O D E R Y 14 7
OUTPUT INPI]TS OUTPUT
A

Y B . T O - 3L I N E P R I O R I TE N C O D E R 148
OUTPUTS II'IPUTS OUT?UT

D32T9 aAO
5678C8

C"S,5zi-0

567ElrA2A_t

\4

5

? I INPUTS

8__9.___9-olto OUTPUTS
INPUTS OUTPUTS

33

DECODE R
Type Number Function
Equivalont LSTTL Equivalent

cMos.
*4028

Pin Number 16 16 16 16 16 16 16 24 16 16 t5 16 24 24 16 16

74HC 42 BCD TO DECIMAL-DECODER 74HC L3t 3-TO-8 LINE DECODER/LATCH 74HC L37 3-TO-8 LINE DECODER/LATCH 74HCT137 3-TO-8 LINE DECODER/LATCH 74HC 138 3-TO-8 LINE DECODER 74HCT138 3-TO-8 LINE DECODER 74HC 139 DUAL 2-TO-4 LINE DECODER 74HC 154 4-T0.16 LINE DECODER 74HC 155 DUAL 2.TO-4 LINE DECODER 74HC 237 3-TO-8 LINE DECODER/LATCH 74HC 238 3.TO-8 LINE DECODER 74HC4028 BCD-TO DECIMAL DECODER 74HC45L4 4-T0-16 LrNE DECODER/IATCH 7 4 H C 4 5 1 5 4-T0-16 LINE DECODER/IATCH 7 4 H C 4 5 1 1 BCD TO 7 SEGMENT LlDID (LED) 74HC4543 BCD TO 7 SEGMENT LIDID (rCD)

LS42 LS131 LS137 LS137 LS138 LS138 LS139 LS154 LS155

4 5 5 6* 4 5 5 5 , 'k4515 * 4 5 5 6* 4 5 5 5 , 4028 45r4 4515 4511 4s43

*LS154,'tLS159 * L S 1 5 4 ,* L S 1 5 9 L S 4 7 *L S 4'8 . L S 4 '. *
LS47,LS48,LS4

*

t Suggestedalternative

DECODER
BCDTO DECIMALDECODER 42 3 .T O-BL INE D E C OD E R /LA TC H l3l

ABCD YOYfY2!3 l4F]6 Y']B 19

Y!

Yl

Y2

Y3

Y4

Y5

B

CCK

Cl2 01 rt

Yo

Y1 Ya vs

it

vs i6

QID

3-TO-8 LINE DECODER/LATCH 137

3-TO-8 LINE DECODTR 138 Tl 38

B

C OQA O2B Cl

Y'/

&or

oEe oae or rr

sxo

34

(R D E C O D EC o n t i n u e d ) TO BCD 451I
VER LATCH/DECODER/DRI 4-TO-I6LINEDECODER/LATCH SEGMENT

45.| 4
vcc
INHIBIT

D c sto su s8 s9 slA sl5 sla sl3

!Eaboal

IMI

D

C Slo Su

S8 89 gl4 St5 Sl2

OLTBILEDA

A

BVS6SS4SgSlSeSo

Sz sO 85 s4 Sg S1 Sa SOorO

4-TO-16 LTNEDECODER/LATCH 451 5
INHIBIT

LCD LATCH/DECODER/ BCD.TO.7 SEGMENT DRIVER 4543

INII. D

O

SI)S,1

S8 S9 SU, 815 Sl2 Lr'

fg6dob a OBDAPIIBI

A

B

S?S68ES4S.gSISASO

35

C D E C O D E(R o n t in u 6 d )

2-T0.4 LINE DECODER DUAL 139
zYO 2Y1 tt? 2Y3

4 - T O - I 6 L I N ED E C O D E R .|54

e2 0]Y15)14

flSYJzYl]

B

C D @ elu5Y14u3

Y216Y41516y/18)B YO Y] Y? Y3

lYO lYL

1Y21Y3

oND

S?EE%FrF

YrEFtuou

DU AL -T O - 4 LI NE DE COD ER 2 3-TO.BLI NE DE CO DE R .|55

3-TO-BLINE DECODER/LATCH 237

ffiF-mzfr

YO YI

Yg

Y4

Y5

Y6

YO Yl

Y2

Y3

Y4

Y5

1 c r-e

frs 1E M. ffi

eno

3 -TO-BL I NE DE CO DT R 238

DECODER BCD-TO-DECIMAL 4028

vcc

Yo

Yl

Y2

Yg

14

Y5

Y6

YSYlBCDAYS AY6 B C E?A E?B Gl Y? Y2 YO Y'I Y9 Y5 Y6

6EqifrB er

Yl
't4 Y2 YO
Y9 Y5

36

COMPARATOR
Type Number 74HC 85 7 4 H C6 8 8
Function Equivalent LSTTL Equivalent

cMos.
x 4 0 6 3 ,* 4 5 8 5

Pin Number

COMPARATOR 4-BIT MAGNITUDE COMPARATOR 8-BrT EQUALTTY

LS 85 LS688

16 20

* Suggested alternative

COMPARATOR

COMPARATOR 4-BIT MAGNITUDE B.5
vcc AS 82 A? A1 Bf Ao Bo A? A1 81 -AO BO IN

B.B IT EQU A LITYOMP A R A TOR C 6 BB
v"6 F= Q Q'/ P'/ Q6 P6 Q5 P5 QL P4

A5 B3

B2

=Q Q7 eP4

P7

Q6

Po

Q5

Ps

Q4

Ke l:
IIJ

DB DB rru,qG
IN

our. ou,r Offi Po Qo Pl Qf Pe Q? P3 Q3

ns <F r+ CASE,ADE

Ds Ds F.e(pexo
INPI'TS OIITPUTS

ADDER
Type Number 74HC 283
Function Equivalent LSTTL Equivalent CMOS. Pin Number

4.BIT BINARY FULL ADDER

ts283, LS83

4008

16

ADDER 4-BIT BINARY FULLADDER 283

Bg

AS

Zs

t+

s+ 2+

2z Bz A? Jr et nr

c4 oo

37

ALU
TYPC lhmbcr 74HC 181 7Atrc182
Function Equivdent ISTTL Equivalent

cMos.

Pin lfumber

ARITII}IETIC LOGIC ITNIT LOOK AIIEAI) CARRYLOGIC

LS181 LSl82

24 16

ALU ARITM.IETIC LOGICUNIT/FUNCTION GENERATOR LOCKAHEAD CARRY GENEMTOR l82
eT
v* Fa o? cnGu+r&+y-o c.."

r8l
ff s:I A-a ila

*:

OPFI

DRAIN

CT'TPITT

e-s Fs

d crn++i

ril

pe o? cn culr(bry

o

P}OOPOOSPS AOsg S? $1 SO cD I FO FIF?

P

ol

pl

oo

po og pg

p

(}rD

B-o fr

ss

sa

sr

so ca

n

rT

F-t F? oro

PARI TY TREE
Type lrlumbcr 74HC280 Function 9-BIT PARITY GENERATOR/CIIECKER
Equivdent I.STTL Equivalent

cMos.
*4531

Pin Numbcr 14

LS28O

* Suggestedalternative

PARITYTREE

PARITY 9-BIT oDD/EVEN GENERAToR/ CHECKER 280
Y@FEITcBA

FBDCB

&%-*

38

LATCH
TYF f.Iumbcr 74HC 75 74EC 77 74HC 259 74HC 279 74EC 375 74nC 373 74ncr373 74EC 533 74HC 563 74HCT563 74AC 573 74HCT573
Rmtio

Equinhot ISTTL

nquinlcnt

cuos.

Pln l{umber

4-BTT TTYPE I.ATTE 4.BIT IFfi?E I.ATCII 8-BIT ADI}RESSABI.EI.ATCN qIAD s-R'r,ATCH OUAI) IFTYPE I.ATCH OCTAL IFTTPE I.ATGE (3-STATE) OCTAL IFTTPE I,ATSN (3-STATE) oimr. rFTrpE LATCH (3-srATE/rNV.) ocral, rFrIr"E r.arcH (3-STATE/rNV. ) OCTAL IFIYPE I.ATCN (3-STATE/IN\I.) OCTAL IFTYPE IATCE (3-STATE) OCTAL IFTYPE I,ATCN (3-STATE)

*4042 LS75 *4042 LS77 *4099 LS259 *4043,*4044 LS279 LS375 rs373,LS573 LS373,LS573 LS533 LS563 LS563 LS373,LS573 LS373.LS573
r $tgggstcd dbrnetivr

16 14 t6 16 r6

20 20 20 20 2A 20 20

LATCH

4-BIT LATCH 75
FUil GT IO }I TABI,E ITTPUTS D LE ES XL
IQ 2Q

4-BIT LATCH 77
FUTICTIOII
IIIPT'TS

TABI,E OI'TPUTS

o

OIITPT'TS q c
LH HI,

X:DON'T CARE

D LS SE XL

G

Q,

0

X:IX)NI

T

CARE

an
2q dt.zorf) Sq

d-n
3Q

LE EL QnG (ilD xC

+q

tQ

aQcl.a

sq 1 q

Ia

ID

?DF34

gD

ID

aQ

rD

2lrg3-ll

Ycc sD aD

llc

8-BIT ADDRESSABLE LATCH

15s

qrAD s-R LATCH 279
FIIUCTIOII ITIPUTS s R TABI,E

OUTPUT

*

a
qn E L

FOR IrATCEES TIlg DOUBLE F INTUTS: rFH)Tts F TIrotS HIOE IJ:OXE OT DOTII IUPIITS I,OT

ua
LS HI,

r,

I, vo

s
rE rF rq

s32 sEr si

sq

qo (&@Q3a*qss cr?

ql

Q2

q3

(xil)

rF rEr r&

ro

aF zE 8q tlrto

39

( L A T C HC o n t i n u e d ) ( L 0C TAL ATCH 3- S T A T E ) DA T O 373 NONI NV E RT E D A U T PU T S T 37 3 LATCH QUAD 375

2
2Q Dl"
<u
'D

D3

( L 0 C T A L A T C H3 - S T A T E ) DA O 533 INVERT E D T A UT PU T S

H 0 c r A LL A T C ( 3 - S T A T E ) OUTPUTS DATA 563 INVERTED T563
&o3o?05'F.o?

( L OCTAL A T CH 3- S T A T E ) DA T O 573 N ONI NV E RT E D A I,IT P U T S T573

40

R E GI S T E R
TYpe Number 74HC L64 74HC L65 74HC L66 74HC L73 74HC L94 74HC L95 74HC 299 74HC 323 74HC 595 74HC 597 74HC 670 74HC4094
8-BIT 8-BIT 8-BIT Function SIPO SHIFT REGISTER PISO SHIFT REGISTER PISO SHIFT REGISTER QUAD D-TYPE REGISTER (3-STATE) 4-BIT PIPO SHIFT REGISTER 4-BIT PIPO SHIFT REGISTER 8-BIT PIPO SHIFT REGISTER 8-BIT PIPO SHIFT REGISTER 8.BIT SHIFT REGISTER/LATCH (3-STATE) 8-BIT LATCH/SHIFT REGISTER 4 I^IORDX 4-BIT REGISTER FILE(3-STATE) 8-BIT SIPO SHIFT REGISTER/LATCH (3.STATE) Equivalent LSTTL Equivalent CMOS. Pin Number

LST64 LS165 LS166 L5173 LS194A LS195A L5299 LS323 LS595 LS597 LS67O

*4034 14014,*402L k4014,x402L 4076 4OL94,,k40104 *4035 ik4034 *4034

T4 L6 I6 L6 16 16 20 20 16 L6 16 L6

4094
* Suggestedalternative

REGISTER 8 - B I T S E R I A L - I N / P A R A LO E LS H I F T LUT REGISTER 164
Vcc

S H IFT 8 -BIT P A R A LLE L-IN /S E R IA L-OU T R E G IS TE R 165
cLoct( v"gINHIBIt o
SERIAL INPUT

AJ{

QC

QF

QE CLEAR CIIJCX

QH

QG

QF

QE

CK INH

DCBASI ofi EFGHOH

c,1{ BQAQBAOO!

{r
clK

B . B I T P A R A L L E L - I N / S E R I A LS O U T - HIFT REGISTER 166
SEIV vcc-foAD H

(3 D QUAD FLIP-FLOP -STATE) 173
DATA EbIABI,E INPUTS

en

o

F

Eeffi-

vcccLEAR

].D

?D

3D

4D

&

(}1

HQHCFE SI CK ABcDINH. CLR CK oIJEA.R lD 2D 3D 4D

SERIAL IN

CND CLOCK INH. CIOCK

4Q CI.0CK or.rD

41

( R E G I S T E RC o n t i n u e d ) SH UNI 4-BIT BIDI RE CT I O NA L VE R S AL IF T REGISTER I94 S I 4-BIT PARALLEL-N/PARALLEL-OUT H IFT R EGIS T ER 195

qA

QB

QC

Ou "_*

tl SO

QA

eB

ec

QD 0D

oK 6

CLEAR SRABCDSL

gLEAR JKABCD

CLEAR SHIIII RIOilT

D SHIFT Cil[D LEFT

SH UNIVE R S AL IF T 8-BIT BID I RE CT I O NA L (R R EGTST E3- S T A T E ) 299 D IREC T CLE A R CLEAR 323 SYNCHRONOUS sHIFr ' --/w---'{qo^'^^cIocr flf[ffi vcc st LEFT e,, ty'on{a{

(3-S 8 .B IT SH IF TR E GIS TE R /LA TC H TA TE ) 595

vCC

-O eA SI nCr

SCLR SCX OH/

s] sL
so s

aH' ly'av nlatroo{as

cr
sR

QA sI

o

RcK ScK scLF

s/qo daadqc/a^a^'

aL
QO QD QE QF' QG QH

a

.g--&rsloo
OIITPUT CONTROLS

{qe

VAC

, r/o.l

or'sm

oNo

QB

8-BIT L ATCH/ S HI F T G IS T ER RE 597

4 WORD 670

B I T R E G I S TF IR E ( 3 - S T A T E ) EL

SLOAD RCK $(:KSCLR OH.

vcc

WRITE ENABLE SELECiI DAfA.-rD1 wa wBmIffiRffi

ouTpUTs af aP

A
B

sI sLoADRcK

scK SclJt Dl
QH,

W.e, WB

Ow

OR Q1

maz
CDEFOH

B,

D4RBR6Q4

Og

D2

D5

D4 RB.RA

-Q 4

Q3

,-t

42

(Continued) REGISTER 8-BrT SERIAL IN/PARALLEL-0uT SHIFT (3-STATE) REGTSTER/LATCH 4094

oE 8T

q5

Q6

q?

Q8 Qsl QS

roKQrQz0SAr

ou)G

gr

qa q3 qa (x|D

43

3.

OUTLINE OF PRODUCTS
3.1 Naming Method of TC74HC Series Its formal TC74HC Series Standard naming method of JEDEC.

was named by the

type

number i-s as shor^rn below.

TC74
(5) (4) 0ther sections for Package type (P or F)

Sections

(3)

Change contrr.rl symbol (blank when there is no change. ) Figures showing functions by JEDEC.

(2) (f)

Type classification (HC, HCU, HCT)

(Example) rcz+ttcT24OF
High with Input ' speed C2UOS IC which the is bipolar designed possible. type is plastic llini Flat Package. is pin and functionally compatible

74LS24O device. with TTL leve1, and direct driving from

LSTTL is Package

(1)

Hc, Hcu, HCT
In the high speed CIvlOS, HC series, the order fundamental d prevent by input HC type. the there are HCU type and HCT l^/ere decided

type

beside

These sections

by JEDEC in performance in

difference

i-n electrical of buffer even

produced

level

and existence

the case of

C M O So f

same function.

44

TyPe HC HCU HCT

Internal T\ro stages above One stage T\^ro stages above

stage and

Input threshold vol tage
CMOS level CMOS 1evel

and

TTL level

Taking these

inverter types

as an exampl-er w€ can show the

difference

of

as fo11ows.

TC74HCO4
Logic Di-agram Input-Output Vol tage transfer characteris tics

TC74HCUO4

TC74HCTO4

w
Er ir

-+"-

w

?
I

2.5V vr ll

(2)

Classification Functions In the are

of

functions by English there numerals are of two to the five,figures. product and the

expressed

case of same pin having of

TC74HC Series, connecti-on same pin

provided with

having product series

and function

LSTTL, with

connection

and fr:nction

40008/45008

standard

CD'IOS. Product function of sanp pi-n connection 74LS series and same

00 n,999

with

(Example)

74L5240 <--+74HC24O

45

4OOOq4O199 . ... 4500{4599

Product frnction

of satp pin with

coanection

and sane

standard

C}I)S 4ffiOB/45OOB series.

(Erample)
TOOO7999 .. .. . Frnction function (Exemple) '

401028 .-* 74EG4Q!O?
proper to 74HC series. ISTIT,. yith 748C7266 ++ 74LS266. buffer Eouever, sorc

approaches

Sam fincElon

Eoryener, output structure. (not open drain

is of nornal

structure.)

(3)

Change control Ttris syfrol proverent product hglish is is

symbol given to clarify remarkably Nornally, are given it the rewision of product stren inof

strLch sill "rade. characters

change the characteristics is blank, but if there

is a chauge,

successively

from A.

(4)

Partitiou English P F

for

package designator shorring type of package. p a c k a g e (D Ip) pl asti c plastic

characters .......

dual ln line flat arrow By this

. - .. .. . nini

package (l,FP) 3fi) nil-l

In 1f,748C series, newly developed. tyPe,

type 24 pfn..package nas development, in' the case of rrprt unified into 300 nill Eidrh

l4lf:6l20l24lpil;s

are all

(7 .62 rm width) . Alsor'in uaified the case of mini iito ErA"r 30o nil1 flat "Ft' type , L4lL6l20 pins are all

type package (TypE I[, Form A).

46

rn the case of both DIP and MFP types, width s o it and sarr= pitch is poss i b l e

pin arrangement

of same

is adopted regardless

of pin nrrmberr and w hen

to a rra n g e th e p a rts boJrd,

systemati cal l y

designing eas ily

the printed

and automatic

rnor.rnting can be

m ade .

(5 )

O t her par t it io n s In the case of mini indic at ion flat IC Taping specification, n a m e. di recti on) the followlng

is a d d e d to th e p a rts

f P l or - W 2 (D i ffe re n c e

i n s t i cki ng

3-2 . Feat ur es Tg74HC Series has the following standard Logic (1 ) (2 ) (3 ) IC; : Sa me a s L ST TL S a m e a s s ta ndard C InC S seri es o f d i rectl y dri vi ng (ut{) 10 LS TTL features in conparlson with other

Hlgh S peed op e ra ti o n Low P ower Dis s i p a ti o n :

Out put Dr iv e C a p a b i l i ty :C a p a b l e

l o a d s (S ta n d ard output Capable of directly l o a d s (Bu ffe r (4 ) H igh Nois e I mmu n i ty : butput

type). 15 TSTTL

driving rype).

H C C U T y p e ... /n HCT Type

45y" V C C (Typ.)

.. .. . 25%VCC (Typ.) t 2 to 6V to 5.5V

(5)

Wide Operating

Vulrage Range i HC/HCU ype ... T

H C TT y p e . . . o . , 4 . 5 (6) tlide operating Temperature Range z

-40 to *g5oc

47

(7)

Self-contai-ned

static

electricity

protective

circuit:

+2000V (min) (All inputsand Outputs) by EIAJ method (8) Ample Latch up Capacity: Total by input Total (9) (10) Based on the Wide Line up, same pin input a70mA and above (Restricted

protective

resi-stance)

output

+300 mA and above. with LSTTT..

connection

and function

and products

amounting

to 180 kinds.

Table

3-1

shows compari-son

of

characteristics

of

various

logic

famili-es.

Table

3-1

Performance

Comparlson of Each Loglc

Famlly HS-C2l0S

HS-Cal,os
Paramter

(rc74rrc) 'serles
time SnstYP

LSTTL

(1'C40H ) 'sert es 15ns tYP

c2los

Condition

Propagation delay GAIE(C1=15PF)

9ns typ

1 25ns tlp

v D D= 5 . o v
Ta = 25"C Total temper voltage

Maxlmum clock freqency J/Kr'F (C1=5Op; QuiescenE Supply Current (GAIE) VIH Input Voltage

60t'ctztYP

4SwtztyP

201'fiztYP

zyftlztyp

0.01uWtYP
3.5Vmin 1.5Vmax

SmI^ItYP 0 . 0 1 u w t v P

0 . 0 1 u W t Y P ature
range 3.SVrnin 1.5Vmax

2.OVmin 0.8Vmax

4.OVmin I .0Vmax

vDn=5.0v
Total ature temper range

vtl

48

HS-CzMOS Parameter

HS-CzMOS
LSTII.

(rc71Hc)
aer1-es

/ T e r4 e s ' \ ts C i 0H

CzMoS

Condition

Output Current

lronI
rot

46min*l 4611min

6.4,,,4min*2 4r6min

0 .36nrA mi n* 36.12r4nin*3
g.gnxlmin

* 1 V cc= 4.5V *2 YcC=4.75Y * 3 V 6g= 5Y g.36o,4min Total temperature range 3 ^, 18V -40^85"C

Operating Operating Range

Voltage

Range

2"v6y -40 ,r,85 "C

4 .7 5q'5 25Y . 0,r, 70"C

2 'r,8V -40 'r,85 "C

Temperature

4.

EXPLANATIONS OF RATINGS AND STANDARDS 4-I. MaximumRatings Regarding C MOS IC, product. In general, the rnaximumrating value should not be exceeded in of i ntegrated ci rcui t the maximumRating is regulated for each

or der t o gua ra n l e e th e l i fe pr oduc t s .

a n d re l i abi l i ty

H e re i s a d o p te d th e n o t i on of absol ute maxi mumrati ng

as the maximuur rating.

Absolute

Maximum Rating of in

should ratings excess recover

not

be exceeded not

even

for

a rnoment,

and any one standard When the unit is used

should of the

be exceeded. the case,

maximum rating, and in

characteristic permanent

will

nbt will

sonptimes,

an extreme

breakage

be caused.

In

designing to

the the

circuit,

therefore, of supply

it

is

necessary

to

pay atof and out-

tention

fluctuation ambient so that

voltage,

characteristics of input

connecting put siganl

parts, liner

temperature, the

and surge not

maximum rating

be exceeded.

49

Table

4-I

indicates

cormron rnaximum ratings of each unit As for

of

TC74HC series. differ,

When the the . refer

maximum rating shall control. 4-2.

and common rating

former to

the meaning of

each item,

Table

Table

4-L

Absolute

Maximum Rating Symbol Value -0.5 t' J

Pararneter
Supply Voltage Range

U ni t V V V mA mA mA

vcc vtu vout

DC Input

Voltage

-0 .5 '', VCC+ 0.5 -0 .5 ' \,V C C 0.5 +

DC Output Voltage Input Diode Current Output Diode Current DC Output Current

rrk
rot< rout rcc
Pp

+20 +20
+ 2 5 (Standard) + 3 5 (Buf f er) + 5 0 (Standard) Tzd (Buf fer)

DC VCC/GND Current

mA

Power Dissipation

s00 (DIP)* 180 (IfrP)
-65 ^, 150

m['l
OC

Storage TemPerature
Lead Temperature (10sec)

Tstc
Tf

300
In

oc

*

5 0 0 m Wi n to 85"C,

the range of derating

Ta=40oCT,65oC. of

the range of be applied

Ta=65'C 300mtl.

factor

-10mW/"C shall

until

50

a

Table 4-2
Pararneter Symbol Indicates the Explanation voltage range in which of IC does characteris

Supply Voltage

vcc

not

cause breakage, and fall'of

deterioratj-on reliability

istics

when voltage

impressed Indicates

on Vgg termi-nal. the voltage range in which of IC does characteris

DC Inpunt Voltage D C Ou tp ut Voltage

Vttt

not

cause breakage, and fal1 of

deteriorationreliability and output value at

vout

istics

when voltage terminals. which IC does

impressed Indicates

on input the

current

Input Diode Current Ou tp u t Diode Current

rtx ror

not

cause breakage or output

due to current

latch is in

up when input

current *

fed. which DC current of cur-

Practically, is not

the

design

flows rent value Output

recomnendable. be prevented, than this. the

When flow adopt the

cannot lower

ctrrrent

current for

indicates one output.

current

value

which

DC Output Cu rre n t Vgg/Gl.Io Current

rout rcc

can be fed

As VCC/CIUOcurrent the case of

includes

output

current, terminals,

in

IC having output

rnany output is

substantial Indicates Power Dissipation

current power

controlled causing

by it. break-

consumption IC in the entire

not

Pp

age of range

operating

temperature

51

Parameter

Sumbol

Explanation

Indicates Storage Temperature Ts tg causing of

the

ambient

temperature of

range

not and fall in the

deterioration

characteri-stic for a long time

reliability not

when left with

state Load Temperature Time

impressed the after

supply

voltage. is car-

T1

Indicates ried out

conditions IC is

when solderi-ng

mounted on printed

board.

4-2.

Reconrnended Operating This is the range in

Conditions which the operation range is is of 74HC series is is 4-I. shown

guaranteed, not

and when this even if it

exceeded, the

the operation of is

guaranteed

within

maximum rating of 74HC seri,es condition differs, of the refer

Cornmon recommended operating in Table 4-3.

conditi-on

When recommended operating conditi-on

each unit former to Table

and common reconmended operating shall 4-4. Table (a) 4-3 control. As for

the meaning of

each item,

Common Recommended Operating

Condition

74HC Type Parameter Symbol Limit Unit

Supply Input Output

Voltage Voltage Voltage Temperature

vcc vtu vout
Topr
trrtf

2c'6 0 ^, VCC
0 n, VCC

V V V
oc

Operating

-40 tu 85 0 q , 1 0 0 0( V C C = 2 . 0 V ) 0'v 500 (VCC=4.5V) 0n,400 (VCC=6.0V)

Input

Rise

and Fal1

Time

NS

52

(b)

74HCT Type

Parameter Supply Voltage Input Output Voltage Voltate Temperature Time

Symbol

Limit 4.5 tu 5.5 OTVCC O .u VCC

Uni t V V V
.C ns

vcc vtu Vout
Topr
tr tf

Operating

-40 tu 85 0tu500

Input Rise and Falling

Table

4-4 Parameter

Symbol

Explanation Indicates normal supply voltage range of guaranteeing IC. normal charac-

Supply

Voltage

Vcc

theoretical voltage

operation range

Input Output

Voltage Voltage

vrn Vout

Indicates theoretical teristic Indicates

guaranteeing

operation of IC.

and electric

operating normal

temperature

range

guarand

0perating

Temperature

Topr

anteeing elec tri.c Indicates input

theoretical of

operation IC . time

charac ter is tic rising not of

Input Time

Rise

and Fall

(,u

and falling causing

range

of

signal

malfunction

due to

oscillation

outout.

53

4-3. DC characteristics
Table of 4-5 shows DC characteristics refer to Table 4-7. of HC Type. 4-5 is from As for the meaning DC

each item,

Table differs control.

a standard individual

characteristics characteristic, regulated all units

Tab1e, the

and when it sha1l

latter

DC characteristics In

is

by JEDEC (International satisfy the this international

standards).

TC74HC series, and some items

(

standard

value,

guarantee standards. by JEDEC.

characteristics 4-6 indicates

surpassing

the international Table standardized

Table

characteristics

Table

4-5

TC74HC Series

DC Characteristics

Table

DC Electrical

characteristics

Parameter

Symbol

Test

Condi ti-on

t;

Ta = 25"C
MIN.

Ta=-40tu85"C MA X . U ni t 1.5 3.15 4.2 V

T Y P . },IAX. M I N .

High-1eve1 Input Voltage

2.0

1.5

vtH

4 . 5 3. 1 5 6.0 4.2 2.0 0.5 1.35 1.8 2.O 4.5 6.0

**Low-leve1 Input Voltage

vtt

0.5 1.35 1.8 , 1. 9 4.4 s.9
4.L3 V V

4.5 6.0 2.0 1.9

**High-leve1 Output Voltage

voH

vrN=
V1g or vtl

roH=-2ouA 4 . 5 4 . 4
6.0
5.9

I8fi::19;A0 * 6.
rol=2ouA
4.5

4.5 4.18 s.68 2.O

4.3r
5.80

s.63
0.1 0.1 0.1 0 26 0.1 0.1 0.1 0 33 V

**

Low-level Voltage

0.0 0.0 0.0

Output

Vol

vrN=
VIH or Vtt

6.0 161={41* 4 .5 IO L = 5.2 m Atr

o.r7
0.18

6.0

0.26

0.33

54

Ta = 25"C
Parameter Symbol

Ta=-40.r85"C MAX. Unit

Tesr Condirion
VIN = V1g or Vfl

I uaa
6.0

MIN.

T Y P . MA X . M I N . {.5

3 State Output 0ff-s tate C urre n t
Input Leakage Current

roz rtu

vour=vcc or GND
VIN = VCC or GND

+5.0 +1.0

6.0

-rc.1
1.0 2.0 4.0

uA

**Quiescent

rcc
Supply Current

vrN =
VCC or cND

GATE
FF MSI

6.0
6.0 6.0

10.0

20.o 40.0

Note)

*

Buffer

Type assumes 1.5

times value,

respectively.

( lrOH | = IOL = 6d, ** Items guaranteeing

7.8mA) the characteristics surpassing JEDEC standards.

Table4-6

JEDECStandard No. 7A characteristics

DC Electrical

Parameter

Symbol

TesE Condition

Vcc M I N . T Y P . MAX.
2.0
1.5

Ta = 25"C

Ta=-40185 "C MIN. MAX.

Unit

High-1evel Input Voltage

1.5 3.15 4.2 0.3 0.9 V

vtH

4.5 6.0

3.1s 4.2

Low-leve1 Input Voltage

2.0 Vtl 4.5 6.0

0.3 0.9 L.2
1.9 4.4 5.9 3.84 5.34 V V

r.2
1.9 4.4 5.9 3 .9 8

2.0

roH=-2ouA 4 . 5
High-leve1 Output Voltage

VoH

vrN=
V1g or Vtl IOH=-4mA* IoH=-52mA*

6.0
4.5 6.0

s.48

55

Parameter

Symbol

Test Condition

Ta = 25oC

Ta=-40-85t
MIN.

vcc
2.0
Low-level Output Voltage

MIN.

TYP.

IqAX.

MAX.

Unit

0.1 0.1 0.1
0.26 0.26 ]{.5

0.1 0.1 0.1
0.33 0.33 V

rol=2oue 4 . 5

vor,

VrN = V 1 g o r V1 1 I91=(nxtr*

6.0

4.s

I O L = 5 . 2 m A6 . 0 *

'-BF?:?"!;'n"t
Current
Input leakage Current

roz

VIN = V1g or V11 VOUT= Vgg or GND

6.0

+5.0

I tlt

VIN = VCC Or GND GATET/

6.0 6.0 6.0 6.0

-t{.1

+1.0 20.0 4 0. 0 8 0. 0 UA

Quiescent Supply Current

2.0 4.0 8.0
respectively.

Icc

FF

V66 or GND

MSI

Note)

*

Buffer

Type assumes 1 . 5 t i m e s v a l u e , (lrOHl=Iol=6mA, 7.8mA)

Table

4-7

Parameter High level Input Voltage

Symbol This is an input

Explana tion voltage capable of judging input rrHrt of IC as level, and the minimuu value is guaranteed. Judgement in this case is made by confirming that it is above the prescribed VOH when output voltage should be at rr11il level, and below the prescribed Vg1 when output voltage should be at 'rl't 1eve1.

56

Parameter

Symbol

Explanation This of is an i-nput voltage capable of judging is input

Low 1eve1 Input Vol tage

vtt,

IC as t'Ltt level, In thils

and the case,

maxi-mum value the judging

guqranteed. sarrn as VIH.

method is

High 1evel Output Vo1tage

voH

This minal put

is is

an output connected

voltage

when each input Vtf, so that case, output

terthe outis

to VtH or In

level

becomes rrgfr.

this of

there

guaranteed obtainable (IOtt) is

the minimum value when the flown out. specified

voltage current

output

Lo w l e vel Ou tp u t Vo l ta g e

Vol

This nal

is is

an output connected

voltage to V1g or In

when each input V11 so that case, output output there the is

Lermioutput guarob-

1evel anteed

becomes rrl.rr. the

this of

minimum value

voltage current

tai-nable is Input Current flown is

when the in. the current

specified

( rol,)

rtu

This

flowing

in

the

input input is

terminal ter-

when the voltage minal that of of IC.

is

impressed this

on the current the

Norma1ly, is

so small

measurement voltage.

nnde with

maximum value

supply

3-state Output Offl e a k C ur r ent

Toz

This

i-s a l e a k a g e when the the

current output

flowing

in

the output imped-

terminal ance, in

has become high three state

device

having

output

terminal

or open drain

output

terminal.

57

Parameter

Symbol

Explanation This is a current

Quiescent Supply Current

rcc

flowing

from is

vgg

terminal

into

IC when V6g or ing IC input,

GND level

held

without under

chang_ all rc

and the maximum value conditions allowable for

theoretical is

measured

guaranteed.

4-4.

AC Characteristics AC characteristics rn general, of guarantees input level transient waveform and rising is characteristic so set of produts.

impressed vcc-cun

as to have time of 6ns.

amplitude Table Fig. time, 4'8 4-I

and fatl of

shows the indicates 4-2

meani.ng of the output

each item connection

AC characteristics, of measuring

diagram

and Fig.

illustrates

the measured waveform.

Table

4-8

Parame ter

Symbol

Explana tion

Drawing

No.

Output R isi n g Tim e Output Fal1ing Time

trlH

Indicates put voltage

the

time during

which

the out-

(VOl, time

VOH) rises during which

from L0% to the LOZ. output

TTHL

9O7", and voltage

the falls

down from

9 0 " / "t o

58

Parameter Propaga tion Delay Time

Symbol tpLH tpHL Indicates put signal

Explana tion the delay is given time, i.e., af ter output inrewhich rr11tf the

No. Drawins HCT HC

(1)(i)

( 2 )(i)

and until

sponse is the output level, output

made.

tpLH is from the

the case in trtrrr level to

changes

and tpHL is changes from

case

in

which to 1tL" after control

rrHrf level time, the i.e.,

0utput disab l e Ti m e

tPLZ tpHZ

Indicates signal minal high is

the delay given to

a t€r-

output output

and until impedance

3 state state.

becomes

( r )( iii) time, i.e., af ter control bethe

( 2 )(iii)

Output Enable Time

t pzL tpzH

Indicates signal terminal is

the delay given to

the output 3 state ttHtt level

and until or

output from

comes rttrfr level high

impedance state. data, data indi-cates the

Minimum Set up Time

tg

Regarding time in

a certain the the

which

must be added and regarding that For inin is at a data

held, before (clock stance, rise sary clock of input,

input

etc.)

changes. is read it the

when the next

data

(1)(ii)

( 2 )(ii)

clock

pulse,

necesof

to add data pulse,

before

rising of ts.

maximum value data, data

Minimum Hold Time

rh

Regarding time after in

a certain the

indicates

the even

which input

must be held that data

the

regarding etc.)

(c1ock input,

has thanged.

59

Parameter
Minimum Rernoval Time

Symbol

Explanation
Indicates leasing set next of the minimum time, asynchronous etc.) input i.e., after re preof

Drawing No. HC HCT

t r em

(cJ-ear,

input,

and until input (clock,

receiving etc.) width at

operation the

Minimum Pulse I^Iidth Max. Clock Frequency

tw

Indicates ilock signal.

minimum pulse etc. is

which

(1)(ii)

( 2 )(ii;

input,

accepted

as a normal

fuRx

Indicates IC carries

a limit out the

clock

frequency

at

which

normal capacity

operaiton. between input and

Input Capacitance

ctu

Indicates GND.

F ig.4 -1

O ut put Conne c ti o n D i a g ra m.

vcc

Meaeur i ng Point

To Outqut Terminaf Measurins Point

To. output Termi na 1

CMOSOutput

r'"
vcc

Open

Output

i.ieaeurinr4 Pornt

i'o output Termi na L

s1 J

I

T
R. L -' -

Note)

C1 contains

the

capacity

of probe, etc.

L
3 state

T

cL
output

1""
60

Fig.

4-2

S wit c hing C h a ra c te ri s ti .c s

T e s t l rl aveform

(1)
i.)

H C TyPe tTLH, tfiIL, tpLH, tpHL

t1 I NPUT

6ns

90%
50|/a

vcc
GND

trul

ro%

]NVERTING CUTPUT

voH

ii)

twr

t",
t,1

th,
6ns

trem
6ns

CLOCK INPUT

eo% o.%

vcc
C}ND

DATA INPUT
ttHl

vcc
50%
GND

OUTPUT

voit vot

S E T, R E S E T oT PRESET

vcc
GND

61

iii)

tpLZ,

tpl/.Zt

tpL,

tpZJ/.

tr CUTPUT DISABLE

6ne

t1

6ns
Vnn

50%
qND
f

*PLZ

O U T P U T :L O W TO OFF

v6H(4ss ) vor, vott

i'iir n rtmnrrm nrr vUIrUl.-t:l-L\t.rl

TO

OFF

v61(4No)
OUTPUTS DISABLED

OUTPUTS
ENABIJED

( 2) i)

HCT T y pe tTLH, ttttl, tpLH, tpHL

ty

6ns

INPUT

INVERTING OUTPUT

62

ii)

twr

t"t,

thr

trem

6ns CLCCK INPUT

3.0v

GND

trr(l)

&ov
DATA INPUT
GND

von
OUTPUT

tpul

vcl

&ov
sET,RESET or PRESET GND

iii)

tpLZ,

tpHZ, tpZL,

tpZll

tr

6ng

t1' 6ns 3V

OUTPUT DISABIJE

GND

\pzr von(lvcc )
OUTPUT: IrOW TO OFF

vor, tpzu vott

OUTPUT:HIGH TO OFF Vol(:<clll) OUTPUTS OUTPUTS

63

5.

How TO READ LOGIC SYMBOL AND TRUTH TABLE
5-1. How to read Logic Symbols

Table rc. data the

5-1

shows the basic chart is

logical printed

block in

used in

high-speed technical

CMOS

The theoretical of each product This

individual

composed of chart is

the- basic

block

shown in

tab1e.

logical

based on MIL-STD-806B, and gate. employ specific symbol.

clocked

inverter

and transmj-ssion

Table

5-1

Basic

Logical

Circuits Logical Equation or Truth Table

Logic Inver ter

Symbol

A=>r

B a--o)-n

NAND Gate

f-D,'$=Nn--c

c f; _D-c
$ €-c

C=A

B=A*B

NOR Gate

C=A*B=A

AND Gate

fi{F-c

t _D*c

A+B

i-Dci-5o_c
Clocked Inver ter (Note 1)

A-.8

a*fo

. td

B A --Xtt

Ld-

6
H H L

A H L

B
L H

X: Dont t Care Zz High Impedance

X A
H L

Z B
H L X: Dont t Care Zz High Impedance

Transmission Ga te (Note 2)

A

-#F'
t6

F

6
H H L

X

Z (A+B)

EXCLUS IVE-OR Gate

A B

:fD-c
64

C= (A+B)

Table Circuit

5-1

(Continued) Logic Symbol Logical Equation or Truth Table

Function

EXCLUSIVE-NOR Gate

$ :1f>-.
S H

c=(a.B)+(A.B)
R
L H L L

D

D-Type Fl i p Fl op

a a

x
X
H L

L

CK X X

a
H L H

X: Dodt Care A: No Change

L
L L S H

-r
K X X
L H

L R
L H L L L L L

X
J

.r -t-

L QnA CK X X

a
H L

L J / K Typ e Flip Flop J CK K

X X
L L H H

aJ
-cK aK

L L L L L

-|-

qnA
L H

L
H

_r -r
_r

x

X

-l_

Qnv
QnA

x
A V

Donrt Care No Change Toggle

Note 1)

Clocked Clocked Fig.

Inverter inverter In ha3 the this figure, circuit shown in

vcc

-s

5-1.

Ql and QZ are

o-1

'

P-channel ll-channel nected in

MOS FET, and Q3 and Q4 are MOS FET, series and four FET are GND. all con-

"{

from Vg6 to

s*1
If 6 signal

i-s at

rr11rr level,

Ql and Q4 turn

oDr and can b e regarded composed of

as a mere inverter Fig. 5-1 Clocked Inverter

Qz a n d

Qf.

65

When I

signal

i-s atrT,ftlevel, of the condition cut

both of off

Qf and Q+ turn the output

off,

and

irrespective high That cut

A i-nput, from both

B becomes

impedance is off to ssy,

condition clocked

Vgg and GND. as a switch to

inverter

can be applied

input

and output,

Note

2)

Transmission Transmission in this figure,

Gate gate has the circuit s h o r n r ni n MOS and rN'/our Qf Fig . 5-2. As shown

Ql is

P channel I.OS FET, para1le1.

FET and QZ i.s N channel these If are connected is on, either at in

vcc

z
. l

d signal

"H" level,

both

cuT,/lN

and QZ turn given from

and a signal direction.

can be Further,

Tn.
/ Gllr)

if

6 s ignal

is a t ttl tt l e v e l ,

b o th Q1

Fi g.5_2

Transmi ssi on Gate

and QZ turn off , and a si-gnal cannot be passed.

5-2. How to Read Truth Table Table 5-2 indicates Tru th T able. Table 5-2
Synbol H L High Level Low Lerrel Indicates (Indicates (Indicates leading Explana tion stationary stationary input input from or or output output level) level)

the explanation

of symbols described

in

-J-

edge changing

ftlrr to

rt11rr.

66

Symbol

Explana tion Indicates
Donrt care

-1_
X

trailing
(nither

edge changing
ttHtt or ItLrf)

from

"Ht' to

ttlrt

z
a....h

High Input

impedance level of

state stationary state of each input of input of A to H. condition

Qo Qn

Level of indicated

Q just before the in Truth Table.

realization

Level of Q just
One tlltt leve1
One ttl.tt level

before inputting

of active

edge (Jorl_l

.

JL

pulse
pulse

Lf

6.

COMMONELECTRICALCHARACTERISTICS
6-1. (1) Supply Current Characteristics current the condition in which FET or input is

Qui-escent supply In the case of at tT,tt off. from

CI'{OS, under ttHt'level, For this

fixed

or,

either reason,

N-channel the current

P-channel

FET turns following saturated rent

Vg6 to of

GND becomes only PN junction of chip

the reverse-direction surface leakage cur-

current

and the

due to of

the stain less than

surface nA at

alone,

and becomes the

current

several

room temperature.

(2)

operating

supply

current current the of high speed CMOS fC can be ttatt and rrbrr.

The operating considered

supply

as the

sum of

following

67

rrafr

The switching capacity ci-rcuit added

current to the

to

charge output

and discharge when the

each in the

gate

gate

including

output

buffer

makes inversion.

tt6rt

The through N-channel turn

current FET which

flowing eonstitute at the

when P-channel gate during

FET and inversion time

on transi.ently

same time.

When rise 6 ns) r in

time

and fa1l current with

time of

of

input is

signal

are

small

(about small the of

through

gate

usually For

negligibly the reason,

comparison

switching current is

current. governed

operating

supply

by internal of load

capacity capacity.

IC And charging By obtaining of the the the

and discharging total

current

sum (Power Dissipati.on as a load to the

Capacitance:CPD) operating in

capacity

connected

gate

ci-rcuit,

the mean operating

supply

current

can be decided

as follows:

IOO (opr.)
For.the inversion of

= fin.CpO.VCC
gate it is output from low level that the to

(6-1)
high level, charge from

necessary

electric supplied

vcc

corresponding

to CI.VCC is

corresponds supplied period.

to

the mean current Vgg line to

to be that

from

IC during

68

rn the actual and their

rc,

operating

gate exists

in plural

number, frequency as rc i s

respective

load capacity

and inversion

a re dif f er ent . a s f ollows :

T h e re fo re ,

o p e ra tl n g

suppl y current

rno (opr) = VcC.lrrr.ar'
As fn (.fin1 , is certainly gate as above ai.ri"ible operating with of by integer fn/m of input frequency

the

frequency

can be considered

equivalently Hence, the

rhe capacity equation

+. can be developed

as

Ioo (opr) = VCC.fin.i C*
Im

rn equat ion

( 6-1 ),

th e fi n a l

i te m i s defi ned as cpD .

Here, cpf and rcc as an example-

(opr)

are obrained by raking diagram at

TC74Hc74p

connection

the measurement

and it is assumedthat 265ttl was obt ained i n th e m e a s u re d rc c (o pr). rn thi s case, CL = 0, and IC C i s n e g l i g i b l e .

time is shown in Fig.6,

Thus, from the above equa tion, ^ *P D= U_
Cf,n
f:] rrdHz f

rcc (opr.) @TffN

.trrt CK D

E -

s' (T;107

265 x 10-6

z
Fig.

= 53 (pF)
6-1

69

Nex t , by V CC = 5 V , fIN = 8 MH z , C P D = 53pF (ti si ng gnl y one c ir c uit ) , I C C (o p r) a t only) th e ti me o f load capaci ty as follows: C tr =

50pF (Q output I C C( o p r . )

can be obtained

= CpD'VCg'fin * Ctr'Vgg'fOUT = (53x 10-1t).5. (8 x 10u)+(50x10-r2)
.5. (4 x 106) = 3.I2 (mA)

As Cpp under separate for data

standard sheet,

operating operating

condition supply

is

described

in

a

current

can be calculated

each unit

separately.

However, lation, by it

in

the

specific

application current

such as crystal characteristics result

oscil-

becomes supply current,

controlled by Cpp cannot

through

and the

calculation

be used.

6-2.

Output

current

characteristics characteristics type of TC74HC series type. can be

The output devided into

current

standard

and buffer

IC of

standard

type

is

capable

of

directly

driving

10 LSTTL, temper-

and guarantees ature dri.ve range.

VOO-VOU:0.37V, Alsoi in buffer

VOL-<0.33V in type, it is

the entire

possible

to directly

15 LSTTL under

the

same conditions.

70

Fig. each

6-2

shows the

standard the

output supply

current voltage

characteristics of 4.5V.

of

type when used at Fig. 6-2 output tics

Standard current

Output

Current

Characteri-stics current

High level characteris

Low level output characteris tics

output voftoge -3 -2 ..1

VgH-Vgg(V) 0
Pa

d< 9E
H . v

p^ c{ tv ;J 5 .Y C)F P

AA

ta:?fc(TYP.
q.n

)

. - I U^

! .{ OFI P

E /\

-20 Ta:gb'C( MIN. )
-tn -"

P'
P

p20
FI

o
d 0)

1a:g5l(MIN.
-t o q) r-l ]n

)

o
_l

-40 Ta:zb"dtyp. )

s u ,.1

012IJow level

output

345 voltoge

VoL(V)

(i) High level output charac teris tics
Iiqh feve-loutput

Standard

TyPe Low l evel output charac teri sti cs
ta:a

current

current

voftoge

Vog Vgg(V)
P,^

s"C( t ..p )

0 .10 20

i< oE
lrv

+:{ F E tn
OvE" tFJ

OH c) P P Jon P P

--

1a:35'Q(

MI N )

._an
-l 0)

"10
-1 c)

|-'
'1a:2 5lQ( TYP

>o o-

e1

VgC:45V

b0 +

F '-l

Low

Ievel- output

vol-toqe Vg1(V)

(fi)

Buffer Type

71

(trtote)

Solid actual

line case,

shows stanilard there is

characteri.stics depending line

chart.

In

the

a variation the broken design.

uPon the

samples, standard

and so, values

adopt

and separete

when making

When the in

structure

of

device

is

decided, voltage

the

current

flowing VDS

MOS FET is source

determined and drain.

by gate

V6g and voltage

between

In

the

actual

IC,

the

gate

voltage

of

output if

step

IOS FET be-

comes nearly considered, saturation

Vgg or the zone3

GND level.

The.refore, is

IVCSI = VCC is in rion-

following

equation

realized

.
If, Vpg is satura

ros = ( 12Vos (vcs- vr) -vos2l
made constant, zorJle , IDS is proportional to Vgg-V1. In the

tion'

IoS=f(VCS

.-Yy)z

t

Th u s , it is

is pr op o rti o n a l voltage

the threshold

' to (VC C V T )2 no t by . _VDS Here, V1 pfoper to I-{OS T, and i s set at a FE

v.a 1 ue of , about 0 .7 V i n T C 7 4 H Cs e ri e s . 6- 3 s hows su p p l y v o l ta g e - o u tp u t c urrent T h i s fi g u re

Fi g .

characteri sti cs

o f st andar d t y pe o u tp u t. No te t hat t he v a ri a ti o n

i ndj -cates standard val ue. at the ti me of l ow that at the

o f o u tp u t c u rre n t

supply voltage time of 4.5V

becomes large

in comparison with

72

vgg-vsH
5432 Ta: 5t

(v)

vcc:2'ov _2.5v =
3.rr v

s,sv
H r.f o
H

'r

l-

4 .ov#
4.5

v -1/

I

5.OV (5.5V

4 I
7
/

7;:

r

-10 -20 -30
tl

-40 -50 -60 -10

rl o H

^/
Vg6:2.0V
6.OV

-0L2345 vol, (v)
Ig1 Characterietics Igg Characterietics

F ig.

6- 3

S ta n d a rd O u tp u t C u rre n t C haracteri sti cs

6-3.
(1)

AC Electrical
Supply voltage

Characteristics
dependence

T r ans ient

c h a ra c te ri s ti c s

o f rc s u c h as propagati oi i del ay ti me time

and maximum ope:ating of inner gat e o r ri s e

frequency are determined by delay ti me a n d fa l l

ti me of output buffer.

Internal of

delay

is

considered of

to be chiefly

due to but

intepfal as the

effect

on resistance capacity the drain

MOS FET and load remarkably

capacity,

internal voltage, the

does not current of

depend upon supply of MOS FET determines on supply

characteristic

dependability

AC electric

characteristics

vol tage . Fig. tion 6-4 shows the dependability delay time i-n a representative

on supply gate

voltage

of

propaga-

IC.

73

In is

JEDEC, the decided the

\

coefficient

of

dependability standard. in Fig . In

on supply the worst

voltage case,

as follows broken of line

as the indicated

adopt on the

6-4 which

was made

basis

JEDEC standard.

Table

6-1

Calculation (excepting

llbthod ft"tRX)

of

AC Standard

Value

vcc
2.0 4.5 6.0

Ta = 25"C

Ta = -40 't,85 "C

5.00x

5.00Y Y=1.25X 0.85Y

x
0.85X

Table

6-2

Calculation

Method of

fUeX Standard

Value

vcc
2.0

Ta = 25"C

Ta = -40 n, 85 oC

0.20x X 1.18X

0 .20Y Y = 0.80X 1 .18Y

4.s
6.0

R

-l d

lr

t\
I

o
4J <dz -l CD tr

\ \
I

p<!

h. xa
\
ts.

_-

---

I . F i g . 6-4 Dependabilit y

t ,oint"

..roorro*ruur.cul

o n Su p p l y V o l ta g e o f P r opagati on D el ay Ti me (Gate IC ) 74

(2)

Load capacitance

dependence

rn TC74HCseries, comparison with ""p""!.ty
Howeverr is or

output

current

has been widely

improved in and

the conventional

40008/45008 series,

load can be driven

at high speed.

4s output rise

impedance time

is

decided time

when supply of in output

voltage

determined, propagation of

and fall

waveform, to an

delay

time will

increase

proportion

increase

load

capacitance.

Fig. rise Fig. delay

6-5

indicates

the

load

capacitance supply voltage

dependence of of 4.5V,

output

time and fal1 6-6 shows the

time at load

while propagation

capacitance

dependence of

time.

Standard

Type

Buffer

Type

3,zo
Fl t-r P d |T1

Ezo
Fl F{ p

dts 4J to U trq)
C0 .d .Fi P ii

sr €10
dF

U
.-ll @ .,-r l.

P

.'+ P

U qP F I

Pc u

U 0

0

Oq{

50 Lood Capaci ty

100 Cf, ( pF)

F.: i i UH

15'A

0

50 100 Lood capacity cL (pF)

Fig.

6-5

Load Capacitance of tTltt, TTIIL

Dependence

(s ta n d a rd c h a ra c te ri s ti cs)

75

Standard

$pe

Buffer

Type

.d P

E

ID

rl P

o E >o rt Fl

>o alc €E! A g+t
o..r !E P>l .tA QP at A o t{ ft
OFI

OFI dE A H+t

3t A 5 .
or5
a, A o k

Ioad. capactty

rcT

*
(1,t)

50 Load Celnclty

100 C1, (pF)

Fig.

6-6

Load Capacitance Dependence of tpLH' tpHL ( s t a n d a rd c h a ra c te ri s ti c s ) o

In

TC74HC serLes, is

AC characteristics Therefore, than

of

50pF during ProPagatlon is

load delay time by

capacitance during the load

guaranteed. other

capacitance eqr:ation.

the above

obtained

f ollowing

(Example)

High

level

propagation of XpF.

delay

time

in

the

case of

load

capacitance

tpln

(x)

= d

(X -

50) + tpLH (50)

A:

I{igh per

leve1 unit

propagation

delay

time

increase

rate

load

capacitance

(ns/pF)

76

Table

6-3

Load Capacitance Characteris tics

Dependence (ns/pF)

of

AC Electrical

Sta n d a rd O u tp u t
Tlpical

Buffer Output
Typd-cal vaLtre (Ta = 25"C)Limit value (Ta = 85'C)

( T a= 2 5 ? e ) 0.33
tttH, tTHL

va1rc

Limit value (Ta = 85'C)

0.83 0.24 0.16 0.43 o.L2 0.77

0.22 0.08 0.06
0.13 0.05 0.038

0.55 0.16 0.11 0 .33 0.10 0.068

o. r 2
0.09

tpt fi,

tPHL

o.L7 0.96 0.043

Table

6-3

indicates

increase

rate having

per load load,

unit

capacity

of

AC

electrical In the

characteristics

capacitance it is this

dependence. to make

case 'of h e a v y c a p a c i t a n c e by using the limit

necessary table.

calculation

value

in

6-4.

Temperature In

Parameters

of

Various in

Characteristics a wide This are temperature chapter range of

TC74HC series,

3D operation

such as -40 switching

to 85"C is

guafanteed. current

shows how the by temperature.

time

and output

influenced

(1)

Temperature Fig. In in 6-7 this

Characteristi-cs

of

Output

Current output current.

indicates figure,

temperature line

dependence of

solid

shows the at

temperature time of case.

dependence designing, use

standard

sample. line

Therefore,

the

the broken

indicated

as the worst

77

t_40 1?0 100

VCC:45V

rour
N
o
4J

140

V6g45V C1 :5OpF

AIOUT:_:XLOO f orrn( Ta:Z5'C)

N
F{ P o

120 ltnd: 100

tPd tpd( Ta:P5"C)

80

80

io

-20

?0 Ta Fig. ("c)

40

A.r

100

-40

-20

0?040 (") ra Fig. 6-8

100

6-7

(2)

Tmeperature Fig. time. ature 6-8

Characteristics

of

Propagation

Delay

Time delay temper-

shows temperature line in this

dependence of figure At indicates the time

propagation standard of

Solid

dependence at

Gate IC., line

designing, case.

therefore,

use the broken

indicated

as the worst

7.

PREcAUTIONS IN HANDLING
7-L. Electric Static Discharge thin to gate this insulation gate the oxide film. (input of When high CMOS IC), breakdor^rn resistnace to protect circuit

CI"OS IC has very voltage oxide i-s applied film directly In are from

electrode

under

gate

causes dielectric Fig. in 7-L, order

sometimes. and diode CMOSgate may not voltage,

TC74HC seriesr added to all

6s shown in terminals

input voltage.

such high

However, against in

protecti-ve

necessarily care

be effective ful1y taken

accidental it.

high

must'be

handling

78

Futher,

8s parastic

diode

is

formed

vcc v cc -

between in Fig.

each termi-nals 7-L, thermal

as indicated and

breakage

Input

I 1
t1
*
-J
ND GND

latch
Output

up due to

excessive

current

may sometimes voltage applied

be caused when the the ratings is

exceeding between care

each terminals. must fu11y assembling be taken and

Therefore, at the

ti-me.of

adj ustment. Fig. 7-L Input Protective Circuit, Note) As input protective poly of silicon 400f1

Output

Equivalent

Circuit

resistance, resistance is used.

20O to

(1)

Electrostatic Fig. 7-2, 7-2 test

Discharge

Test

Method discahrge test method In Fig.

shows electrostatic j-s conducted Table of test with 7-L

C = 200pF, R = 00. shows the static plied results

electroap-

Vnn

discharge

to a r.pr"""rrtaEive

t y pe of T C 7 4 H Cs e ri e s .

_ola

^?f-

Input or Output

vt
L
+200V an

|

|

GND

I n- t he t es t

o f th e a b o v e

TT
t

m et hod s t an d a rd i z e d b y E IAJ ,
it will is acknowledged practically service that

withstand condition.

Fig.

7-2

Test Cireuit
7-L Toshibats

ordinary

As shown by Table

TC74HC series

has ample capacitance.

7g

In p u t
Name Impression * voltage of Impression - voltage of

Output Im pressi on of * voltage Above 1000V Above 1000V Above 1000V Above 1000V Above 1000V Above 1000V
frequency Impression of - voltagd

TC74HCOOP TC74HC O4P TC74HC 74P TC74HC1 38P TC74HC24OP TC74HC37 3P

300v 400v 300v
450V

-300v
-350v -300v -350v -350v -350V
R = 00, 7-L

Above -1000V Above -1000V Above -1000V Above -1000V Above -1000V Above -1000V
three times

350V 350V
C = 200pF, Table

Impression Result

Test

7-2. (1)

Precautions

in

Handling and Storage terminals they of are body, it"is unmounted apt to CI'{OS IC are in the

Transportation As input state from of the

and output high

impedance,

receive

induction field, and

surroundipg For this them to so that

chargep reason,

space electric necessary mat, of metal in

human body. and storing num foil potential. box,

transporting alumisame

use dielectric each terminal

case or

IC may become at

As TC74HC series treatment the or at the

is

inserted of

in

a maga zine do not

given take it to

no-charging out from

time

shipment,

maga zine vinyl

unnecess arLLy. which is

Especially, apt to charge

avoid static

use plastic electricity.

container

80

(2)

Assembling I^lhen installing to protect static the C M O SI C o n t h e p r i n t e d electric equipment, by.making stand board, it is necessary

working grounding.

stand It

and operators is advisable or alumibe an

from to

electricity the working

ground

by spreading of l

metal operators

plate

num foil

on the the

surface. resistance It

Grounding of about

should

made through electri-c metallic not it

Mft so as to

prevent through advlsable

shock. ring or

j.s convenient

to make grounding Also, it is

metallic clothes

watch band. make of

to wear working is necessary

chemical

fiber.

Further, to

to periodically electric

check electri-c

equipment

insure

absence of

leakage.

When shaping advi-sable not to

the

lead

wire or

during similar

the jig,

packaging so that

of

IC,

1t may

is

use pincet to the root.

stress

be given

l,lhen stori-ng board, short

or

transporting the

the

completely of printed so that

assembled board input or

printed cover

circuit board with

termi.nals foil,

the entire of

aluminum

terminal

IC may be opened.

(3)

Soldering, I,rlhen making out

washing so]deri-ng the by using temperature that soldering of lron and tank, carry 10

the work at It is

260"C or below within of TC74HC

seconds. series stress is to

confirmed affected of

the reliability

never the

when subjected lead at

to a temperature 10 seconds. end. It is re-

stopper iron

260"C for at its

Use a soldering commended to exceeding

having iron

no leak having

use A class

insulation

resistance

10 M0.

81

When using so as to

soldering the

tank,

it

is of

necessary soldering

to make grounding tank from becoming

prevent

potential

unstable

After

soldering etc.

IC on the printed For this

board, is

cleaning used flux

i.s made to removing Care so at CMOS IC.

remove flux, abluent or

cleaning

cleaning taken effect is

method utilizing for the selecti-on to to the

ultrasonic of this

wave. solvent

must be ful1y to In prevent general, the it

given

packagg

and mark of

advisable

use Freon

series.

In the

the

case of

ultra'sonic

cleaning,

it

is

necessary

to prevent

stress

due to resonance For that this

from being it is

imposed on IC or needed to consider a such

printed washing vibrator,

board. method

purpose,

the main body becomes a shade against a cleaning time of less than

and also

30 seconds.

(4) .

Adjustment, lrlhen making printed soldering

Test adjustment board, or and it test is af ter the to completion of of

circuit bridge

necessary printed

check absence board before only

crack

on the

switch-

i-ng on supply supply current,

power. it is

As CMOSsystem requires well to apply current

small when

limitation

uraking test

by using

marketed

constant

voltage

pohTer source.

Inlhen mounting from hand. the

and dismounting never fail

printed to cut off

circuit

board

on and before-

socket,

power supply

82

lrlhen surveying the of test, probe is care with

each

part

of

printed taken or

board

with

probe contact

during of tip

must be fully other si-gnal

to prevent

poT^rer li-ne. it is

when surveying to erect a

place special

previously test pin.

determined,

advisable

When test aturer ature ma terial it

is is

conducted necessary and the

under to

high

temperature of

and low constant in the

tempertemper-

take set

grounding

oven, .

inside

must be on or

inhuctive

This single

item

excepting is

one part,

is

also

applicable

when CMOSIC

trnit

tested.

/ 8. PREcAUTIoNS DESIGNING IN cIRCUITS
8 -1 (1 ) I nput P r oc e s s i n g P r oc es s in g o f u n n e c e s s a ry g a te I nput of C MOSIC h a s s o h i g h i mp edance that l ogi cal bec om es u n d e rfi n e d
input the is at

l eve1 case, i f

u n d e r o p e n c o ndi ti on.
level, p-channel

In thi s

internediate of both

transistors

and N-channel state, current

becorne continuity supply

and unnecessary flows.

Therefore, be sure input input 1evel to

as shown in connect

Fig.

8-1,

unnecessary other Fig. 8-1 Treatment of Input

line

to VCC, GND or

and output is decided

whose logical

83

rn t he c as e of c M o s , i f fu n c t ion ca u s ed.

s o l d e re d p a rt has bad contact, will

mul be

of s y s te m o r i n c re a s e o f s u p pl y current T her e fo re ,

c a re mu s t b e ta k e n at the ti me of w i ri ng.

(2)

Input

processing

of

printed of

circuit circuit

board board is connected

trlhen input directly is brought

terminal

printed

to CMOS input, to electrically the

CMOS input floated IC or printed

condi-tion single stored board. to

as in

case of

unj-t

when transported uni.t of

as a single It is

advisable, to in

therefore, VCC or GND

connect

previously

through circuit

resi-stance boardr

the printed in Fig. ;of
F::lookf}

3s indicated

Fig. 8-2.

8-2

Input processi ng ci rcui t board

pri nted

8- 2

D e sign of P ower S o u rc e
trn general, pari-son with only srnall cMos requires other bipolar -srnall digital consumption rc, current in it comneeds

and therefore from its and of

capacity

power supply.

However, spike

operationaltherefore 'pohrer

requirement, it is

cMoS consumes poh/er in to keep high

state,

necessary at

frequency

impedance

source

low level

rt

is

adviasable thick

to make wiring and short, once 0.01 IC.

of

power source insertr

(v6g)

line

and GND line frequency ""a GND for

and to gF to 0.1

eis high between V6g

fliter, each

ttF capacitor

84

Also, to

it

is

recommended to insert power supply current of of

a condenser

of

about

10pF frequency

100uF between

entrance

and GND as low differs of

filter.

As rRean supply frequency and falling

considerably existence

depending

upon operating load, risi-ng

system, input

condenser

signal

and supply specially

voltage, given in

attentj_on the case of diode, is

must be simple

poT^rer source driving. or of that

by Zener

oE battery

.tlhen there

overshooting transient etc, time so be Fig. 8-3 Example of in driving capacity

urtdershooting supply the

during

pourer, use filter maximuri rating

rnay not

increase

exceeded.

8-3

On Output rn

Short-circuit buffer is added to (IOf,) current shorted with the output, driving in and both are possible. when

Tc74Hc series, (IOH) reason, output line

flow-out . For this

and flow-in excessive line is is

current flows with

C IvXCSutput o or frtrrf

f r 1 1 r re v e l l level:output when the is

GND line

shorted is

Vgg 1ine. arlowable

particularly, loss care of package

supply

voltage

high,

exceeded by this cause output

current, short

and therefore

must be taken

not.to

circuit.

:
It i s of c our s e i m p o s s i b l e to d i re c tl y connect ordi nary output, outputs to g e t her , but in th e c a s e o f rc w h i c h h as 3 state provided

wired OR ls pernitted

that more than two outputs

d o n ot bec om e en a b l e s i mu l ta n e o u s l v .

85

Further, to connect

in

order the

to

improve in the

driving

capacity,

it

is

possible Fig. E"'3.

gates

sane package

as shown in

8-4

Effect

of

Input

of

Slow Rise of is slow imit rise

Time and Fall

Time

When the waveform ti.me or pressed times tends fall to time

F/Y

I

FA_Z

CMOSinput, that

some-

happens to

output around of in is circuit) the case
CIJOCK

oscillation voltage waveform IC. This

VtU
CLOCK

(threshold of of input gate

because ampli-

CMOSgate fier ity

becomes linear in

Qt i-r

equivalently of VtU, ripple

the vicinpower compooutCLOCK

tl

and minute and noise in

source nent put

(a) Normal operating

waveform

are

amplified

the

and appear.

V11C1

v11c2 For the purpose it is of preventing to (b) nr

the above, insert high

necessary filter

n,
Malfunction at the time waveform from of VthCl>Vs6C2

frequency

condenser of

between IC,

VCC and GND or to use

oscillating trigger case of

Schmitt In the

IC. TC74HC series, Schmitt rising and as

CLOCK

V 15C2 V15C1

nt

excepting trigger falling shown in

HCU type, IC, time inpu.t is

n,
(c) Malfunction at the tire waveform from of VthCl <V16C2 Malfunction

regulated 8-1 in the

Table

recommended operating Eions. Please fo1low

condi-this

Fig.8-4

Example of

condition.

86

Fig.

8-4 shows an example of by using

malfunction of

when shift another to be level

counter

is

constituted In this

type D flip-flop is of f1op.

package.

case,

malfunction

considered circuit

caused by the difference respective D type flip

threshold

of

Now,let of F/F-2

circuit

threshold

level

of F/F-I Fig.

be V56Cl, and that 8-4, clock time dif ference pulse cuts

be VttrC2.

Then, ds shown in the rising

,\t is

formed while

waveform of voltage,

the respective takes place.

circuit

threshold

and thus malfunction

The fo1 lowing c:ondition operation:

is

required

for

insuring

normal

ht < tpd In this case,

(Cf - Q) + tset-up there signal ir is a possibility within of malfunction value of even Table 8-1.

though input Therefore, clock

the standard taken for

care must be speciallv

sequence circuit

input.

Table 8-1 I tem

Standard Value of Symbol

Input

Rising Limit

and Falting

Time Uni t

Inp rrt Ri sing and Falling Time

tr, tf

= Q r, 1000 (VCC 2.0V) = 0 '\, 500 (VCC 4.5V) 0 = tu 400 (VCC 6.0V)

NS

87

8-5 (1)

Precautions Output

for

hliring distortion TC74HC series is considerably ql4OS IC, low in

waveform

As output comparison is

impedance of with the

conventional in the output

standard waveform

distortion upon L end line

sometimes

caused wiring,

depending

component of is long or

when the wiring is line

connected

to output signal

when capacitance between the signal

connected and GND.

between

and VCC or designing wiring board, less.

Thereforer'when to make signal side to printed 30cm or of

printed tbo ideal

board, In

take the

care

not

length it is

1ong.

case of wire

both

to limit in

signal

length line,

Especially, causes

the clock

signal

distortion

waveform

malfunction

(2)

Precautions Output of

for

arrangement has quick rising and falling time,

TC74HC series swing at

and makes ful1 source it of other

VCC-GND, and so it Therefore, which is it is

becomes a noise desirous to locate

signal,.

separately circuit.

from a part Also,

sensitive for

to a noj-se of the reduction

analog of load

care

must be taken of wiring

number and curtailment

length.

(3)

Termination From j-ts physical apt to and electrical factors, TC74HCseries and this IC. is leads These the

cause overshooting of circuit

and undershooting, or breakdown of to some extent 8-5 indicates

to malfunction troubles end of

passive by

can be prevented signal line. Fig.

terminati-ng

examples of

general

termination

88

T t
(a) Termi-nation by C R (b) Termination by' Diode

Fig.

8-5

Examples of

Termj-nation

8-6 (1)

Interface Input and output interface with CMOS system, circuit are naturally or most systems

When rhaking some processing make exchange of These input in signals

with.external signal lines

or mechanism. made long reactance. give

and output

many cases, if

and have distributed directly connected with

inductance

Therefore, rise

CI'OS, they will

to various

troubles.

Conceivable induced due to signal noise for for

serious

troubles

mav be the malfunction of input/output

due to element of of

noise, surge. line

and the destruction To cope with

these problems, impedance) receiving or

reduction inserti-on is

impedance

(driving

eliminating the fornrEr,

circuit while

on the

side

applied taken

surge

protective

measures are

the latter.

Fig.

8-6

illustrates on the input

an example of side'.

making noise

. surge

pro-

tection

89

(a) and (b) of

this

figure lnput

show an example of absorbing waveform by RC. (c) and (d) surge.

noise by integrating indicate

an example of protecting

cl.os from input

Fi g .

8- 7 giv es a n e x a mp l e o f o u tp u t

i n te rface.

These are should be

only one example, but in any case, some protection given to an interface involving long signal line.

7n
(a) uoise

T
Ki11er I (u)

T
N o i e e Ki l-1er 2

vcc

vco ,\

G

tt
Z

(c)

Surge Protection

1

Surge Proiection

F ig.

8- 6

C M O S In p u t Pro te c ti v e

C i rcui t

4i
(a) Surge Protection f

J_

(u) output Driver

\ Ei+ fl,i
(a) Surge Protection Z

(")

output

Driver

P

Fig.

B-7

Output

Protection/Driving

Circuit

90

(2)

Interface In the

of

C MOS IC mutual interface between that is CIOS IC, limitation actually adding input of imfan out

case of of

pedance may not consider capacity

CMOS has so large However,

value there time power

be so large. fall of

need to effect of load

propagation of

due to

and an increase

consumption.

As input fan outs

capacity are taken

of

C M O Si s

about

5 pF per capacity

input, of

if

10 given

for line

example, capacity

load

50pF is board

by it, also

and further, be taken

on the printed shows that only the

must

i-nto account. is controlled out.

This not

processing constituting

speed of

system also

by circuit

method but

bv fan

When constituting to examine fan out

a system with by taking

CI"OS IC, points

it

is into

recommended cosideration.

these

(3)

Interface

between, different to be considered of supply

CMOS families between different between CI,OS families trlhen

The problem i-s difference different it is all

voltages are

families.

C MOS families right to

used with to

the

same power source, due to the difis

pay attention time di.fference, voltage

Ehe hazard but in

propagation ferent needed

delay

the case of

power source,

the

level

converting

circuit

Fig.

8-8

shows an interface at 6V^, 15V to

method from The npst level

the

standard

C MOS to

oprating

74HC.

popular shift

method is function as

use C MOS (4O4gB/40508) shown in this figure.

which-Ias

91

4 0 4 98140508 has d i o d e o f GND side co ns t r uc t ed t ha t c u rre n t
does not

diode flow

only, in of the

and is power

so source

(VCC) of 5V system even t h o u g h v o l t a g e

15V is

impressed.

On the

otherhand,

an interface

from

74HC to level it is

standard shift

C MOS as to

can be reali indicated in

zed by using Fig. 8-9(a).

TC5020BP of Fgrther, as shown in can of

use IC, possible

also 8-9(b).

use discrete employing inversion.

transistor

Fig.

The circuit power

discrete

transistor

course

be used for

(4)

Interface

with

TTL TII- with TC74HC series, in that of input and output trouble. voltage Fan out of

When driving leve1 is

can be connected by output example is

state. without

decided Its

current shown in

CMOS IC and input 8-10..

current

TTL.

Fig.

61F"15V 4049P,,/50B'

!Lt

i+
I
L___
C llOS Level

l

t_
S t a n d ard

___J
thifter

L

Fig.

8-€

Standard

C D'0S + 74HC Interface

92

5V

6V-15V

-l
(a)

Ll
T C 5 O? O B P

14HC

Standard

C MOS

Example of

using

level

shifter

IC.
6V- L5V

- - --.{

rl
LJ

,/ oHC

Stand.ard

C I1OS

Level conversion by transi-stor using transistor C MOS

(b) , Example of Fig. 8-9

7 4 H C .+ S t a n d a r d

vgc:5v Fan Out Number Standard TyPe

Buffer

Type

TTL S TTL LS TTL ALS TTT,

2 2 10 20

3 3 15 30

Fi g .

8 -1 0

+ T C 7 4 H C TTL I n t e r f a c e 93

In

this

way,

TC74HC series

is

capable

of

directly

driving

various On the

TTL devices. other to hand, convert when driving output in TC74HC series level case of from TTL to TTL, input which of and and it is

necessary level has of

voltage this

74HC.

Normally, level is with

TCT4HCT series Input

same input

LS TTL are that

used. of

current

TCT4HCT series therefore the said pul1

very is

sma11 like imposed fa11

TC74HC series, side it is 74L5,

no burden

on the

driving

speed also

does not

so much. Another Fig.

Therefore npthod

can be to use

to be an effective up resistance

method.

as shown in

8-11.

Rp:Pulfup

Resistance

( z_loK())

Fig. 8-11

TTL + TC74HC Interface

(5 )

In te r f ac e
At present, of

wit h C P U
as the peripheral supporting logic is of micropro-

cessor

rnany NloS and cMoSr T4LS series has the same speed with peripheral

used universally. it can naturally

As TC74H} series

74L5,

be used as microporcessor

logic.

94

As for is

an interface

between

C MOS CPU and 74HC seri-es, are CMOS. At present, of

there

no problem of

because both

however, NIOS to CMOS

prio-rity must

NI.OS CPU ls into

higher,

and interface

be taken

consideration.

Output in Fig.

of

m o s t N M O SC P U d e f l - e c t s 8s outputs with VCC. the For qf both

up to near driving typer in ro

VCC, but

as shown MOS takes

8-12,

MOS and load deflection to

are.constituted place carry easy until out to

enhancement this reason,

order

certainly 74HC, it is

signal

transfer which

from

NMOS CPU to of

use 74HCT series

has an input

TTT. l-evel . is used as

When connecting indicated in Fig.

74HC series, 8-12.

pull

up resistance

Next, without is of

driving

of

NMOS CPU from This like is

74HC series

can be connected input of NMOS be

difficulty. high into impedance

because,

normally out

C MOS, and DC fan

need not

taken

consideration.

Rp:Po1]up

Resistance

--

d
._l

Fig.

8-L2

CPU Interface NMOS

95

8-7

Latch-up
Ldtch up is a phenomenon peculiar controlled time, or if Rectifier) excessive to CMOS, and is phenomenon. voltage are also called the

scR, (silicon normal

During

operation

and current applied amplitude on the is

caused by big input

noise

accidental or

surge

and output

terminalr

supply current

source flows to

sud.denly fluctuated, GM, and this

abnorrnal current is cut

between Vcc and flow even.though is

abnormal signal is

continues off,

the'disturbance caused. Latch-up

and finally to

puncture

a name given

such phenomenon.

once

the

latch-up unless

takes the

place,

the is

former cut to off

condition or

is

not is vcc and

restored lowered, GND. rt

power supply

voltage be\ween of

and an overcurrent this status of is left

continues

flow

a1one, destruction take place.

element

such as melting
I

wirlng

will

(1)

Cause of Fig. 8-13

latch-up shows-.r, .Orrrvalent NPN transistor PNP transistor and parasitic from element constitute the Qz is Qr is circuit formed formed due to parasitic in in p-well of NMos of

el.ement. side while

N-substrate

PMOSside, As is clear

resistance path in this

exists through figure,

between terminals. the medium of these parasitic

current

parasitic elements

indicates Thyristor.

96

OUT Poly Srlicon resistance

b00

L__ P-[te ]-1

-+-

I

N-SubBtrate

Fig. For

8-13

Internal if current voltage

Equivalent flows drop into takes

Circuit

of

CMOS IC frorn exRs of

example,

the N-substrate place to turn in

ternal the

causes,

resi.stance

N-substrate, Ql,

and this and current resistance drop takes

causes flows Rw of place

on parasistic GND from Vcc through flows

transistor the in

towards P-Well. at both

medium of Rw, voltage

When current ends of

Rw, Q2 turns As a reincrease,

oD, and further, su1t, the voltage left

supply

current both

flows ends of

through

Rs.

drop at in the

Rs furthers

Qf and QZ are current further

turn-on

state,

and the supply

increases.

In

this

way, P-ldell

if

the voltage

drop

takes

place

in

resistance latch-up considered.

Rw of occurs,

and in

resistance

Rs of

N-substrate, causes are

and therefore,

the following

97

@ @

To make input

voltage

higher

than V66 + Vp 8-13 turns on)

(Q S o f F i g . To rnake input voltage lower

than GND - Vf 8-13 turns on)

(Q S o f F i g .

o
@

To make output- voltage

higher

than Vgg + Vp

(QS of Fig. 8-13 rurns on) To make output To raise voltage lower than GND - Vp)

o

supply voltage

VCC above the rated value and to fl o w current i n R w or R s)

c aus e br eak d o u m ,

(T o d i re c tl y

Here,

VF is

the

forward

voltage

between base and emitter Q4.

of

parasitic

bipolar

transistor

Q3 -

(2)

Latch. up strength '8-14 Fig. illustrates in

measurement measurement er<ample of 8-14, terminal (O latch-up (O is latch up strength.

As indicated current out at of that into output time

Fig.

induced or

by flowing flowing current value of

input

injection)

terminal. is

Injection), Table 8-2

and the current shows the,results types of

ueasured. Test of

Latch-up series.

Strength

representative TC74HC series

TC74HC

As indicated of

here,

have ample margin of above + 300mA

such as input against the

above + 70mA and output of * 20mA.

maximum rating

98

Inn

-{>

rcc (b ) Measuri ng ci rcui t of O Injection s trength of Input Terminal

( a) Me a su r ing c ir c uit of (E Injection strength of Input Terminal

g
vcc
IN OUT

GND

rcc (c) of @ Injection Measuring circuit strength of Output Termirral (d)

of e Injection Measuring circuit of Output Terminal strength

Input Input

condition condition

to make measured, terminal to m a k e m e a s u r e d t e r m i n a l

"Htt level. "Lt'level.

Fig.

8-14

Latch-up Current

Strength Feeding

Measuring System

Circuit

by

99

Table 8-2 Type 74HCO2 Class NOR.GATE INVERTER D-P/r LINE DECODER D-Latch

Unit

: mA

Input @
Above 70 Above 70 Above 70 Above 70 Above 70

Input Q Above 70 Above 70 Above 70 Above 70 Above 70

Output @
A'bove 300 Above 300 Above 300 Above 300 Above 300

Output Q Above 300 Above 300 Above 300 Above 300 Above 300

u04 74
138 375

(Note 1)

As for

exceedj-ng !On'A and the output exceeding t300mAr Do measurement is made as t h e r e i s a p o s s i . b i l i t y of this input

br eak down o f e l e m e n t.

(3)

Countermeasures As ample there is rnargin 'is provided in using for the latch-up unit having is as explained the in (2),

no problem for the

within the

standards. of the

However, receiving ' protective

interface

part

possibility add

excessive circuit

surge., it as indicated

recommended to in Fig. 8-15.

Fig.

8-15

Example of

Latch-up

Preventive

Method

r00

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