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Chip Implementation Center - Design Service Department - Digital Technology Section


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IC Compiler Laboratory Exercise
Design Preparation
unix% tar -xvf icc_lab_18.tar
DESIGN DATA
FILE OR DIRECTORY
Gate Level Netlist / icc_lab_18 / design_data / CHIP_syn.v
IO Constraint File / icc_lab_18 / design_data / io.tdf
Timing Constraint File / icc_lab_18 / design_data / CHIP.sdc
Scandef Fille / icc_lab_18 / design_data / CHIP.scandef
Technology File
(CIC Design Kit)
/icc_lab_18/tsmc18_CIC.tf
Layer Mapping File / icc_lab_18 / tech / macro.map
Antenna Rules / icc_lab_18 / tech / antenna_CIC.cmd
Reference Library (Memory)
/ Icc_lab_18 / ref_lib / nco_table_cos
/ Icc_lab_18 / ref_lib / nco_table_log
Reference Library (Core) / icc_lab_18 / ref_lib / tsmc18_fram
Reference Library (IO)
/ Icc_lab_18 / ref_lib / tpz973gv
/ Icc_lab_18 / ref_lib / tpb973gv
* TLU + Data / icc_lab_18 / tluplus /
Script Files / icc_lab_18 / scripts /
Directory for Physical Verification / icc_lab_18 / verify /
Environment Setup
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Lab1-1 Design Setup
1. Change directory to / run and invoke IC Compiler
unix% cd / icc_lab / Lab1 / run
unix% icc_shell -gui &
Open the file and observe .synopsys_dc.setup
unix% more .synopsys_dc.setup

2.
"File> Create Library"
Click the Windows Add
In the Select Directory window selection
../ref_lib/tpz 973gv
Press OK
../ref_lib/tpb973gv
Press OK
../ref_lib / tsmc18_fram
Press OK
../ref_lib / nco_table_cos
Press OK
../ref_lib / nco_table_log
Press OK to select Finish.
Press OK to close the window.
3. "File> Import Design"
Click the Windows Add
In the Select File window selection
../design_data/CHIP_syn.v press select Open.
Press OK.
ICC can see the entire design of the CEL View build it.
4. "File> Set TLU + ..."
Max TLU + file
../tluplus/t18.tluplus
Layer name mapping file between
technology library and ITF file
../tluplus/t18.map
5. "File> Import> Read SDC ..."
Input file name ../design_data/CHIP.sdc
Version
Latest
Other
default value
New Library Name
CHIP
Technology File
../tech/tsmc18_CIC.tf
Bus naming style
[% D]
Open library
enable
Import format

verilog
Import verilog files
../design_data/CHIP_syn.v
Top design name
CHIP

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6. "File> Save Design"
Click Save All
"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name design_setup
Press OK.
7. "File> Close Design"
"File> Close Library"
If lab1_1 not complete, you can enter in the Message / Input Area source "../scripts/design_setup.tcl"
Eli
Were behind the lab.
ps before executing the CHIP please delete folder (in Terminal use rm -rf * command)

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Lab1-2 Design Planning
1. Invoke IC Compiler
unix% icc_shell -gui &
2. "File> Open Library"
Library Name
CHIP
open library as read-only
disable
open reference library for writing
disable
Press OK.
"File> Open Design"

Select CHIP
Press OK.
3. We want to join the Core IO and the P / G pad, POC pad and Corner pad
In the Message / Input Area Input
source ../scripts/create_phy_cell.tcl
Or the Message / Input Area Input
create_cell {cornerLL cornerLR cornerUL cornerUR} PCORNER
create_cell {core_vdd1 core_vdd2 core_vdd3 core_vdd4 core_vdd5 \
core_vdd6} PVDD1DGZ
create_cell {core_vss1 core_vss2 core_vss3 core_vss4 core_vss5 \
core_vss6} PVSS1DGZ
create_cell {io_vdd12} PVDD2POC
create_cell {io_vdd1 io_vdd2 io_vdd3 io_vdd4 io_vdd5 io_vdd6 \
io_vdd7 io_vdd8 io_vdd9 io_vdd10 io_vdd11} PVDD2DGZ
create_cell {io_vss1 io_vss2 io_vss3 io_vss4 io_vss5 io_vss6 \
io_vss7 io_vss8 io_vss9 io_vss10 io_vss11 \
io_vss12} PVSS2DGZ
Press enter.
4. Read TDF file, before switching to LayoutWindows
"Floorplan> Read Pin / Pad Physical Constraints"
Input file name
../design_data/io.tdf
Press OK.

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"Floorplan> Initialize Floorplan"
Control type
Aspect ratio
Core utilization
0.6
Row / core ratio
1
Aspect ratio (H / W)
1
Horizontal row
Enable
Double back
Enable

Start first row


Disable
Filp first row
Enable
Core to left
80
Core to bottom
80
Core to right
80
Core to top
80
Press OK.
5. Insert pad filler
"Finishing> Insert Pad Filler"
Pin / Blockage cells
PFILLER20 PFILLER10 \
PFILLER5 PFILLER1 \
PFILLER05 PFILLER0005
Pin / Blockage overlap cells
PFILLER0005
Boundary placement (Top)
Enable
Boundary placement (Bottom) Enable
Boundary placement (Left)
Enable
Boundary placement (Right)
Enable
Other
Default value
Press OK.
6. "File> Save Design"
Click Save All
"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name
die_init
Press OK.

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7. "Placement> Placement macro and Standard Cells"
Effort
Low
Congestion driven
disable
Timing driven
disable
Hierarchical gravity enable
Press OK.
Can be observed in all Macro and Standard Cell placement are completed
First of all the macro setting surrounded each of keepout margin 10um
In the Message / Input Area Input
set_keepout_margin -type hard -all_macros -outer {10 10 10 10}
In order to facilitate subsequent steps, we will be placed in a fixed position Macro unity
In the Message / Input Area Input
move_objects -x 270 -y 496 [get_cells -hier log]
move_objects -x 270 -y 270 [get_cells -hier cos]
Place to live after the completion of all macro fix
In the Message / Input Area Input
set_dont_touch_placement [all_macro_cells]
Click Flylines
Macro observe the connection status

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8. Some cell overlap together to perform Incremental placement will be laid beneath the memory cell
"Placement> Placement macro and Standard Cells"
Effort
Low
Congestion driven
disable
Timing driven
disable
Hierarchical gravity enable
Select Advanced Options Tab

Incremental
enable
Other
Default Value
Press OK.
9. Connect Cell of P / G nets
"Preroute> Derive Power Ground Connection"
Manual connect
selected
Power net
VDD
Ground net
VSS
Power pin
VDD
Ground net
VSS
Other
Default value
Press Apply.
10. Setting PNS Constraints
"Preroute> Power Network Constraints> Layers Constraints"
layer
METAL3
Direction
Horizontal
Density (By strap number) Max: 10 Min: 3
Width
Max: 5 Min: 3
Press Set re-election
layer
METAL2
Direction
Vertical
Density (By strap number) Max: 10 Min: 3
Width
Max: 5 Min: 3
Press Set and press Close to leave.
"Preroute> Power Network Constraints> Ring and Straps Constraints"
Power Ground nets
VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS \
VDD VSS VDD VSS

Horizontal layers
METAL3
Vertical layers
METAL2

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Ring width
enable
Variable
Variable (Max: 3 Min: 2)
Ring offset to IO or PNS region 12
Extend straps to
Core ring
Press Set and press Close to leave.
"Preroute> Power Network Constraints> Global Constraints"
No routing over hard macros
enable
Other
Default value
Press Set and press Close to leave.
"Preroute> Power Network Constraints> Block Ring Constrants"
Cell master
selected (nco_table_cos nco_table_log)
Other
Default value
Power Ground nets
VDD VSS
Vertical layer
METAL2 (Width: 3 Offset: 1)
Horizontal layer
METAL3 (Width: 3 Offset: 1)
Press Set and press Close to leave.
"Preroute> Synthesize Power Network"
Synthesis power network by nets VDD VSS
Supply voltage
1
Target IP drop
10% of supply voltage

Power budget (mW)


80
Other
Default value
Press Apply observed IR drop map, press Commit connection P / G net.
11. Strap manually create CHIP on the right connections
"Preroute> Create Power Straps ..."
Direction
Vertical
X start
1435
Nets
VDD VSS
Width
3
Layer
METAL2
Extend for multiple connections Enable
Gap
10
Press Apply.

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12. Strap manually create connections to the left of CHIP
"Preroute> Create Power Straps ..."
Direction
Vertical
X start
265
Nets
VDD VSS
Width
3
Layer
METAL2
Low ends
At: (786)
Extend for multiple connections Enable

Gap
10
Press OK.
13. The establishment of I / O Pad to P / G Ring, the level of the first connecting portion of the M1
"Preroute> Preroute Instances"
Instances Types
Pad (just check the rest Pad disable)
Target directions
Four side (just check the top and bottom rest disable)
Route pins on layer
METAL1
Primary routing layer
Pin
Extend for multiple connections Enable
Gap
10
Press Apply.
Partial re-connection of M2
"Preroute> Preroute Instances"
Instances Types
Pad (just check the rest Pad disable)
Target directions
Four side (left and right just check the rest disable)
Route pins on layer
METAL2
Primary routing layer
Pin
Extend for multiple connections Enable
Gap
10
Press Apply.
Block Ring to build P / G Ring connection
"Preroute> Preroute Instances"
Press Apply
14. Preroute Standard Cell Rail
Instances Types
Macro (Macro leaving only remaining disable)
Route pins on layer
All
Primary routing layer
Pin

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"Preroute> Preroute Standard Cells ..."
Option Routing Option
Do not route over macro cells
enable
Fill empty rows
enable
Keep floating rail segments
disable
Extend for multiple connections Enable
Gap
10
Press OK to leave.
15. Do not put down the set Strap Standard Cell
In the Message / Input Area Input
set_pnet_options -complete "METAL2 METAL3"
create_fp_placement -incremental all
16. "File> Save Design"
Click Save All
"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name
design_planning
Press OK.
17. "File> Close Design"
"File> Close Library"
If lab1_2 not complete, you can enter in the Message / Input Area source
"../scripts/design_planning.tcl" to
Lee's lab conducted behind.

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Lab1-3 Placement
1. Invoke IC Compiler

unix% icc_shell -gui &


2. "File> Open Library"
Library Name
CHIP
open library as read-only
disable
open reference library for writing
disable
Press OK.
"File> Open Design"
Select CHIP
Press OK.
3. "File> Import> Read SDC ..."
Input file name ../design_data/CHIP.sdc
Version
Latest
Other
default value
4. Verify that the clock definitions are complete:
In the Message / Input Area Input
report_clock
report_clock -skew
5. Click the Draw Clock Trees data on layout
And LayoutWindows
Observe Clock Tree
6. Set zero interconnect delay attribute ture
"Timing> Timing and Optimization Setup ..."
Zero Interconnect delay
enable
Other
default value
7. Report timing
In the Message / Input Area Input
report_timing
8. Check all constraint violations:
In the Message / Input Area Input
report_constraint -all

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9. Setting zero interconnect delay property is false
"Timing> Timing and Optimization Setup ..."
Zero Interconnect delay
disable
Other
default value
10. Check for potential floorplan issues:
In the Message / Input Area Input
check_physical_design -for_placement
check_physical_constraints
11. Load the SCANDEF file:
In the Message / Input Area Input
read_def ../design_data/CHIP.scandef
report_scan_chain
check_scan_chain
12. Report the settings for high fanout synthesis:
In the Message / Input Area Input
report_ahfs_options
13. Based on the above, and knowing the defaults (see man-page) have a look at which nets are
candidates for high fanout synthesis:
In the Message / Input Area Input
all_high_fanout -nets -threshold 100
14. Click the Draw Scan Chain data on layout
And observe the scan chain in LayoutWindows
15. Read the SAIF file of the design:
In the Message / Input Area Input
read_saif -input ../design_data/CHIP.saif -instance_name test_top / CHIP_1
16. Setup the power optimization option:
In the Message / Input Area Input
set_power_options -leakage true -dynamic true

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17. Setup the tie cell option:
In the Message / Input Area Input
source ../scripts/add_tie.tcl
18. Message / Input Area Input
place_opt -power -optimize_dft

Or
"Placement> Core Placement and Optimization ..."
Effort
Medium
Power optimization
enable
Reorder scan during placement enable
Press OK.
19. Connecting the Cell P / G nets
"Preroute> Derive Power Ground Connection"
Manual connect
selected
Power net
VDD
Ground net
VSS
Power pin
VDD
Ground net
VSS
Other
Default value
Press Apply.
20. "File> Save Design
Click Save All
"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name
placement
Press OK.
21. "File> Close Design"
"File> Close Library"
If lab1_3 not complete, you can enter in the Message / Input Area source "../scripts/placement.tcl" to
facilitate post
Lab conducted face.

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Lab1-4 CTS
1. Invoke IC Compiler
unix% icc_shell -gui &
2. "File> Open Library"
Library Name
CHIP
open library as read-only
disable
open reference library for writing
disable
Press OK.
"File> Open Design"
Select CHIP
Press OK.
3. As the design contains a frequency divider, set clock pin for hierarchical pin.
In the Message / Input Area Input
set cts_enable_clock_at_hierarchical_pin true
4. Set the ICC CG cell setting
In the Message / Input Area Input
set power_cg_auto_identify true
5. The following commands should be executed before performing CTS.
In the Message / Input Area Input
check_physical_design -for_cts
check_clock_tree
report_clock
Check for error?
report_clock -skew
report_clock_tree -summary
report_constraint -all
See if there is violation?
6. Open an Interactive CTS Window by select Clock.
Select
in LayoutWindow in

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7. Turn on hold time fixing.
In the Message / Input Area Input
set_fix_hold [all_clocks]

8. Generate a QoR report.


In the Message / Input Area Input
report_qor
9. Perform psynopt:
In the Message / Input Area Input
set_max_area 0
set physopt_area_critical_range 0.1
10. Perform CTS optmization:
In the Message / Input Area Input
clock_opt -fix_hold_all_clocks -no_clock_route
11. Click the Draw Clock Trees data on layout
And LayoutWindows outlook
Police Clock Tree.

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12. Review the global skew after CTS.
report_clock_tree -summary
ex_clk
Skew
Longestpath
in_clk
int_clk
13. Connect the Cell P / G nets
"Preroute> Derive Power Ground Connection"
Manual connect
selected
Power net
VDD
Ground net
VSS
Power pin
VDD
Ground net
VSS
Other
Default value
Press Apply.
14. "File> Save Design

Click Save All


"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name
cts
Press OK.
22. "File> Close Design"
"File> Close Library"
If lab1_4 not complete, you can enter the source "../scripts/cts.tcl" Eli's lab back in Message / Input
Area
Get on.

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Lab1-5 Route
1. Invoke IC Compiler
unix% icc_shell -gui &
2. "File> Open Library"
Library Name
CHIP
open library as read-only
disable
open reference library for writing
disable
Press OK.
"File> Open Design"
Select CHIP
Press OK.
3. Analyze the design for timing (setup and hold)
In the Message / Input Area Input
report_timing
Timing observe whether the violation?
4. Check the routeability of the design
"Route> Check Routability ..."
Observe whether there is error?
5. It is recommended that you can use zroute do routing, unlike traditional routing, zroute using off-grid
route, effect

Better, time is more than half as long as the traditional routing


"Route> Zroute Mode option will enable (2010.03 version default is enable, please confirm once again)
Setting options when routing and routing set when joined redundant via
"Route> Routing Setup> Set common Route Option
Via Tab election
Post detail route redundant via insertion
High
Concurrent redundant via flow
Mode: Insert at High Cost
Concurrent redundant via flow
Effort: High
Press OK.
6. To install a set of antenna rules, source the following command file
In the Message / Input Area Input
source ../tech/antenna_CIC.cmd

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7. Perform clock net routing
"Route> Net Group Route ..."
Net to route
All clock nets
other
default value
Press OK.
8. Perform auto routing
"Route> Auto Route ..."
Press OK.
9. DRC violation error checking and fixing
"Verification> Error Browser ..."
Press OK.
There DRC error point to take place, will be marked in the layout.
10. Recalculate the number of DRC violations as seen by the router
"Route> Verify Route ..."
After performing as well as DRC Violation, the following message

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Verify Summary:
Total number of nets = 32351, of which 0 are not extracted
Total number of excluded ports = 0 ports of 0 unplaced cells connected to 0 nets
0 ports without pins of 0 cells connected to 0 nets
0 ports of 0 cover cells connected to 0 non-pg nets
Total number of DRCs =
Twenty three
Total number of antenna violations = 6
Total number of voltage-area violations = 0
Total number of tie to rail violations = not checked
Total number of tie to rail directly violations = not checked
If DRC Violation shall execute Step 11, if there is no DRC Violation, you can skip to Step 12
11. Run a search & repair operation
"Route> Detail Route"
Incremental routing
enable
Initial DRC from input cell
enable
Press OK.
Note !! execute Detail Route to correct DRC violation, when the
Initial DRC from input cell option is enable,
Always make sure there is first done verify route
If DRC violation, you can use
Detail Route and under
Incremental routing and Initial DRC from input cell option
Correction, but if there is timing violation, please use the following ways to fix:
"Route> Core routing and Optimization ..." and press OK.
12. If you need to insert the antenna diode Antenna Violation
First set the insert antenna diode set
"Route> Routing Setup> Set Detail Route Options ..."
Select Antenna Tab
Diode library cells for antenna fixing
ANTENNA
Insert diode during routing to fix antenna violations
enable
Other
Default value
Press OK to leave.
Then perform Antenna Violation Fixing
"Route> Verify Route ..."
"Route> Detail Route"

Incremental routing
enable
Initial DRC from input cell
enable
Press OK.

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13. Connect the Cell P / G nets
"Preroute> Derive Power Ground Connection"
Manual connect
selected
Power net
VDD
Ground net
VSS
Power pin
VDD
Ground net
VSS
Other
Default value
Press Apply.
14. "File> Save Design
Click Save All
"File> Save Design"
Click Show advanced options
Save As
Enable
Save As Name
route
Press OK.
23. "File> Close Design"
"File> Close Library"
If lab1_5 not complete, you can enter in the Message / Input Area source "../scripts/route.tcl" Eli back
lab conducted.

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Twenty one
Lab1-6 DFM
1. Invoke IC Compiler
unix% icc_shell -gui &
2. "Library> Open"
Library Name
CHIP
Library Path
Press OK.
"Cell> Open"
Cell Name
CHIP
Press OK.
3. Check the design for mask rule violations.
"Verification> DRC ..."
Read child cell from
Cell view
Select Save and Run DRC.
This result is for reference DRC, DRC results Calibre DRC based.
"Verification> LVS ..."
What was observed violation, and choose violation with Error Browser.
What violation analysis can be ignored. (Here there may be a mistake, that is, Floating Port, which
belong to DFF's
QN pin is unused so Floating Port, this error can be ignored)
4. Insert standard cell filler
In the Message / Input Area Input
insert_stdcell_filler -cell_without_metal "FILL64 FILL32 FILL16 \
FILL8 FILL4 FILL2 FILL1 "\
-connect_to_power {VDD} \
-connect_to_ground {VSS}
5. Verify insert standard cell filler after the DRC violation
"Route> Verify Route ..."
6. If there is DRC violation execute DRC Violation fixing
"Route> Detail Route"
Incremental routing
enable
Initial DRC from input cell
enable
Press OK.

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Twenty two
Note !! execute Detail Route to correct DRC violation, when the
Initial DRC from input cell option is enable,
Always make sure there is first done verify route
If DRC violation, you can use
Detail Route and under
Incremental routing and Initial DRC from input cell option
Correction, but if there is timing violation, please use the following ways to fix:
"Route> Core routing and Optimization ..." and press OK.
7. Reconnect PG net
"Preroute> Derive Power Ground Connection"
Manual connect
selected
Power net
VDD
Ground net
VSS
Power pin
VDD
Ground net
VSS
Other
Default value
8. Add IO text
In the Message / Input Area Input
source ../scripts/add_io_text.tcl
add_io_text TEXT3 20 portName
The Core Power branded text, you must hit the design of the Ring
"Edit> Create> Text ..." or Shift + t
Text
VDD
Height
20
Layer
TEXT3
Location selected point play on the look and press OK.
"Edit> Create> Text ..." or Shift + t
Text
VSS

Height
20

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Twenty three
Layer
TEXT3
Location selected point play on the look and press OK.
The IO Power branded text, you must hit the IO Power Pad's true pin
"Edit> Create> Text ..." or Shift + t
Text
IOVDD
Height
20
Layer
TEXT3
Location selected point play on the look and press OK.
"Edit> Create> Text ..." or Shift + t
Text
IOVSS
Height
20
Layer
TEXT3
Location selected point play on the look and press OK.
9. Add bonding pad
In the Message / Input Area Input
source ../bond_pads/createNplace_bondpads.tcl
createNplace_bondpads
-inline_pad_ref_name PAD60GU \
-stagger true \

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Twenty four
-stagger_pad_ref_name PAD60NU
10. "File> Save Design"
Click Save All

"File> Save Design"


Click Show advanced options
Save As
Enable
Save As Name
dfm
Press OK.
11. Stream Out GDS II
In the Message / Input Area Input
set_write_stream_options -map_layer ../tech/macro.map \
-child_depth 20 -flatten_via
"File> Export> Write Stream ..."
Output file format
GDSII
Cells to output
Selected cells
Stream file name to write
CHIP.gds
Press OK.
The GDS file copy to verify the information folder
unix% cp ./CHIP.gds ../verify/drc
unix% cp ./CHIP.gds ../verify/lvs
12. Output SDF file
In the Message / Input Area Input
write_sdf -version 1.0 -context verilog -load_delay net CHIP.sdf
The SDF file copy to verify the information folder
unix% cp ./CHIP.sdf ../verify/function
13. Verilog Out for post-layout simulation & LVS
"File> Export> Write Verilog ..."
Press Default
Output verilog file name
CHIP_route.v
Output physical only cells
disable
Unconnected ports
enable
Diode ports
enable

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25
Wire declaration
enable
Backslash before Hierarchy Separator
enable
The verilog file copy to a folder within
unix% cp ./CHIP_route.v ../verify/function
unix% cp ./CHIP_route.v ../verify/lvs

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Lab1-7 Calibre DRC & LVS & Post-Layout Simulation
1. Change directory to / icc_lab / Lab1 / verify / drc
unix% cd / icc_lab / Lab1 / verify / drc
2. Modify the Calibre-drc-cur file
LAYOUT PATH "./CHIP.gds"
LAYOUT PRIMARY "CHIP"
3. Perform Calibre DRC
unix% calibre -drc -hier Calibre-drc-cur
Observe DRC.rep file to see if there drc error, you should see several DRC error, all of density-related
violation
Can be ignored, you can ignore this DRC error
If error, use Calibre RVE drc number of errors can be found, because the coordinates and other
information, go back to IC Compiler
Do the correction.
unix% calibre -rve DRC_RES.db
4. In the ICC read Calibre DRC results
Under the ICC Layout window
"Verification> Read Third-party DRC Error File ...
Error file
../verify/drc/DRC_RES.db
Other
default value
Observe the place where there Violation, and what is not seen and Calibre DRC ICC has seen violation
5. Change directory to / icc_lab / Lab1 / verify / lvs
unix% cd / icc_lab / Lab1 / verify / lvs
6. RAM Black Box generate Verilog and Spice stall

Nco_table_cos.v modify the original file, leaving only the module and input, output declaration, as well
as other Memory
And so on.
nco_table_cos.v (already finished editing)
module nco_table_cos (Q, CLK, CEN, A);
output [15: 0]
Q;
input
CLK;
input
CEN;

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input [9: 0]
A;
endmodule
Nco_table_cos.spi use v2lvs produce stalls
unix% v2lvs -v nco_table_cos.v -o nco_table_cos.spi
nco_table_cos.spi
$ Spice netlist generated by v2lvs
$ V2010.4_26.16
.SUBCKT Nco_table_cos Q [15] Q [14] Q [13] Q [12] Q [11] Q [10] Q [9] Q [8] Q [7] Q [6]
+ Q [5] Q [4] Q [3] Q [2] Q [1] Q [0] CLK CEN A [9] A [8] A [7] A [6] A [5] A [4 ] A [3] A [2]
+ A [1] A [0]
.ENDS
7. Modify CHIP_route.v all keywords pad PVDD and PVSS comment
... ..
// PVSS2DGZ io_vss3 (.VSSPST33 (SYNOPSYS_UNCONNECTED_156));
// PVSS2DGZ io_vss2 (.VSSPST33 (SYNOPSYS_UNCONNECTED_157));
// PVSS2DGZ io_vss1 (.VSSPST33 (SYNOPSYS_UNCONNECTED_158));
// PVDD2DGZ io_vdd11 (.VDDPST33 (SYNOPSYS_UNCONNECTED_159));
// PVDD2DGZ io_vdd10 (.VDDPST33 (SYNOPSYS_UNCONNECTED_160));
// PVDD2DGZ io_vdd9 (.VDDPST33 (SYNOPSYS_UNCONNECTED_161));
... ..
8. CHIP_lvs.v convert spice format
v2lvs -v ./CHIP_route.v -l tpz973gv_lvs.v -l tsmc018_lvs.v -l nco_table_cos.v -l nco_table_log.v
-o CHIP.spi -s tpz973gv_lvs.spi -s tsmc018_lvs.spi -s nco_table_cos.spi
-s nco_table_log.spi -s1 VDD -s0 VSS

Or
unix% ./v2lvs_lab.sh
9. Modify Calibre-lvs-cur
SOURCE PRIMARY "CHIP"
SOURCE PATH
"./CHIP.spi"
SOURCE CASE YES (plus)
LAYOUT PRIMARY "CHIP"
LAYOUT PATH
"./CHIP.gds"

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LAYOUT CASE YES (plus)
VIRTUAL CONNECT BOX NAME "?" (Plus)
Removes IO Power & Ground relevant
// LVS BOX PVDD2DGZ
// LVS BOX PVSS2DGZ
// LVS BOX PVDD2POC
Then remove the CORE Power & Ground relevant
// LVS BOX PVDD1DGZ
// LVS BOX PVSS1DGZ
Added in the last two lines
LVS BOX nco_table_log
LVS BOX nco_table_cos
10. Perform Calibre LVS
unix% calibre -lvs -spice layout.spi -hier -auto Calibre-lvs-cur
OVERALL COMPARISON RESULT observed lvs.rep find part if match
11. Change directory to Lab1 / tbench
unix% cd / icc_lab / Lab1 / verify / function
12. Modify CHIP_route.v all keywords pad PVDD and PVSS comment
... ..
// PVSS2DGZ io_vss3 (.VSSPST33 (SYNOPSYS_UNCONNECTED_156));
// PVSS2DGZ io_vss2 (.VSSPST33 (SYNOPSYS_UNCONNECTED_157));
// PVSS2DGZ io_vss1 (.VSSPST33 (SYNOPSYS_UNCONNECTED_158));
// PVDD2DGZ io_vdd11 (.VDDPST33 (SYNOPSYS_UNCONNECTED_159));
// PVDD2DGZ io_vdd10 (.VDDPST33 (SYNOPSYS_UNCONNECTED_160));
// PVDD2DGZ io_vdd9 (.VDDPST33 (SYNOPSYS_UNCONNECTED_161));
... ..

Edit CHIP_route.v all ANTENNA keywords cell comment


... ..
// ANTENNA diode_6 (.A (in1 [4]));
// ANTENNA diode_5 (.A (in1 [3]));

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// ANTENNA diode_8 (.A (in1 [2]));
... ..
13. Edit run.f
./test_top.v
./CHIP_route.v
-v ./tsmc018.v
-v ./tpz973gv.v
-v ./nco_table_cos.v
-v ./nco_table_log.v
+ Access + r
14. unix% ncverilog -f ./run.f
After the end of the simulation can be used to observe waveforms verdi.