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C.Vijaya Bhaskar
P.G Student
VLSI, Department of E.C.E
SIETK, Puttur
Assistant Professor
Department of E.C.E
SIETK, Puttur
I. INTRODUCTION
Power consumption being the major problem in achieving high
performance and it is listed as one of the top three challenges in
electronics industry. The clock system, which consists of the clock
distribution network and flip-flops and latches, is one of the most power
consuming components in a VLSI system. It accounts for 30% to 60% of
the total power dissipation in a system. As a result, reducing the power
consumed by flip-flops will have a deep impact on the total power
consumed. A large portion of the on chip power is consumed by the clock
circuits.
Power consumption is determined by several factors including frequency
, supply voltage V, data activity , capacitance C, leakage, and short
circuit current
P=Pdynamic+Pshort circuit+Pleakage
In the above equation, dynamic power Pdynamic is also called the
switching power,
Pdynamic=CV2.
Pshort circuit is the short circuit power which is caused by the finite rise
and fall time of input signals, resulting in both the pull up network and
pull down network to be ON for a short while
Pshort circuit= Ishort circuitVdd
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Pleakage is the leakage power. With supply voltage scaling down, the
threshold voltage also decreases to maintain performance. However, this
leads to the exponential growth of the sub threshold leakage current.
Sub threshold leakage is the dominant leakage now.
Pleakage= IleakageVdd.
Flip-Flop is an electronic circuit that stores a logical state of one or more
data input signals in response to a clock pulse. Flip-flops are often used
in computational circuits to operate in selected sequences during
recurring clock intervals to receive and maintain data for a limited time
period sufficient for other circuits within a system to further process
data. At each rising or falling edge of a clock signal, the data stored in a
set of Flip-Flops is readily available so that it can be applied as inputs to
other combinational or sequential circuitry. Such flip-flops that store
data on both the leading edge and the trailing edge of a clock pulse are
referred to as double-edge triggered Flip-Flops otherwise it is called as
single edge triggered Flip-Flops.
In digital CMOS circuits there are three sources of power dissipation,
the first is due to signal transition, the second comes from short circuit
current which flows directly from supply to ground terminal and the last
is due to leakage currents. As technology scales down the short circuit
power becomes comparable to dynamic power dissipation. Furthermore,
the leakage power also becomes highly significant. High leakage current
is becoming a significant contributor to power dissipation of CMOS
circuits as threshold voltage, channel length and gate oxide thickness
are reduced. Consequently, the identification and modeling of different
leakage components is very important for estimation and reduction of
leakage power especially for High-speed and low-power applications.
Multithreshold Voltage Based CMOS (MTCMOS) and voltage scaling
are two of the low power techniques used to reduce power.
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The flip flop output is depending upon the previous output Qand Qb_kpr
in addition with clock and data input. So the initial condition should be
like when D=1 the previous state of Q should be 0 and Qb_kpr should
be 1. Similarly when D=0 the previous state of Q should be 1 and
Qb_kpr should be 0. Whenever the D=1 the transistor N5 is idle,
Whenever the D=0 input transmission gate is idle.
In high frequency operation the input transmission gate andN5 will
acquire incorrect initial conditions due to the feedback from the output.
The noise coupling occurred in the Q output due to continuous
switching at high frequency. The glitch will be appearing in the Q
output. It will propagate to the next stage which makes the system more
vulnerable to noise. In order to avoid the above drawbacks and reduce
the power consumption in proposed flip flop, we can make the flip-flop
output as independent of previous state. That is without initial
conditions and removal of noise coupling transistors. In addition double
edge triggering can be applied easily for power reduction to the proposed
flip flop. It will be a less power consumption than other flip flops.
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In this proposed Clocked Pair Shared Flip Flop, a high threshold voltage
NMOS transistor is provided with a sleep signal S, which is high in the
active mode and low during the standby mode.Here, the first and the
second stage shares the same clocked pair (M5 and M6). Furthermore,
the pMOS M1 is always turned on and is connected to the power supply
Vdd, thus charging the internal node X all the time. This reduces the
floating of node X and enhances the noise robustness.
The flip flop works, when both clk and clkdb are at logic 1. Pseudo
nMOS and conditional mapping technique both are combined using the
above scheme. The nMOS M3 is controlled by a feedback signal. For
input D=1and S=1,Q will be high, switching ON the transistor M8, and
turning OFF M3 thus parrying redundant switching activity and flow of
shortcircuit current at the node X. When D transits to 1 the output Q is
pulled up by pMOS M2 whereas M4 is used to pull down Q when D=0
and Y=1 at the arrival of clock pulse. When the input D transits from 0-1
the short-circuit occurs for once even though M1 is always ON, thus
disconnecting the discharge path and turning off M3 after two gates
delay by feedback signal. There will be no short-circuit even if the input
D stays high as M3 disconnects the discharge path. The output of the flip
flop depends upon the state previously acquired by Q and QB along with
the clock and the data signal inputs provided.
T-FLIP-FLOP MTCMOS TECHNIQUE
The below diagram which shows the extension of the MT-CPSFF.T
flip-flop which uses for the reducing switching activity and also power
consumption. This is the another proposed MTCMOS technique, The
schematic of MT-CPSFF is shown in Fig.5.2
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CDFF
CDMFF
CPSFF
MT-CPSFF
MT-CPSFF
AREA
26
SWIT
ICHIN
G
TRANS
ISTOR
13
20
17
21
27
7
4
4
4
FREQUENCY
500MHZ
700MHZ
POWER CONSUMPTION
1.5
9.7
1.9
1.3
1.2
1.1
SUPPLY VOLTAGE
3
1.5
3V
54.8
14.6
82.0
49.6
2.7
53.7
22.9
2.5
32.8
7.7
2.12
11.6
7.5
2.00
10.5
VII CONCLUSION
In this paper, a new design for D and T flip-flop is introduced to reduce
internal switching activity of nodes and stand by leakage power; along
with this variety of design techniques for low power clocking system are
reviewed. This proposed flip-flop reduces local clock transistor number
and power consumption as well. The proposed MT-CPSFF outperforms
previously existing CDFF, CDMFF and CPSFF in terms of power and
good output response by approximately 20% to 85%. Furthermore,
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several low power techniques, including low swing and double edge
clocking, can be explored to incorporate into the new flip-flop to build
system.
References
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