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AMS C35 Inverter Example

Part III: Layout and Verification
This tutorial builds on Part I to introduce custom layout of the inverter and layout verification (compliance with
layout design rules, or design-rule-check (DRC), and confirmation that layout matches the schematic, or
layout-vs-schematic (LVS) check).
1. Inverter Layout: to begin the layout, we need to create a layout view of the design.
a. From the Library Manager, select Library: ams_5007, Cell: inv1, then from the menu, select: File -> New --> Cellview...
b. In the pop-up, change the tool to Virtuoso. You should see the View Name change to layout.
Select OK.

c. This brings up two windows: a blank layout window (similar to the schematic window) and an LSW
window with all of the available layout layers (with appearance, name, and dg (drawing) or pn (pin)
designation). We will primarily use only the first 21 layers, from NTUB to PAD. Note that there is a
glitch in Cadence so that you cannot close the LSW window without exiting Cadence completely.
The first few layers include:
i. NTUB: n-well for pmos devices;
ii. DIFF: used for drawing any diffusion (n or p type for transistors and for substrate and well
contact);
iii. NPLUS: designates any diffusion within the box to be n-type diffusion
iv. PPLUS: designates any diffusion within the box to be p-type diffusion
v. MIDOX: designates a thick oxide (not used for now)
vi. HRES: designates poly within box to be of high resistance type (not used for now)
vii. POLY1: 1st layer poly-silicon, used for transistor gates
viii. POLY2: 2nd layer poly-silicon (not used for now)
ix. CONT: designates contact from diffusion to MET1
x. MET1-4: four metal layers; dg and pn are the same but appear differently on the screen (dg
for standard drawing and pn for pins)
xi. VIA1: metal via between MET1 and MET2 (similar for VIA2-3)
xii. PAD: designates area for bonding pads where protection silicon-dioxide layer will be etched
away (used only in final project)
d. From this point, proper layout is somewhat painful until you learn the most common layout rules. It
is best if you spend some time reading the layout rules from AMS Design Documents, C35 design
rules. Focus on pages 5-20. Then follow the procedures below to add layers and run DRC to
receive feedback on layout errors.

e. The best starting point is to quickly sketch a top-view of the desired layout, making decisions on
whether the poly gates will be vertical or horizontal, where metal contacts will be placed and how
metal will be routed for I/O and power supplies, and how or if you will be paralleling any devices.
Once these decisions have been made, it is important to be consistent with device orientation and
layout when matching is critical. Note that if you do parallel devices, you should go back and
change the schematic to match. There is a tool in cadence for auto-generation of parameterized
cells (or p-cells) such as mosfets, resistors and capacitors, that will auto-create devices with
specified dimensions, contacts, etc. This function has been disabled for now so you will have
experience designing devices manually, which is generally necessary for complex analog circuitry.
NOTE: ignore warnings that the pcell license is not enabled.
f. Once you have a general sketch of the layout (on paper or in your mind), you begin by selecting a
layout layer from the LSW window, then a drawing shape from the icons on the left side of the
layout window. Here we will draw the inverter with the gates vertical, starting with the gate for the
pmos.
i. The process allows you to layout on a 0.01u grid. However this is generally more trouble
than it is worth, and all layout rules are in multiples of 0.05u. Change the grid by selecting
from the layout menu: Options --> Display ... (or hotkey e), then changing the X Snap & Y
Snap spacing to 0.05 (which is in micron). This is the grid your mouse operates on (the
Minor & Major spacing designates the visible grid). In this menu, you can also change how
you are able to move blocks when creating new or editing (Snap Modes): orthogonal,
diagonal, vertical, horizontal, or any angle. The last option is the easiest to work with, but
makes it easy to make alignment mistakes. The more limiting options force alignment, but
can be frustrating when moving blocks around your layout. Another useful option is in
Options --> Layout Editor ... (hotkey E), where you can click to enable/disable gravity
control, which forces your mouse to block edges or labels when it is close. The hotkey g

also turns gravity on and off.

ii. To draw the gate, note the layout rules under the heading 4.1.3 POLY1. To shrink the
tutorial layout we will use a 5u x 0.35u pmos device (and make the same change to the
schematic). We need a 0.35u (for length) by 5u (width) + the required poly overhang (rule
PO.O.1 = 0.4u) on each side of the transistor, plus some distance for the poly contact. Start
with a 0.35u x 7u block by:
iii. Select POLY1 from the LSW window, Rectangle icon in the layout window (left side, you
may need to increase the window size, or use hotkey r, or select from the Create menu),
then left-click to create the poly rectangle. Monitor the dX and dY values on the top of the
window to help with the size.
iv. Now add diffusion for the source & drain regions. This is done by drawing DIFF directly
across the channel (it is understood that this creates a transistor and diffusion will not be
place in the channel region, and the oxide under the poly will be reduced to the thin gate
oxide in the channel region). The DIFF should be exactly 5u (for device width) and long

enough for the source & drain contacts. Note under 4.1.6 CONT, rule CO.W.1 shows that
contacts must be a fixed 0.4u wide, and CO.C.1 shows 0.3u min spacing to the channel and
CO.E.1 shows min DIFF enclosure of the contact is 0.15u. A first estimate on the DIFF
length is 2.1u.
v. Select DIFF, Rectangle, create 5u x 2.1u box for the pmos device. Use the hotkey z for
zoom, arrow keys for panning the window, hotkey k for a ruler, and f for fit design in window.
Also, hotkey m is useful for moving the DIFF box and centering over the gate poly, F6 for
redrawing.
vi. Follow similar procedures to draw in 0.4u x 0.4u CONT (contacts) up and down the diffusion
spaced by 0.4u and add a contact for the poly gate (note that the POLY1 must enclose
CONT by 0.2u on each side, rule CO.E.2). For the CONT in diffusion, it will be useful to use
the hotkey c for copy. To auto-generate an array, place the mouse over a single 0.4u x 0.4u
CONT, hit c, then hit F3, fill in the pop-up for 5 rows, 1 column, TAB, the pull the mouse
down, place the first copy with left-click, then place the 2nd copy with 0.4u separation. You
will see all 5 in the string get placed. Again, the ruler k and move m will be useful (and K
(shift-k) for remove rulers). Another useful command is stretch (hotkey s). Place the
mouse over the edge of one side of a rectangle, hit s, then move the mouse to stretch a
rectangle (e.g. DIFF or POLY1) in that direction. Finally, you can use default contacts from
the library (with min dimensions). In the layout window, use the hotkey i for insert -->
Browse --> TECH_C35B4 --> P1_C --> symbolic --> then place into your layout. This is a
standard POLY1 contact (to metal 1). It shows as a hierarchical box. To show all layers in
the hierarchy, hit the hotkey F (shift-f). The result with DIFF, POLY1 and CONT is shown
below.

vii. Now, we have to designate the DIFF as p-type using the PPLUS layer and add n-well
contacts. For the inverter, the n-well is tied to the pmos source, so we can abut the ndiffusion for the n-well contacts up to the pmos source. The source can be either side at this
point, lets use the left side. Add an additional column of DIFF abutted to the pmos source
and copy your contacts over. Next, add a PPLUS rectangle to designate the DIFF of the
pmos as p-type and NPLUS over the DIFF and contacts you just added to designate as ntype for the NWELL contacts. Now, draw in the n-well for the device (NTUB, must enclose
PDIFF by 1.2u, rule OD.C.4, and NDIFF by 0.2u, rule OD.C.1). Again, whether DIFF is
NDIFF or PDIFF is determined by the NPLUS or PPLUS designation. Finally, draw metal
one over your source & drain contacts and gate contact. The complete pmos device is
shown below:

viii. To check your design for layout rule violations, perform a design-rule-check (DRC).
1. Verify --> DRC... if you leave all defaults and click OK, you will get many
warnings and errors, some due to real rule violations you may have and others
due to complete layout constraints that are not relevant at this time (you can try
this by clicking OK). To limit messages to only relevant ones
1. select Set Switches in the DRC window --> select (with shift key):
2. no_coverage: you can always use this, only applies to final layout
3. no_erc & no_info: this can be used at first to focus only on design rule
violations
2. Run DRC with these three switches set. You will see white markers placed in the
layout on your errors. To zoom in on the errors, select: Verify --> Markers -->
Find..., then click box: Zoom to Markers, then click Next. This process will take
you to each violation with a pop-up window showing the reason (use shift-z to
zoom out).
3. Correct all of your violations so there are no errors. Again, the stretch s
command and ruler k are useful. It is also useful to re-create some shapes using
the Polygon (hotkey P), since each time you click your mouse the dX and dY
reference is reset, making it easy to set each dimension according to the rules.
4. Re-run DRC with only the no_coverage switch set. This should give you three
warnings:

5. Floating gate is due to no pin on the gate or other connection; No Stamped

Connections: is due to a lack of substrate contacts; and hot nwell is a term for nwells that are not tied to vdd!. We can remove the first and last errors by
assigning pins to vdd!, in and out. The No Stamped Connection error will remain
until we complete the nmos device with a substrate contact. In general, you
layouts should be DRC Clean with only the no_coverage switch set, meaning
no errors. To delete error markers, select: Verify --> Markers --> Delete All -->
OK.
ix. Add pins by selecting: Create --> Pin from the menu. Click Display Pin Name Options -->
height to 0.1 (so labels are not so large). Write in terminal name: vdd!, type: inputoutput,
TAB, then move your mouse into the layout window and place the vdd! pin on the MET1 of
your pmos source. Repeat for terminals: in (input) and out (output). The design with labels
is shown below.

g. Repeat the same procedure to draw the nmos. Use dimensions of 2.5u x 0.35u (dont forget to
change the schematic as well). Again, draw the POLY1 gate, DIFF, source & drain contacts
(CONT), DIFF and CONT for the substrate contact, then NPLUS over DIFF in nmos source & drain
and PPLUS for DIFF in substrate contact. Add a pin for the nmos source and substrate contact
labeled: gnd!.
i. Fix all errors until your layout is DRC Clean with only the no_coverage switch (see below).

2. Layout verification: finally, we need to verify that the layout matches the schematic, and later use extracted
views with parasitic elements for more accurate simulation.
a. Adjust device sizes your schematic to match the layout you just completed (if not done already).
b. In the layout window: Verify --> Extract ... Leave all defaults, OK.

c. Select: Verify --> LVS. If you get a pop-up window complaining of directory contents differences,
select: Use form contents, OK. In the LVS window, fill in as below to compare the schematic view
with the extracted view (just created). Click Run. You should get a pop-up stating that LVS has
succeeded. Click Output to see the results, which should state that the netlists match. You can also
select Info to view the logfile (especially useful when LVS fails) and to view detailed info on the
schematic and extracted views.

d. At this point, if you open the extracted view of the inverter (from Library Manager), you can crossprobe between the schematic and layout as well. Open the schematic & extracted views of inv1 -->
in the extracted view, select Verify --> Probe, then click Cross Probe Matched, then click on the
schematic view window, followed by Add Net in the Probe window. You are now asked to select a
net in the schematic window. When you click on a net (e.g. out), it will highlight in both the
schematic and layout views.