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UNIVERSITI TEKNOLOGI MALAYSIA
DECLARATION OF THESIS / UNDERGRADUATE PROJECT PAPER AND
COPYRIGHT
Author’s Full Name

:

NUR ERSHADIAH BINTI ABDUL HADI

Date of Birth

:

12th DECEMBER 1988

Title

:

DESIGN AND CHARACTERIZATION OF
BIAXIAL STRAINED SILICON CMOS

Academic Session

:

2010/2011

I declare that this thesis is classified as:

CONFIDENTIAL

(Contains confidential information under the Official
Secret Act 1972)*

RESTRICTED

(Contains restricted information as specified by the
organisation where research was done)*

OPEN ACCESS

I agree that my thesis to be published as online open
access (full text)

I acknowledged that Universiti Teknologi Malaysia reserves the right as follows:
1. The thesis is the property of Universiti Teknologi Malaysia.
2. The Library of Universiti Teknologi Malaysia has the right to make copies for the
purpose of research only.
3. The Library has the right to make copies of the thesis for academic exchange.
Certified by:

SIGNATURE

SIGNATURE OF SUPERVISOR

881212-01-6032

PROF. DR. RAZALI ISMAIL

(NEW IC NO. / PASSPORT NO.)

Date :

NOTES :

20TH MAY 2011

NAME OF SUPERVISOR

Date :

20TH MAY 2011

* If the thesis is CONFIDENTIAL or RESTRICTED, please attach with the letter from
the organisation with period and reasons for confidentiality or restriction.

DESIGN AND CHARACTERIZATION OF BIAXIAL
STRAINED SILICON CMOS

NUR ERSHADIAH BINTI ABDUL HADI

A thesis submitted in partial fulfillment of
the requirements for the award of the degree of
Bachelor of Engineering (Electrical-Microelectronics)

Faculty of Electrical Engineering
Universiti Teknologi Malaysia

MAY 2011

i

“I hereby declare that I have read this thesis and in my opinion this thesis is
sufficient in terms of scope and quality for the award of the degree of Bachelor of
Engineering (Electrical - Microelectronics).”

Signature

:

Supervisor

:

Prof. Dr. Razali Ismail

Date

:

20th MAY 2011

ii

I declare that this thesis entitled “Design and Characterization of Biaxial Strained
Silicon CMOS” is the result of my own research except as cited in the references.
The thesis has not been accepted for any degree and is not concurrently submitted in
candidature of any other degree.

Signature

:

Name of Candidate

:

NUR ERSHADIAH

Date

:

20th MAY 2011

iii

Specially dedicated to
my beloved mother, father, and sisters
and someone who inspired me all of these years.

iv

ACKNOWLEDGEMENT

Alhamdulillah, the author would like to express her utmost gratitude to the
project supervisor, Prof. Dr. Razali Bin Ismail for his ultimate dedication of supervision,
guidance, and motivation to the author to complete the project. His advices and
motivations have kept the author in the track and achieve the aim of the project.
Appreciation should also be extended to doctoral candidate, Miss Kang Eng
Siew becoming the author’s mentor besides her selfless help and guidance throughout
this project. Not to forget, Mr. Yeap Kim Ho from Universiti Tuanku Abdul Rahman for
his guidance and help to the author.
Next, the gratitude should be expressed to the author’s beloved parents’, family
and sisters. The support and love given by them has inspired the author to finish the
project on the estimated time.
Lastly, to the author’s friends, Akmal Hayati Rusli, Nurulsyahida Ishak, Sabariah
Mohamad Ali, Aimie Amalina Azman, Siti Zubaidah Tumari, Norsaradatul Akmar
Zulkifli, Nabilah Yusoff, Nadiah Abdul Razak, Nurul Nadia Ramli, Wan Haszerila Wan
Hassan, Nursyifa Zainal Abidin, Noraliah Aziziah Md.Amin, Hafiz Izzuddin Julaihi,
Muhd. Firdaus Yusof, and lots more, the author would like to thank them for their
support, love and trust besides sharing the knowledge and motivated her all of this
while. Thank you to all, very much.

v

ABSTRACT

The challenging improvement of semiconductor devices from conventional
type is the result of the high demand for smaller and faster electronics devices
nowadays. A lot of effort has been made to overcome the scaling problem, which
seems to obey Moore’s Law. Since scaling has reached its limit, strained silicon is
the latest alternative to achieve the same result as scaling down, without the need to
alter the size of the electronic devices. The device performance can be improved by
introducing strained Silicon layer on MOSFET. The aim of introducing nano regime
strained silicon MOSFET is to increase the carrier mobility and improving the speed
of the device. However, researchers are also facing certain limitation such as short
channel effects that is unavoidable. The objective of the study is to conduct a
research on biaxial strained silicon Complementary MOSFET (CMOS). The project
will be aided by SILVACO’s International® Technology Computer Aided Design
(TCAD) tools. The process is divided into two parts, that are design and fabrication
by using SILVACO’s ATHENA software, and the last process will be the
characteristics analysis, aided by SILVACO’s ATLAS software. The result analysis
of electrical properties such as subthreshold swing, drain induced barrier lowering
(DIBL) are compared to the conventional CMOS. Conclusions with some further
suggestions are presented in this project.

vi

ABSTRAK

Bagi memenuhi permintaan yang tinggi terhadap peranti elektronik yang kecil
dan laju telah menghasilkan era penambahbaikan peranti semikoduktor konvensional.
Semakin banyak usaha telah dijalankan bagi mengatasi masalah pengskalaan, dimana ia
mematuhi Moore’s Law. Kebelakangan ini, pengskalaan dilihat semakin mencapai tahap
limitasi, maka, silicon tegang merupakan kaedah terkini untuk mencapai hasil yang sama
seperti pengskalaan, tanpa perlu mengubahsuai saiz peranti elektronik. Prestasi peranti
elektronik bolek diperbaiki dengan menambah lapisan silicon tegang didalam MOSFET.
Tujuan menambah lapisan nano silicon tegang didalam MOSFET adalah untuk
menambah pergerakan pembawa dan menambahbaik kelajuan peranti. Walau
bagaimanapun, penyelidik menghadapi beberapa limitasi seperti kesan saluran pendek
yang tidak dapat dielakkan. Objektif projek ini adalah untuk menjalankan kajian
terhadap dwipaksi silicon tegang CMOS. Projek ini dibantu oleh SILVACO’s
International® Technology Computer Aided Design (TCAD) tools. Proses telah
dibahagikan kepada dua bahagian, iaitu rekabentuk dan simulasi menggunakan perisian
SILVACO’s ATHENA, dan proses terakhir adalah analisis cirri-ciri peranti, dibantu oleh
perisian SILVACO’s ATLAS. Analisis terhadap hasil dapatan dalam sifat-sifat elektrik
seperti subthreshold swing, drain induced barrier lowering (DIBL) dibandingkan
dengan CMOS konvensional. Kesimpulan beserta cadangan untuk penambahbaikan turut
disertakan didalam projek ini.

vii

TABLE OF CONTENT

CHAPTER

1

TITLE

PAGE

DECLARATION

i

DEDICATION

iii

ACKNOWLEDGEMENT

iv

ABSTRACT

v

ABSTRAK

vi

TABLE OF CONTENT

vii

LIST OF TABLES

xii

LIST OF FIGURES

xiii

LIST OF ABBREVIATIONS

xvii

LIST OF SYMBOLS

xix

LIST OF APPENDICES

xx

INTRODUCTION
1.1 Background of Study

1

1.2 Problem Statement

3

1.3 Objectives

4

1.4 Scope

4

1.5 Summary of Previous work

5

viii

2

THEORY AND LITERATURE REVIEW
2.1 Overview of MOSFET
2.1.1 NMOSFET

7
8

2.1.1.1 NMOS Structure

8

2.1.1.2 NMOS Operation

9

2.1.2 PMOSFET

12

2.1.2.1 PMOS Structure

12

2.1.2.2 PMOS Operation

13

2.1.3 CMOS
2.2 Short Channel Effect

13
15

2.2.1 Drain Induced Barrier Lowering (DIBL) &
Punchthrough

16

2.2.2 Surface Scattering

17

2.2.3 Velocity Saturation

18

2.2.4 Impact Ionization

19

2.2.5 Hot Electrons

20

2.3 Strained Silicon

20

2.3.1 Theory and Concept

21

2.3.2 Strained Silicon MOSFET

22

2.3.3 Types of Strained Silicon MOSFET

23

2.3.3.1 Uniaxial Strained Silicon MOSFET

23

2.3.3.1 Biaxial Strained Silicon MOSFET

23

2.4 Advantages of Strained Silicon MOSFET

24

ix

3

2.4.1 Carrier Mobility Enhancement

25

2.4.2 Lower the Resistance and Power Consumption

25

2.4.3 New Gate Stack Material Needs Delay

25

METHODOLOGY AND APPROACH

26

3.1 Methodology

26

3.2 Flowchart

28

3.3 TCAD Tools

30

3.3.1 Simulation Tools
3.3.1.1 TCAD Software

4

30
31

3.3.1.1.1 DECKBUILD: Interactive Deck
Development and Runtime Environment

31

3.3.1.1.2 TONYPLOT: 1D/2D Interactive
Visualization Tools

32

3.3.1.1.3 MASKVIEWS

33

DESIGN OF CONVENTIONAL AND STRAINED
SILICON MOSFETS
4.1 Design of MOSFET
4.1.1 ATHENA – Design of Biaxial Strained Silicon
MOSFETs

35
36

4.1.1.1 Mesh Definition and Substrate Initialization

39

4.1.1.2 Epitaxial Layer

40

4.1.1.3 Deposition of Silicon and SiGe Layers

41

4.1.1.4 Formation of Gate Oxide

42

4.1.1.5 Threshold Voltage Adjustment

44

x
4.1.1.6 Deposition and Patterning of Polysilicon

44

4.1.1.7 Polysilicon Oxidation and Doping

46

4.1.1.8 Spacer Oxide

48

4.1.1.9 Source and Drain Annealing

48

4.1.1.10 Metallization and Contact Patterning

50

4.1.1.11 Structure Reflection and Electrode Labeling

50

4.1.1.12 TONYPLOT – Concentration View and
Measurement

52

4.1.2 MASKVIEWS – Design of Conventional and
Biaxial Strained Silicon Complementary MOSFET

5

6

54

CHARACTERIZATION OF BIAXIAL STRAINED
SILICON MOSFETS

62

5.1 ATLAS – Device Simulation Framework

62

5.2 Device Characterization using ATLAS Simulator

64

5.3 Drain Current versus Gate Voltage (ID vs.VGS)

65

5.4 Drain Current versus Drain Voltage (ID vs. VDS)

68

5.5 Drain Induced Barrier Lowering

70

5.6 Subthreshold Swing

72

5.7 Result Comparison

76

CONCLUSION

77

6.1 Project Summary

77

6.2 Suggestion for Future Work

79

6.2.1 Reducing Channel Length

79

6.2.2 Capacitance-Voltage Characteristics

79

xi

6.2.3 Strained Silicon in Silicon-On-Insulator (SOI)

80

6.2.4 MOSFET with Side Gates

80

6.2.5 Twin Well with Field Oxide Technology (FOX)

81

REFERENCES

83

APPENDICES

86

xii

LIST OF TABLES

TABLE NO.

TITLE

PAGE

1.1

Summary of previous researches

6

2.1

Type of Stress Needed for NMOS and PMOS

22

4.1

Specification of simulated devices

54

5.1

Comparison of DIBL with different channel length

72

5.2

Comparison of Subthreshold swing with various channel
length

75

5.3

Comparison between conventional and biaxial strained
silicon MOSFETs

76

5.4

Comparison between different channel lengths of
strained silicon MOSFETs

76

6.1

Summary of device characteristics

78

xiii

LIST OF FIGURES

FIGURE NO.

TITLE

PAGE

2.1

Basic MOSFET structure

7

2.2

NMOS structure

9

2.3

Induced NMOS

10

2.4

Cutoff region of NMOS operation

11

2.5

Linear/Triode region of NMOS operation

11

2.6

Saturation region of NMOS operation

11

2.7

PMOS structure

12

2.8

CMOS structure

13

2.9

Channels formation in CMOS

14

2.10

a) NMOS part b) PMOS part

15

2.11

Several ways to reduce punchthrough effects (a) delta
doping (b) halo (c) pocket implants

17

2.12

Inversion layer, depletion region and the surface
scattering effect

18

2.13

Hot electron effects

20

2.14

(Left) Pure Silicon and Silicon Germanium (Right)
Strained Silicon after being matched with Silicon
Germanium

21

2.15

The direction of strain

21

2.16

Uniaxial Strained Silicon MOSFET

23

xiv

2.17

Biaxial Strained Silicon MOSFET

24

3.1

Flowchart of the project

28

3.2

Segmentation of project

29

3.3

SILVACO TOOLS used in this project

29

4.1

The flow of designing a conventional MOSFET

37

4.2

The flow of designing biaxial strained Silicon MOSFET

37

4.3

The view of DECKBUILD

38

4.4

Codes for generating mesh

39

4.5

Codes for generating substrate material

40

4.6

Codes for depositing epitaxial layer

41

4.7

View of Epitaxial Layer and Substrate with Grid
Definition

41

4.8

Codes for depositing Silicon and SiGe layer

42

4.9

Silicon and SiGe layer

42

4.10

Codes for diffusing gate oxide

43

4.11

The formation of Oxide layer for Gate Oxide

43

4.12

Codes for extracting the thickness of gate oxide

43

4.13

Codes for implanting the doping for threshold
adjustment

44

4.14

Codes for depositing Polysilicon

45

4.15

Layer of Polysilicon

45

4.16

Codes for patterning Polysilicon

45

4.17

Etched Polysilicon

46

4.18

Codes for Polysilicon oxidation

46

xv
4.19

Oxidized Polysilicon

47

4.20

Codes for Polysilicon doping

47

4.21

Codes for depositing spacer oxide

48

4.22

Codes for implanting and annealing source and drain

49

4.23

The view of source and drain region/junction

49

4.24

Codes for depositing and patterning Aluminium

50

4.25

Codes for reflecting structure

51

4.26

Reflected structure

51

4.27

Codes for labeling structure and creating output file

52

4.28

Codes for viewing the structure

53

4.29

Concentration view and channel length measurement

53

4.30

The first trial of creating a bulk CMOS

55

4.31

Flowchart of creating a conventional CMOS

56

4.32

Steps of processes of fabricating conventional CMOS

57

4.33

MASKVIEWS Base Window

58

4.34

A 0.35 um conventional CMOS GDS layout

58

4.35

Top view and side view of 0.35um CMOS using
MASKVIEWS

59

4.36

Structure obtained from GDSII layout

59

4.37

Concentration view of 0.35um CMOS

60

4.38

Flowchart of creating biaxial strained silicon CMOS

61

5.1

ATLAS inputs and outputs

63

5.2

Order of Statement in ATLAS Simulation

64

5.3

ID-VGS of NMOS and strained Silicon NMOS at VDS =
0.1V

66

xvi
5.4

ID-VGS of PMOS and strained Silicon PMOS at VDS =
0.1V

67

5.5

ID-VDS Graph of NMOS

68

5.6

ID-VDS Graph of PMOS

69

5.7

Determining DIBL from graph (a) NMOS (b) PMOS

70

5.8

DIBL effect of conventional MOSFETs

71

5.9

Comparison of DIBL effect between conventional and
strained Silicon MOSFETs

71

5.10

Log ID vs. VGS at VDS = 0.1V

73

5.11

Comparison of subthreshold swing between
conventional and biaxial strained Silicon MOSFETs

74

5.12

Comparison of subthreshold swing with various channel
length

75

6.1

Strained Silicon implemented on Silicon-on-Insulator
(SSOI)

80

6.2

Formation of MOSFET with Side Gates

81

6.3

MOSFET with twin well and FOX technology

82

xvii

LIST OF ABBREVIATIONS

MOSFET

-

Metal Oxide Semiconductor Field Effect Transistor

CMOS

-

Complementary Metal Oxide Semiconductor Field Effect Transistor

RAM

-

Random Access Memory

TCAD

-

Technology Computer Aided Design

DIBL

-

Drain Induced Barrier Lowering

UTM

-

Universiti Teknologi Malaysia

NMOS

-

N-channel Metal Oxide Semiconductor Field Effect Transistor

PMOS

-

P-channel Metal Oxide Semiconductor Field Effect Transistor

SiGe

-

Silicon Germanium

DOS

-

Density of States

GaAs

-

Gallium Arsenide

FYP

-

Final Year Project

PBL

-

Problem-Based Learning

sSi

-

Strained Silicon

EDA

-

Electronic Design Automation

IC

-

Integrated Circuit

GUI

-

Graphical User Interface

SOI

-

Silicon On Insulator

xviii
VLSI

-

Very Large Scale Integrated Circuit

STI

-

Shallow Trench Isolation

DC

-

Direct Current

AC

-

Alternating Current

HEMT

-

High Electron Mobility Transistor

LED

-

Light Emitting Diode

LASER

-

Light Amplification by Stimulated Emission of Radiation

CCD

-

Charge Coupled Device

NVM

-

Non-volatile Memory

xix

LIST OF SYMBOLS

ID

-

Drain current

VDS

-

Drain-to-source voltage

VGS

-

Gate-to-source voltage

VT

-

Threshold Voltage

µ

-

Effective carrier mobility / microns

VSB

-

Source-to-body voltage

VDB

-

Drain-to-body voltage

Leff

-

Effective channel length

S

-

Subthreshold Swing

W

-

Width

L

-

Length

xx

LIST OF APPENDICES

APPENDIX

TITLE

PAGE

A

ATHENA INPUT FILE: 45nm BIAXIAL STAINED
SILICON NMOS

85

B

ATLAS INPUT FILE: DIBL CHARACTERISTICS
OF BIAXIAL STRAINED SILICON NMOS

87

C

ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS
OF BIAXIAL STRAINED SILICON NMOS

89

D

ATLAS INPUT FILE: Id-Vds CHARACTERISTICS
OF BIAXIAL STRAINED SILICON NMOS

92

E

ATHENA INPUT FILE: 45nm CONVENTIONAL
NMOS

94

F

ATLAS INPUT FILE: DIBL CHARACTERISTICS
OF CONVENTIONAL NMOS

96

G

ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS
OF CONVENTIONAL NMOS

98

H

ATLAS INPUT FILE: Id-Vds CHARACTERISTICS
OF CONVENTIONAL NMOS

101

I

ATHENA INPUT FILE: 45nm BIAXIAL STRAINED
SILICON PMOS

103

J

ATLAS INPUT FILE: DIBL CHARACTERISTICS
OF BIAXIAL STRAINED SILICON PMOS

105

K

ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS
OF BIAXIAL STRAINED SILICON PMOS

107

L

ATLAS INPUT FILE: Id-Vds CHARACTERISTICS
OF BIAXIAL STRAINED SILICON PMOS

110

xxi

ATHENA INPUT FILE: 45nm CONVENTIONAL
PMOS
ATLAS INPUT FILE: DIBL CHARACTERISTICS
OF CONVENTIONAL PMOS

112

O

ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS
OF CONVENTIONAL PMOS

116

P

ATLAS INPUT FILE: Id-Vds CHARACTERISTICS
OF CONVENTIONAL PMOS

119

M
N

114

1

CHAPTER 1

INTRODUCTION

1.1 Background of Study

Widely used as electronics signal’s amplifier and switches, Metal Oxide
Semiconductor Field Effect Transistor – MOSFET is a voltage controlled device. Its
physical includes the presence of n-type and p-type material, which is known as NMOS
if the source and drain are made of n-material and PMOS if the source and drain are
made of p-material. In advanced integrated circuit (IC) design, MOSFET is one of the
most common transistors used in both analog and mixed-signal circuits. MOSFET has
the advantages which the switching time is about 10times faster than a bipolar transistor.
MOSFET has a very much smaller switching current; it is less affected by temperature
when compared to bipolar transistor1.

MOSFET family is divided into three most common types, NMOS, PMOS and
CMOS, which consists of both NMOS and PMOS. CMOS – the abbreviation of
Complementary Metal Oxide Semiconductor Field Effect Transistor technology – is
widely used in microcontrollers, microprocessors, static RAM, and also in other digital

2
logic circuits. For its variety usage, it is also been used in analog circuits, such as data
converters, image sensors, and highly integrated transceivers in the communication field.
The most important characteristics of CMOS are its high noise immunity and low static
power consumption.

Silicon is one of nature’s compounds that have been used widely in the
semiconductor technology for years. It is a tetravalent metalloid or semimetal chemical
element that is less reactive than its chemical analog carbon. Silicon comes in atomic
number of 14. The most natural-famous form of silicon found in nature in dusts and
sands is silicon dioxide or silicates. Because of its native oxide that is easily grown in a
furnace and it forms a better dielectric and semiconductor interface compared to the
other material, silicon remains as the most popular material used in semiconductor
technology. Strained silicon MOSFET has been known for increasing the speed,
mobility and reducing power consumption of conventional MOSFET2.

Strained silicon is formed by matching a pure layer of silicon over a substrate of
silicon germanium, SiGe. The silicon atoms inside the pure silicon will be stretched out
and aligned according to the atomic structure of the silicon germanium. The atoms will
be arranged to be far apart, thus will reduce the atomic forces. The atomic forces
influence the movements of electrons through the silicon, thus, when strained silicon is
used in a transistor, the transistor’s performance will be increased. The electrons can
move almost 70% faster in the strained silicon compared to the pure one, which allowing
the transistor to operate 35% faster than usual. The mobility enhancement obtained by
applying appropriate strain provides higher carrier velocity in MOS channels. Under a
fixed supply voltage and gate oxide thickness, this will result in a higher drive current3.

A general term for Si1-xGex is SiGe, which is widely used in the semiconductor
technology to be matched with silicon and produced strained silicon. Since the

3
fundamental scaling has its own limitation caused by the short channel effect, SiGe
extends the chance of improving the performance of MOSFETs. The 4.2% lattice
mismatch between Si and SiGe layer is used to create strained layer to enhance the
carrier transport in the MOSFET’s channel4. Theoretical calculations5-9 predict electrons
and holes mobility enhancements in strained Si MOSFETs.

In this project, biaxial strained silicon CMOS has been chosen to be studied to obtain
the characteristics of biaxial strained silicon CMOS and to compare it with the
performance of the conventional CMOS. Recent studies in semiconductor technology
specialized in strained silicon has proven that the performance of strained silicon CMOS
is much better than the conventional CMOS.

1.2

Problem of Statement

The advancement of semiconductor technology demands for faster and smaller
electronic devices. The scaling of MOSFET has approaching nanoscale, and limitations
arose as short channel effect becomes the main obstacle in producing smaller devices.
Thus, strained silicon has been introduced to improve the performance of CMOS,
without altering or reducing the length of the channel.

It is very costly to fabricate the device and to perform experimental analysis.
After the first fabrication, it takes some time to obtain the characteristics, and when the
desired result could not be obtained, another fabrication of the device will be needed.
Instead of a real life fabrication, virtual fabrication is the alternative way to reduce the
cost and to obtain the accurate result of electrical properties. TCAD tools are one of the
alternatives as the software can be used to fabricate and to analyze the electrical
properties of the virtual design.

4
1.3

Objectives

1. To conduct a study on biaxial strained silicon CMOS.
2. To design and simulate biaxial strained silicon CMOS by using SILVACO’s
ATHENA software.
3. To conduct an investigation on the electrical characteristics of biaxial
strained silicon CMOS by using SILVACO’s ATLAS software.
4. To compare the characteristics between the conventional and strained silicon
CMOS.

1.4 Scope

Biaxial strained silicon CMOS is modified from the conventional CMOS and the
characteristics of the device is studied. The design and the fabrication process of biaxial
strained silicon CMOS is done by using SILVACO’s ATHENA software. The
SILVACO’s ATLAS software is used to simulate and to obtain the device’s
characteristics. Lastly, analysis is done to the result to investigate the electrical
properties of the biaxial strained silicon CMOS, and compared it to the conventional
one, and the project is concluded.

Some electrical characteristics that are studied in the project including the
threshold voltage, subthreshold swing, and drain induced barrier lowering (DIBL). For
every step in simulation process, caution has been taken to ensure the accurate CMOS
that has been designed is simulated.

5
1.5

Summary of Previous Work

Previous research held by UTM students and researchers focused on PMOS and
NMOS. In the year of 2007, some researches were done on uniaxial strained silicon
PMOS

10-11

. In 2010, Biaxial strained silicon NMOS has been designed virtually, using

TCAD tool (Silvaco International)

12

. In fact, a few research has been conducted to

explore the enhancement of performance of MOSFET devices worldwide, thus
conducting a study on biaxial strained silicon CMOS is relevant for undergraduates
project.

The study focused on 45nm biaxial strained silicon MOSFET, since the technology
now has reach 32nm nano regime. Former research proved that the study is still valid
and can be done extensively. The results of the researches are summarized in Table 1.1
to compare with the result in this project.

6
Table 1.1: Summary of previous researches
Characteristics

Threshold Voltage
(Vd=0.1V)

Subthreshold Swing
(mV/dec)

DIBL (mV/V)

Mobility enhancement
at Vgs=3V (%)

Strained silicon PMOS
(uniaxial)

Strained silicon NMOS
(biaxial)

-0. 596894V (100nm)10
-0.511299V (71nm) 11

0.571733(90nm)12
0.581068(150nm)12

186.153 10

112.8 12

693.564 10 / 303.411

354 12

25.65% 10
-Hole mobility enhancement

35.7% 12
-Electron mobility
enhancement

7

CHAPTER 2

THEORY AND LITERATURE REVIEW

2.1

Overview of MOSFET

Metal Oxide Semiconductor Field Effect Transistor is commonly known as
MOSFET, is capable of voltage gain and signal-power gain. MOSFET is used
extensively in digital circuit applications. Since it is relatively small in its sizes,
thousands of devices can be fabricated in a single integrated circuit. All MOSFET are
actually transistors, which consist of metal, Silicon Oxide, silicon, n+ material or p+
material. The heart of the MOSFET is a metal-oxide-semiconductor structure known as
a MOS capacitor1.

Figure 2.1: Basic MOSFET structure

8
MOSFET is divided into three main types, PMOS, NMOS and CMOS. MOSFET
operates when a voltage is applied across it. Let us review an example of a p-type
semiconductor. When a positive voltage is supplied at the gate, it creates a depletion
layer by forcing the positive charged majority carrier (in this case – hole for p-type)
away from the gate insulator interface, and leave an exposed carrier-free region of
negative charged acceptor. When the voltage supplied at the gate is high enough, high
concentration of negative charge carrier will form an inversion layer – a very thin layer –
next to the interface between the insulator and semiconductor.

2.1.1 NMOSFET

NMOSFET – N-channel Metal Oxide Semiconductor Field Effect Transistor or
simply NMOS is a type of MOSFET that will have an inversion layer of n type material,
or simply said n-channel. It is one of MOSFET family member that is used extensively
as switches and in digital logic design.

2.1.1.1 NMOS Structure

NMOS is built with p-type material as the substrate. The plus (+) notation on n+
indicates the n-type material/region are heavily doped material. An insulator which is
made of a thin layer of silicon oxide (SiO2) is grown on the substrate’s surface, and
covering the area between the source and drain. Metal is deposited at four different
terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).

9

Figure 2.2: NMOS structure

2.1.1.2 NMOS Operation

When a positive voltage is applied at the gate terminal, it causes the free holes
(positive charges) to be repelled from the region of the substrate, under the gate. Then,
these holes are push downwards into the substrate, creating a carrier depletion region.
The depletion region is made from the negative charges, due to the neutralizing holes
that have been pushed down. The gate voltage, which is positive, will attract electrons
from the n-wells, forming an n channel that connects the source and the drain. Thus,
current will flow through the induced region. The current flow from drain to source,
since the current, iD is carried by free electrons from source to drain. The current
magnitude depends on the electrons’ density in the channel, which depends on V GS >
VT.

If VGS > VT, the channel will increases, and the resistance across the channel is
reduced or the conductance is increased. The conductance of the channel is proportional
to the excess gate voltage, which is known as effective voltage.

10

Figure 2.3: Induced NMOS

For summary, NMOS operates at:
I.

Cutoff region – When VGS < VT, there is no inversion layer present under
the surface. At VDS = 0, the source and drain depletion regions are
symmetrical. A positive VDS reverse biases the drain substrate junction,
hence the depletion region around the drain widens, and since the drain is
adjacent to the gate edge, the depletion region widens in the channel.
However, there is no current flows even for VDS > 0, since no conductive
channel is present and ID = 017.

II.
III.

Linear/Triode region when VDS < VGS – VT
Saturation region when VDS > VGS – VT

11

Figure 2.4: Cutoff region of NMOS operation

Figure 2.5: Linear/Triode region of NMOS operation

Figure 2.6: Saturation region of NMOS operation

12
2.1.2 PMOSFET

PMOSFET – P-channel Metal Oxide Semiconductor Field Effect Transistor or
simply PMOS is a type of MOSFET that will have an inversion layer of p type material,
or simply said p-channel. It is one of MOSFET family member that is used extensively
as switches and in digital logic design.

2.1.2.1 PMOS Structure

PMOS is built with n-type material as the substrate. The plus (+) notation on p+
indicates the p-type material/region are heavily doped material. An insulator which is
made of a thin layer of silicon oxide (SiO2) is grown on the substrate’s surface, and
covering the area between the source and drain. Metal is deposited at four different
terminals, which are labeled as Source (S), Gate (G), Drain (D), and Body (B).

Figure 2.7: PMOS structure

13
2.1.2.2 PMOS Operation

A PMOS operates in a similar way as the NMOS, except that V GS, VDS and the
threshold voltage VT are negative values. The current flow through the channel, iD enters
the source terminal, and leaves through the drain (opposite to the NMOS)
For summary, the PMOS device operates at:
I.

Cutoff region – the device is turned off when VGS > VT, and turned on
VGS < VT.

II.
III.

2.1.3

Linear/Triode region when VDS < VGS + VT
Saturation region when VDS ˃ VGS + VT

CMOS

CMOSFET – Complementary Metal Oxide Semiconductor Field Effect
Transistor or simply CMOS is a device that consists of both PMOS and NMOS in its
structure.

Figure 2.8: CMOS structure

14
The PMOS part has been designed so that the PMOS can only receive an input,
either from the source (voltage source) or from the other PMOS transistor. The NMOS
part works similarly. It can only receive an input either from the ground, or from the
other NMOS transistor.

In the PMOS part, the composition of its structure has created a low resistance
every time a low voltage is applied through it, and similarly, when a high voltage is
applied, it creates a high resistance in it. Contrary, in the NMOS part, when a low
voltage is applied, it creates a high resistance and when a high voltage is applied on it, it
creates a low resistance.

Figure 2.9: Channels formation in CMOS

There are two cases of the operation of CMOS device, when a low voltage is
applied, and when a high voltage is applied. Both cases have a similar flow of operation.

15

Figure 2.10: a) NMOS part b) PMOS part

a) When low voltage is inserted: At NMOS part, if the input is a low voltage
supply, the NMOS creates a high resistance, and it prevents the voltage from
leaking into the ground. At the PMOS part, if the input is low voltage, it allows
the input to go through the PMOS transistor straight to the output. The output
will be a high voltage.
b) When high voltage is inserted: When a high voltage is inserted, PMOS transistor
will produce a high resistance and it will automatically block the voltage source
from the output. At the NMOS part, it will be a low resistance, and allows the
output to move from the drain to the ground. The output will eventually register
as a low voltage.

2.2

Short Channel Effect

If the channel length of a MOSFET is the same order of magnitude as the depletionlayer widths (xdD, xdS) of the source and drain junction, the MOSFET is considered as
short MOSFET. To improve the operational speed of a device and to increase the
number of components per chip, the channel length should be altered. Unfortunately, the
short channel effect will arise when the channel length, Leff is reduced. Two phenomena
are attributed by the short channel effects, which are the limitation imposed on electron

16
drift characteristic in the channel, and the modification of the threshold voltage due to
the shortening channel length3. Basically, there are five significant short channel effects
that can be observed, which are the drain induced barrier lowering (DIBL) and
Punchthrough, surface scattering, velocity saturation, impact ionization and hot
electrons.

2.2.1

Drain induced barrier lowering (DIBL) & Punchthrough

……………. (1)

Or

.…………… (2)

Based on the equations, when the depletion regions surrounding the drain
extends to the source, until the two depletion layer can merge (xdS + xdD = L),
punchthrough will eventually occurs. Thinner gate oxides, larger substrate doping,
shallower junctions, and obviously with longer channels can minimized the effects of
punchthrough3. Creating and sustaining the inversion layer on the surface of a MOSFET
will influence the current flows in the channel. When the gate bias voltage is not
sufficient to invert the surface (i.e. VGS<VT0), a potential barrier will block the flow of
the carriers (electrons) in the channel. By increasing the gate voltage, it will reduced the
potential barrier and, thus, allowing the carriers to flow under the influence of the
channel electric field. In small-geometry MOSFETs, the gate-to-source voltage VGS and
the drain-to-source voltage VDS are controlling the potential barrier. Once the drain
voltage is increased, the potential barrier in the channel will decreases, creating an effect
called drain induced barrier lowering (DIBL). Electrons can flow between the source

17
and drain when the potential barrier is reduced, even if the VGS is lower than VTO
(threshold voltage). The current that flows under the condition of V GS<VTO is called a
sub-threshold current.

There are several ways to reduce the punchthrough effect, but the simplest way is
to increase the overall bulk doping level. As the doping in the bulk increases, the drain
and source depletion regions will become smaller, and it will not establish a parasitic
current path. Unfortunately, this method is not the most efficient one since increasing the
bulk doping will increase the subthreshold swing at the same time. Some other method
that will not affecting subthreshold swing are delta doping, halo and pocket implants.

Figure 2.11: Several ways to reduce punchthrough effects (a) delta doping (b) halo (c)
pocket implants

2.2.2

Surface Scattering

Due to the lateral extension of the depletion layer into the channel region, the
channel length becomes smaller, the longitudinal electric field component (Ɛx) increases,
and the surface mobility becomes field-dependent. Since the carrier transport in a
MOSFET is confined within the narrow inversion layer and the surface scattering cause
reduction of the mobility, the electrons move with great difficulties, parallel to the

18
interface. This will results the average surface mobility to become about half as much as
that of the bulk mobility, even for small values of Ɛx. Surface scattering is the collisions
suffered by the electrons that are accelerated toward the interface by Ɛx3.

Figure 2.12: Inversion layer, depletion region and the surface scattering effect

2.2.3

Velocity Saturation

Short channel devices’ performance is also affected by velocity saturation.
Velocity saturation reduces the transconductance of the device, when it operates in the
saturation mode. At a very low longitudinal electric field, Ɛx, the electrons drift velocity
varies linearly with the electric field intensity. As the longitudinal electric field increase
and exceeds above 104 V/cm, the drift velocity will increase slowly and approaches a
value of saturation of vDE (sat) = 107 cm/s around Ɛx of 105 V/cm, at the temperature of
300K. Instead of the pinch off, the drain current is actually limited by velocity
saturation. It occurs when the dimensions of the short channel device is scaled, without

19
lowering the voltage bias. The maximum gain that is possible for a MOSFET, by using
VDE (sat), can be defined as
.................. (3)

2.2.4

Impact Ionization

With the presence of high longitudinal fields that generate electron-hole pairs,
impact ionization occurs when the high velocity of electrons exist. By impacting on
silicon atoms and ionizing the atoms, impact ionization occurs, especially in NMOS.
Most of the electrons are attracted by the drain, while the holes will enter the substrate to
form an art of the parasitic substrate current3.

The source region plays the role of the emitter, the drain region plays the role as
the collector, and the region between the source and the drain plays the role as the base
of an npn. When the source is collecting the holes, the corresponding hole current will
create a voltage drop, right in the substrate material. The normal reverse biased
substrate-source pn junction of 6V will conduct appreciably. Only then electrons can be
injected from the source to the substrate3, most likely to be similar as electrons that have
been injected from the emitter to the base. As the electrons travel towards the drain, it
gained enough energy to create new electron-hole pairs. If some electrons generated due
to high fields escape from the drain field to travel into the substrate, it will affect the
other devices on the chip and worsen the situation.

20
2.2.5

Hot Electrons

Hot electrons refer to high energy electrons, which enter the oxide layer and trapped,
that will affecting the oxide, to rise to oxide charging. It accumulates with time, and
degraded the performance of the device by increasing the threshold voltage, V T, affects
its conveyed conductance, and affects adversely the gate’s control on the drain current 3.

Figure 2.13: Hot electron effects

2.3 Strained Silicon

Strained silicon is widely used nowadays in semiconductor manufacturing
technology to design Integrated Circuits (IC). It has captured the researchers attention
and vendors heart since it can be found easily anywhere in natural substance.

21
2.3.1

Theory and Concept

Strained silicon is a semiconductor technology that involving the process of
stretching ad compressing physically, the silicon crystal lattice via various means.

Figure 2.14: (Left) Pure silicon and Silicon Germanium (Right) Strained silicon after
being matched with Silicon Germanium

Figure 2.15: The direction of strain
The technique involves the deposition of pure silicon (Si) on the top of a Silicon
Germanium layer (SiGe) with SiGe ratio as Si1-xGex. The atoms in pure silicon will

22
eventually stretched /strained to match the SiGe atoms as SiGe atoms molecular
structure is much wider. The strained silicon obtained after the process have less
resistance compared to the pure one, which leads to the improvement in the device
performance.

It will increases the carrier mobility and improves the electrical

performance of the device without the need of altering them to make it smaller.

2.3.2

Strained Silicon MOSFET

Strained Si (SS) MOSFETs are device structures that take advantage of straininduced enhancement of carrier transport in silicon. When a thin layer of Si is
pseudomorphically grown on a thick, relaxed SiGe layer, the lattice constant of the Si
film conforms to that of the SiGe layer, and the lattice mismatch between Si and SiGe
leads to biaxial tensile strained in the Si layer. If the SiGe layer is fully relaxed and the
Si layer fully strained, the amount of strain in Si is approximately 4.2 x x% where x is
the Ge mole fraction in the SiGe layer13. The type of stress needed for MOSFET is
sectioned in Table 2.1.

Table 2.1: Type of Stress Needed for NMOS and PMOS
Direction

NMOS

PMOS

Longitudinal (along length of channel)

Tension

Compression

Transverse (along width of channel)

Tension

Tension

Compression

Tension

Out of Plane

23
2.3.3

Types of Strained Silicon MOSFET

2.3.3.1 Uniaxial Strained Silicon MOSFET (Substrate Strain)

All 90, 65, and 45nm high performance logic technologies adopted uniaxial
process induced strained silicon. Uniaxial stress could provide a low channel direction in
plane conductivity mass, large out-of-plane in confinement mass, and high in-plane
density of states (DOS) to the ground hole subband14. A tensile capping layer is formed
right on top of the Strained SiGe gate. At the area between source and drain, strained
silicon is introduced.

Figure 2.16: Uniaxial Strained Silicon MOSFET

2.3.3.2 Biaxial Strained Silicon MOSFET (Process-Induced Strain)

Biaxial strain in the lattice structure of a crystalline Silicon is induced when an
epitaxial of a thin Silicon film is grown on top of a relaxed Silicon Germanium (SiGe)

24
substrate15. Strained silicon is introduced at the region between the source and the drain
region, and a relaxed SiGe layer is placed at the top of the bulk, right under the strained
silicon layer. The bottom part of the device will be the silicon substrate layer.

Figure 2.17: Biaxial Strained Silicon MOSFET

2.4

Advantages of Strained Silicon MOSFET

Several advantages have been found by introducing strained silicon in MOSFET It
includes carrier mobility enhancement, lowers the resistance and power consumption,
and the most important thing is that it will delays the new gate stack material needs. The
advantages of strained silicon is indeed should not be taken lightly, since it is the new
hope of improving MOSFETs for better performance.

25
2.4.1

Carrier Mobility Enhancement

The variation of interatomic distance in silicon layer, either tensile or
compressive, would eventually increase the mobility of the devices. By increasing
mobility, the current and the speed required can be maintained. The carriers can move
almost 70% faster in strained silicon, compared to a pure one, which will result a 35%
faster devices.

2.4.2

Lower the resistance and power consumption

Since the interatomic atoms in the strained silicon have been stretched, it allows
electrons to move faster, which means that it creates a lower resistance region.
Fortunately, the power consumption in the device will be reduced as the resistance is
lowered.

2.4.3

New gate stack material needs delay

Strain silicon improves the MOSFET performances without further scaling of
gate dielectric thickness, junction depth or other dimensions of transistor. The silicon
Germanium (SiGe) material could integrate well with silicon. As strained Silicon
products are much more cheaper, it gives a competitive edge over Gallium Arsenide
(GaAs)16.

26

CHAPTER 3

METHODOLOGY AND APPROACH

3.1

Methodology

Several stages in the project were done to complete the project in the estimated
time. Stages were carefully planned to fit the schedule and also the submission of the
project, part by part.
Stage 1: The title, problem, objectives and scope is determined

Problem is determined, and relevant title with objectives and scopes to focus is
chosen.

Outcomes are determined.

Stage 2: Literature studies are conducted

Conduct literature studies on CMOS, strained silicon, biaxial and uniaxial strained
silicon.

Materials such as eBooks, journals and websites are compiled.

27
Stage 3: FYP 1 Seminar

The project’s proposal is presented in front of the panels.

Suggestions were taken into a serious consideration, to improve the project.

Stage 4: TCAD Tools Learning

PBL Lab of SEW 4722 is reviewed to get familiar with the ATLAS and
ATHENA software.

User manual of ATHENA, ATLAS and MASKVIEWS are used extensively to help
the fabrication and characterization process.

Stage 5: Fabrication and Characteristics Simulation

ATHENA is used to design and fabricate the device virtually.

ATLAS is used to investigate the characterization of the device.

MASKVIEWS is used to design the layout and extract information to ATHENA.

Stage 6: Result Analysis

Results is analyzed to conclude the electrical properties of biaxial strained silicon
CMOS.

Results are concluded.

Stage 7: FYP 2 Seminar

Results are presented in front of the panels to be evaluated.

Stage 8: Thesis Writing

Final thesis is written with binding hard cover and submitted to the faculty.

28
3.2

Flowchart

1

2

3

4

•Propose a topic, objective/s, and outcomes.

•Conduct a literature research.
•Collect relevant data.

•Learn TCAD tools - ATHENA
•Learn TCAD tools - ATLAS
•Learn TCAD tools - MaskViews

•Design conventional PMOS and NMOS using ATHENA
•Analyse the characteristics using ATLAS

5

•Design biaxial strained silicon PMOS and NMOS using
ATHENA
•Analyse the characteristics using ATLAS

6

•Compare the characteristics of conventional MOSFET and
the biaxial strained silicon MOSFET.
•Conclude the comparison.

7

•Design a bulk CMOS using MaskViews
•Extract to ATHENA

Figure 3.1: Flowchart of the project

29

Biaxial sSi
CMOS

Conventional &
sSi PMOS

Conventional &
sSi NMOS

CMOS (Layout)

Analyze
Characteristics

Analyze
Characteristics

CMOS
Structure

Figure 3.2: Segmentation of project

SILVACO
ATLAS
SILVACO
ATHENA

SILVACO
MASKVIEWS

PRODUCT

Figure 3.3: SILVACO TOOLS used in this project

30
3.3

TCAD Tools

The software used in the project is originally from SILVACO’s International. It is
divided into three parts, which are the ATHENA software, used for fabrication and
simulation of the device, and ATLAS software, used for investigation of the
characterization of the device, and MASKVIEWS – to design a complicated MOSFET by
drawing the layout. TCAD tools are chosen to aid the project since the cost to fabricate
the real design is very expensive. Thus, virtual fabrication is needed, especially when the
design does not meet the right specification and you have to do it all over again. If a real
fabrication is done, the cost to fabricate two to three times would be so much expensive.
Thus, virtual fabrication is the most suitable method to investigate the characterization of
the device, without any costs. Any improvement in the design can be made without hassle
with the aid from the software.

3.3.1 Simulation Tools

Nowadays, simulation tools are very popular in the design section to aid the
designers to obtain the optimized desirable result. In electrical engineering field itself,
stages from digital design to circuit level design, are using simulation tools in every
aspect to obtain the accurate characteristics and results. In this project, ATHENA and
ATLAS have been chosen to aid the author throughout the project.

31
3.3.1.1 TCAD Software

SILVACO International is owned privately and provides a comprehensive set of
electronic design automation (EDA) software, which allows companies to design both
analog and mixed-signal integrated circuit (IC). SILVACO delivers products like TCAD
tools for process and device simulation. It provides analog semiconductor process, device
and design automation solution in CMOS, bipolar transistors, SiGe and any other
compound technologies. The main process and the device simulation project are using the
SILVACO’s ATHENA and ATLAS software, for device simulation and characterization
respectively.

3.3.1.1.1 DECKBUILD: Interactive Deck Development and Runtime Environment

DECKBUILD is an interactive runtime and input file development environment
within which all Silvaco’s TCAD and several other SIMUCAD products can run.
DECKBUILD has numerous simulator specific and general debugger style tools. This
includes powerful extract statements, GUI based process file input, line by line runtime
execution and intuitive input file syntactical error messages. DECKBUILD contains an
extensive library of hundreds of pre-run examples decks which cover many technologies
and materials, and also allow the user to rapidly become highly productive18.
Key features of DECKBUILD are:

Provide an interactive runtime and input file development environment for
running several core simulators

Input deck creation and editing

32

View simulator output and controls

Set popups that provide full language and run-time support for each simulator

Automatic interface among simulators

Many input file creation and debug assist features, such as run, kill, pause, stop at,
and re-start

Extracted quantities can be used as targets in DECKBUILD’s internal optimizer, allowing
automatic cyclical optimization of any parameter19.

3.3.1.1.2 TONYPLOT: 1D/2D Interactive Visualization Tools

TONYPLOT is a powerful tool designed to visualize TCAD 1D and 2D structures
produced by SILVACO TCAD simulators.

TONYPLOT provides visualization and

graphic features such as pan, zoom, views, labels and multiple plot support. TONYPLOT
also provides many TCAD specific visualization functions, 1D cut lines from 2D
structures, animation of markers to show vector flow, integration of log or 1D data files
and fully customizable TCAD specific colors and styles.
Some of the key features of TONYPLOT are:

Flexible graphical analysis tool specifically developed for TCAD visualization
assists in rapid prototyping and developing of process and device designs

Common visualization tool across all SILVACO TCAD products

Plotting engine supports all common 1D and 2D data views including: 1D x-y
data, 2D contour data, 2D meshed data, smith charts and polar charts

Exports data in many common formats for use in reports or by third party tools.
Supported formats include; jpg, png, bmp, Spice Raw File and CSV

33

Flexible Labels allow plots to be annotated to create meaningful figures for
reports and presentations

Integrated suite of probes, rulers, and other measurement tools allows detailed
analysis of 1D and 2D structures

Overlays allow multiple plots to be easily compared

Overlaying 1D log files enables visualization of how process conditions effect
electrical results

Cutline tool allows 1D slices to be generated from 2D structures. Slicing can be
automated to generate several slices through a structure

Function and Macro editor allows complex functions and macros to be defined
that can be visualized as normal 1D quantity. This feature allows calculation of
M-Plots for OLED devices

Quasi 3D mode allows visualization of multi dimensional data

Fully customizable including; colors, materials, legends, toolbars and shortcuts 20.

3.3.1.1.3 MASKVIEWS

Another interesting part in SILVACO TCAD tools is MASKVIEWS. MASKVIEWS
is an IC layout editor. It is designed to interface IC layout or any complicated structured
device with SILVACO’s process simulator. MASKVIEWS can be used extensively to
draw and edit any complicated device and IC layout, store and then load the complete
layout, and import or export the layout details by using the industry standard GDSII and
CIF layout format.

34
Any part of the layout can be simulated – the most interesting process, and
without the hassle of structuring the codes in ATHENA; you can obtain the accurate
design based on the layout that has been accurately designed. MASKVIEWS also provides
features to allow layout experimentation such as misalignment, polygon over sizing or
under sizing, global rescales and region definition — depending on combinations of
present mask elements21.

35

CHAPTER 4

DESIGN OF CONVENTIONAL AND STRAINED SILICON MOSFET

4.1

Design of MOSFET

In this chapter, we will be discussing the important part of this project, which is
designing MOSFETs – PMOS, NMOS and CMOS. Basically, the design of NMOS and
PMOS are the same, except the source/drain doping and the VTH adjustment for NMOS.
That means the material is either Arsenic or Phosphorus. The substrate for NMOS is a
p+ material, so it will be Boron. As for PMOS - the doping at the source and drain, and
also the threshold voltage adjustment is p+ material; which means it is Boron.

Next, the distinct difference between the conventional MOSFET and the strained
silicon MOSFET is minor – that is the strained silicon will have two additional layers –
Silicon Germanium layer on top of the substrate and Silicon layer on top of the Silicon
Germanium layer. The author would like to declare that only strained silicon NMOS will
be discussed as the flow of conventional and biaxial strained silicon is quite similar
except that conventional MOSFET does not have a silicon and SiGe layers. A bulk
CMOS design will be discussed in the subsequent subtopic.

36

4.1.1 ATHENA – Design of Biaxial Strained Silicon NMOS

ATHENA enables process and integration engineers to develop and optimize
semiconductor manufacturing processes. ATHENA provides a useful and convenient
platform for simulating ion implantation, diffusion, etching, deposition, lithography,
oxidation, and silicidation of semiconductor materials. It replaces costly wafer
experiments with simulations in software to shorten the development cycles and gives
higher yields. The key features of ATHENA provided fast and accurate simulation of all
critical fabrication steps used in CMOS, bipolar, SiGe/SiGeC, SiC, SOI, III-V,
optoelectronic, MEMS, and power device technologies, apart from accurately predicts
multi-layer topology, dopant distributions, and stresses in various device structures 18.

This advanced simulation environment allows easy creation and modification of
process flow input decks including automatic control of layout mask sequences, runtime extraction of important process and device parameters optimization of process flow
and calibration of model parameters. Besides, this platform also enables IDMs,
foundries and fables companies to optimize semiconductor processes for the right
combination of speed, yield, breakdown, leakage current and reliability to upgrade the
equipment or the devices used. ATHENA can also be used to interface with ATLAS for
device simulation18. The design of biaxial strained Silicon MOSFET is quite similar for
PMOS and NMOS as mentioned earlier, referring to the figure below.

37

Define mesh,
initialize
substrate

Metallization
and Contact
Patterning

Reflect
Structure
Electrode
labeling

Add epitaxial
layer

Source Drain
Annealing

Tonyplot

Gate Oxidation
formation

Polysilicon
Oxidation

Concentration
view and
Measurement

Threshold
Voltage
Adjustment

Polysilicon
patterning

Figure 4.1: The flow of designing a conventional MOSFET
Define mesh,
initialize
substrate

Source Drain
Annealing

Metallization
and Contact
Patterning

Add epitaxial
layer

Polysilicon
Oxidation

Reflect
Structure
Electrode
labeling

Deposition of
Silicon and SiGe
layer

Polysilicon
patterning

Tonyplot

Gate Oxidation
formation

Threshold
Voltage
Adjustment

Concentration
view and
Measurement

Figure 4.2: The flow of designing biaxial strained silicon MOSFET

38
Note that the only difference between the conventional MOSFET and the biaxial
strained silicon MOSFET is only the deposition of Silicon and Silicon Germanium
layers. This is a simplified version of designing a MOSFET and of course, a much more
detail process do exists. Let’s discuss each part of the process starting from the first one,
thoroughly.

The very basic step is to know how to use DECKBUILD of SILVACO TCAD
Tools. DECKBUILD can only be ran in UNIX prompt – which means that the next
important thing is to have a computer with UNIX and a SILVACO licensed software.
Open terminal and create a folder to specify the location of the design that will be
created. Since DECKBUILD is a very convenient and user-friendly tool, it is easy to
familiarize with it.

Figure 4.3: The view of DECKBUILD

39
4.1.1.1 Mesh Definition and Substrate Initialization

After invoking ATHENA with the command of go athena, mesh definition is
the essential part in designing a device. At the x-line, setting the mesh with too few lines
can cause the calculation to be inaccurate, while setting the grid with too dense mesh can
consume more time for ATLAS to calculate in the characterization part. At the vertical
line or y-line, the bigger the size of the lines could contribute to the increment of the
weight of the actual fabricated device. Basically, mesh definition is the part where we
can control the size of our device.

# Establishing Initial Non-uniform Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.50 spac=0.008
line y loc=-2.40 spac=0.006
line y loc=-2.20 spac=0.005

Figure 4.4: Codes for generating mesh

At the horizontal or x-line, the line has been set up to be denser at the right of the
structure with the space of 0.025 microns. This region will be the critical region of the
device, where the flow of current and channel formation will occur here. At the vertical
or y-line, almost an even mesh is created. The dimension of the device structured is
0.5µ microns x 0.3 µ microns. Note here that the dimension specified here is only the
dimension that will be generated straight away from the codes. After reflecting it, the
dimension will be 1 µ microns x 0.3 µ microns.

40
The structure then is initialized by defining the wafer or the substrate of the
device. This is the step where the dopants’ of the device is determined – whether it is a
PMOS or NMOS device. In this case, since it is a NMOS device, the dopant is Boron –
which is a p+ material. The concentration is set to be 2 x 1018 cm-3, and a <100>
orientation with two-dimensional substrate is chosen.

# Initializing Substrate Material
init silicon c.boron=2.0e18 orientation=100 two.d
Figure 4.5: Codes for generating substrate material

Note that this is the code for generating a NMOS structure. For a PMOS
structure, the substrate should be doped with an n+ material, which is either Phosphorus
or Arsenic.

4.1.1.2 Epitaxial Layer

Adding epitaxial layer is a process of depositing a thin single layer crystal over a
single crystal substrate. This process is mandatory to minimize the latch-up occurrence
in VLSI (Very Large Scale Integrated Circuit) design, thus allowing a better
controllability in doping concentration and improves the device performance. Normally
the material used in epitaxial layer is the same material with used in its substrate, which
means that, for NMOS, the substrate is Silicon doped with Boron, and for PMOS is
Silicon doped with Phosphorus.

41

# Depositing Epitaxial Layer
epitaxy time=25 temp=800 thickness=0.02 c.boron=4.0e16
Figure 4.6: Codes for depositing epitaxial layer

Epitaxial layer

Substrate

Figure 4.7: View of Epitaxial Layer and Substrate with Grid Definition

4.1.1.3 Deposition of Silicon and SiGe layers

As mentioned earlier, the only significant difference between a conventional
MOSFET and a biaxial strained Silicon MOSFET is the additional of two main layers –
which are Silicon layer and SiGe layer on top of the silicon substrate. The layers
deposition process is executed line by line, which means that it will deposit Silicon layer

42
first, and then SiGe with germanium mole fraction of 0.35, and on top of it is a thin
single layer of Silicon.

# Deposit Si & SiGe layer
deposit silicon thick=0.02 c.boron=1.0e16 divisions=10
deposit sige thick=0.015 c.boron=1.0e16 divisions=5 c.fraction=0.35
deposit silicon thick=0.009 c.boron=1.0e16 divisions=4

Figure 4.8: Codes for depositing Silicon and SiGe layer
Silicon Layer
SiGe Layer

Figure 4.9: Silicon and SiGe layer

4.1.1.4 Formation of Gate Oxide

To obtain the gate oxide layer, an oxide layer is diffused after the deposition of
Silicon and SiGe layers. Since a very thin oxide layer needed, diffuse time is minimized
and Dry O2 process is preferred since oxide tends to grown faster in Wet O2 condition.

43
Here, a thin layer of gate oxide of thickness less than 6nm is desired. The temperature
used normally is higher than 800ºc since Silicon can only be oxidized in temperature
higher than 800ºc.

# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
Figure 4.10: Codes for diffusing gate oxide
Oxide Layer

Figure 4.11: The formation of Oxide layer for Gate Oxide

To obtain the accurate thickness, the thickness of gate oxide is the extracted to a
log file that can be open via Microsoft Excel.

# Extract Gate Oxide Thickness
extract name=”GateOxide” thickness material=”SiO~2” \
mat.occno=1 x.val=0.3 datafile=”gateOxide.final”

Figure 4.12: Codes for extracting the thickness of gate oxide

44
4.1.1.5 Threshold Voltage Adjustment

The next step is to implant material for threshold voltage adjustment. This
process is needed to determine the threshold voltage. The lower the concentration of the
dopant, the lower the threshold voltage will be. The material used should be the same as
the material used in the MOSFET device. For NMOS, Boron is used, and for PMOS,
Phosphorus is used. Moderate energy is used as it does not need big junction. The
determination of threshold voltage concentration is highly related to the formation of
gate oxide. Reducing the thickness of gate oxide requires a reduction in threshold
voltage. In other words, thin gate oxide needs a small voltage to turn it on.

# Vth Adjust Implant
implant boron dose=1.0e10 energy tilt=0 rotation=0 crystal

Figure 4.13: Codes for implanting the doping for threshold adjustment

4.1.1.6 Deposition and Patterning of Polysilicon

In this project, Polysilicon is used instead of metal as the contact. Polysilicon is a
type of material that consists of small silicon crystals. Also called Polycrystalline
Silicon, Polysilicon has been the ultimate choice as a conducting gate material for the
new generation of MOSFETs. This is due to its flexibility to become a conductor, or a
resistor, by simply changing the doping material of the Polysilicon. Eventually, the
conductivity of the Polysilicon may be increased by simply depositing a layer of metal
such as Tungsten on top of it. Virtually, a layer of Polysilicon is deposited in this step.
To pattern the Polysilicon, it is then etched from left, since it will be mirrored later. Note
that the channel length desired also depends on the length of the Polysilicon. So altering

45
the length of etched Polysilicon in this process is needed to obtain the accurate desirable
result.

# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
Figure 4.14: Codes for depositing Polysilicon

Polysilicon
Layer

Figure 4.15: Layer of Polysilicon

# Etch Poly
etch polysilicon left p1.x=0.408093
Figure 4.16: Codes for patterning polysilicon

46

Etched
Polysilicon
Layer

Figure 4.17: Etched Polysilicon

4.1.1.7 Polysilicon Oxidation and Doping

The Polysilicon is then oxidized to create the effect of insulation on top of the
Polysilicon. In this project Polysilicon is diffused in a temperature of 900ºc since Silicon
can only be oxidized in a temperature above 800ºc. Wet O2 is preferred so that the oxide
layer can be grown faster.

# Poly Oxidation
method Fermi
diffus time=3 temp=900 weto2 press=1.00

Figure 4.18: Codes for Polysilicon oxidation

47

Figure 4.19: Oxidized Polysilicon

The next crucial step is the Polysilicon doping. This step is needed to alter the
junction of source drain and to ensure the conductibility of the Polysilicon gate. For
NMOS, Polysilicon is doped with an n+ material; while for PMOS, Ploysilicon is doped
with a p+ material. Since TCAD tools has its own limitation, which is etching the
Polysilicon might not affect the channel length when the channel length is too short, you
may found out that altering the doping concentration of Polysilicon is somehow useful to
obtain the accurate desirable channel length. In this process, Polysilicon is implanted
with 5x1014cm-3 Phosphorus with a small amount of energy.

# Poly Doping
implant phosphor dose=5.0e14 energy=13 crystal

Figure 4.20: Codes for Polysilicon doping

48
4.1.1.8 Spacer Oxide

To prevent ions from being implanted to the gate, a layer of spacer oxide with
thickness of 0.12microns is deposited and then etched. Normally the thickness of the
spacer oxide is only about 10% of the Polysilicon thickness. Since the thickness of
Polysilicon is 0.2 microns, the thickness of spacer oxide can be 0.02 microns. However,
this condition is not mandatory.

# Deposit Spacer Oxide
deposit oxide thick=0.12 divisions=10
#Etch Spacer Oxide
etch oxide thick=0.12
Figure 4.21: Codes for depositing spacer oxide

4.1.1.9 Source and Drain Annealing

Right after spacer oxide process, the source and drain formation is done. The
device is implanted with a dopant of 1 x 1016 cm-3. For NMOS, the dopant is an n+
material such as Phosphorus or Arsenic, and for PMOS, the dopant is a p+ material,
which is Boron. This process is also called ion implantation, where a chemical species
directly bombarded into a substrate with a high energy ions of the chemical for
deposition.

49
Thermal diffusion process has been replaced by ion implantation process for
doping a material in wafer fabrication since it the control of the process of depositing
dopants’ atoms into the substrate, is much more precise as compared to the thermal
diffusion process. However, the damage caused by atomic collisions during ion
implantation changes the electrical characteristics of the target. Many target atoms are
displaced, creating deep electron and hole traps which capture mobile carriers and
increase resistivity. To repair the lattice damage and inserting the dopant in
substitutional sites where they can be electrically active again, annealing is therefore
needed in this process 11.

# Source Drain Implantation
implant phosphor dose=1.0e16 energy=20 crystal
# Source Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
Figure 4.22: Codes for implanting and annealing source and drain

Source/Drain region

Figure 4.23: The view of source and drain region/junction

50

4.1.1.10 Metallization and Contact Patterning

After the formation of body, gate, source and drain, the structure is the ready for
the next step, which is depositing and patterning the contact. When contact is deposited,
the layer of metal is electrically interconnected the device fabricated on the silicon
substrate. The material used for the contact is Aluminium, since it has a very low
resistivity (high conductivity) and its adhesion compatibility with SiO2. In this step, a
very thin layer of metal – which in this case is Aluminium, is deposited, and a portion of
it is etched away, leaving a contact right on top of the source and drain region.

# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminium right p1.x=0.18
Figure 4.24: Codes for depositing and patterning Aluminium

4.1.1.11 Structure Reflection and Electrode Labeling

Since the structure obtained all the way through these processes is only half of
the device structure, the second final process of structuring a device using ATHENA is
to mirror the structure (if it happens the structure is symmetrical). The process eased the
burden of creating the same step over and over again, thus, minimized the risk of errors
occur in the process of structuring a device.

51

# Mirror structure
struct mirror right
Figure 4.25: Codes for reflecting structure

Figure 4.26: Reflected structure

Finally, the device is then labeled for the ease of analysis and the output file is
created. Labels included source, drain, gate, and backside.

52

# Label structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
# Struct Outfile
struct outfile=ssin.str

Figure 4.27: Codes for labeling structure and creating output file

4.1.1.12 TONYPLOT – Concentration View and Measurement

The out file of a biaxial strained Silicon NMOS is now obtained. The next step is
to view the structure and measure the channel length of the device and to ensure that the
channel length is the desirable length. By using another advance feature of TONYPLOT
by SILVACO, the effective channel length can be measured by simply viewing the
concentration view and displaying the junction, and zooming right beneath the gate.
Note that the length measured is in microns.

The out file obtained later is exported into ATLAS right after invoking ATLAS
with the command of go atlas. As mentioned earlier, the process of structuring a
conventional NMOS and PMOS is similar to the process of creating biaxial strained
Silicon NMOS and PMOS.

53

# Tonyplot structure
tonyplot ssin.str

Figure 4.28: Codes for viewing the structure

Figure 4.29: Concentration view and channel length measurement

Overall, the specification of MOSFETs that have been designed is illustrated in
Table 4.1. Effective channel length, gate oxide thickness, threshold voltage and
germanium fraction are the important specification the author has observed.

54
Table 4.1: Specification of simulated devices
Specification
Effective
Channel
Length (nm)
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Germanium
fraction

NMOS
45

sSi NMOS
45

PMOS
45

sSi PMOS
45

5.7

5.7

5.7

5.7

1.50
-

0.2625
0.35

-1.30
-

-0.80
0.35

4.1.2 MASKVIEWS – Design of Conventional and Biaxial Strained Silicon
Complementary MOSFET

As mentioned above in Chapter 3 – Methodology, the design of conventional
bulk CMOS and biaxial strained silicon CMOS can be accomplished by using another
powerful tools provided by SILVACO. If you have any experience creating or designing
a layout, let say in TSPICE L-edit layout, you may have a clue on the topic we are about
to discuss.

MASKVIEWS by SILVACO provided a very handy help which can ease the
burden of creating a complicated device. As you may find typing or even generating the
codes with GUI (Graphical User Interface) is somehow a tedious process for a
complicated device such as Complementary MOSFET, MASKVIEWS is the sole, easiest
solution to this problem.

Some researchers and student tried to construct a CMOS and any other
complicated device using solely ATHENA and ATLAS, including the author. Basically,

55
the structure obtained will have the resemblance of a Complementary MOSFET, and the
STI (Shallow Trench Isolation – to isolate between NMOS and PMOS) is simply the
etched Silicon that has been oxidized. But the significance problem arose is that how to
get the accurate effective channel length desired? ATHENA can design and using
TONYPLOT the cross-section of the simulated device can be observed. By using,
MASKVIEWS, layout is designed using top-view of the device, and the characteristics
will be exported to ATHENA to generate the cross-section view.

Figure 4.30: The first trial of creating a bulk CMOS

The only solution is to use MASKVIEWS to produce a GDS layout, and extract it
to ATHENA to produce the structure. Since MASKVIEWS license is not available, the
author could not proceed with this step to create a bulk CMOS and a bulk biaxial
strained silicon CMOS. The author will discuss MASKVIEWS processes by referring to
SILVACO MASKVIEWS manual and journal from SILVACO

21

. The recipe of

simulation should be observed and done carefully, since even with M ASKVIEWS aid, if
the simulation recipe is incorrect, the desirable result could not be obtained. Figure 4.31

56
shows the flowchart to design a CMOS and Figure 4.32 shows the recipe and steps to
design a CMOS.

Figure 4.31: Flowchart of creating a conventional CMOS

57
The process recipes and fabrication flows are referred from University of
California, Berkeley Micro lab open source 21.

Figure 4.32: Steps of processes of fabricating conventional CMOS

The only significant difference between designing a conventional CMOS and
biaxial strained silicon CMOS is that, biaxial strained silicon CMOS includes the
process of depositing a thin silicon layer and SiGe layer on top of the substrate.
MASKVIEWS Base Window can be invoked within DECKBUILD. Examples can be
loaded, similar with loading the examples of ATHENA and ATLAS.

58

Figure 4.33: MASKVIEWS Base Window

After creating the layout and converting it to GDS II format (industry format),
the parameters generated is sent to ATHENA to construct the structure of a complicated
device.

Figure 4.34: A 0.35 um conventional CMOS GDS layout

59

Figure 4.35: Top view and side view of 0.35um CMOS using MASKVIEWS

The structure of a complicated device – in this case CMOS – is then straight
away generated from the out file of GDSII format.

Figure 4.36: Structure obtained from GDSII layout

60

Figure 4.37: Concentration view of 0.35um CMOS

Comparing a conventional CMOS and biaxial strained silicon CMOS structure,
the only distinct difference between both devices is that the absence of a thin silicon
layer and a SiGe layer on top of the conventional CMOS substrate. Thus, in the design
steps of biaxial strained silicon CMOS, there will be extra step of depositing a very thin
silicon layer and SiGe layer on top of its substrate.

61

Figure 4.38: Flowchart of creating biaxial strained silicon CMOS

62

CHAPTER 5

CHARACTERIZATION OF BIAXIAL STRAINED SILICON MOSFETS

The design of conventional and strained Silicon MOSFETs has been discussed
thoroughly in the last chapter. The next step conducted in this project is to characterize
the electrical properties of the devices that have been simulated previously, before
comparison and conclusion is made. In this chapter, ATLAS as a device simulator is
discussed as well as the electrical properties of the devices.

5.1

ATLAS –Device Simulation Framework

ATLAS enables device technology engineers to simulate the electrical, optical,
and thermal behavior of semiconductor devices. ATLAS provides a physics-based, easy
to use, modular, and extensible platform to analyze DC, AC, and time domain responses
for all semiconductor based technologies in two and three dimensions12.

The key features of ATLAS are that ATLAS can accurately characterize physicsbased devices in 2D or 3D for electrical, optical, and thermal performance. This means

63
that ATLAS can characterize without costly split-lot experiments, solve yield and
process variation problems for optimal combination of speed, power, density,
breakdown, leakage, luminosity, or reliability. ATLAS also is fully integrated with
ATHENA process simulation software, comprehensive visualization package, extensive
database of examples, and simple device entry, that can be chosen from the largest
selection of silicon, III-V, II-VI, IV-IV, or polymer/organic technologies including
CMOS, bipolar, high voltage power device, VCSEL, TFT, optoelectronic, LASER,
LED, CCD, sensor, fuse, NVM, ferro-electric, SOI, Fin-FET, HEMT, and HBT, as well
as connect TCAD to Tape-out with direct import of ATLAS results into UTMOST for
SPICE parameter extraction. ATLAS is also worldwide support software 28.

Figure 5.1: ATLAS inputs and outputs

64
5.2

Device Characterization using ATLAS Simulator

The most commonly used inputs of ATLAS are text file (.txt file) and structure
file (.str file). Commands written in text file can be executed by running the coding
while the structure defined in structure file can also be exported for the device
simulation12.

Besides, ATLAS produces three outputs: run-time output, log files (.log) and
solution files.

Run-time output will display the progress of simulations running,

warning or error messages if any. Log file (.log file) stores all the terminal current and
voltage values from the device simulation. These values are then extracted and used for
data analysis in Microsoft Excel. Solution file will stores two or three dimension data
that related to the values of solution variables within the device for a bias point12.

Material
model
Specification

•Mesh
•Region
•Electrode
•Doping
Structure
Specification

•Material
•Models
•Contact
•Interface

Solution
Specification

•Method

Numerical
Models
Specification

•Log
•Solve
•Load
•Save

Figure 5.2: Order of Statement in ATLAS Simulation

•Extract
•Tonyplot

Result
Analysis

65
To start the device simulation, the input file of structure specification can be read
from another existing file. The input file of ATLAS in this project is taken from the
structure file (.str file) created in ATHENA. The result analysis is done to obtain the
characterizations of biaxial strained Silicon MOSFET and conventional MOSFET in the
following sub chapters12.

5.3

Drain Current versus Gate Voltage (ID vs. VGS)

Characterization of biaxial strained silicon MOSFETs is done using ATLAS.
Both MOSFETs were characterized in a similar way, except that a negative voltage is
supplied to biaxial strained silicon PMOS, and positive voltage is supplied to biaxial
strained silicon NMOS. To plot drain current versus gate voltage (ID vs. VGS) graph,
each of the nodes of gate, source and drain is biased at different value of voltage. At the
gate of NMOS, the voltage is ramped from zero volts (0V) to three volts (3V) with steps
value of +0.1V. Drain voltage is biased with two different values that have a big
difference, which is 0.1V and 1V. The source is biased with zero voltage. The same
values have been applied to the conventional NMOS.

As for PMOS, gate voltage has been ramped from 0V to -3V. A negative voltage
must be applied to the gate in order to make the inversion layer charge equal to zero,
whereas a positive gate voltage will induce a larger inversion1. Drain voltage is biased
with -0.1V and -1V, and the same value is supplied to the conventional PMOS.

66

ID - VGS of NMOS at VDS=0.1V
1.80E-04
1.60E-04
1.40E-04
1.20E-04
1.00E-04
8.00E-05

NMOS

6.00E-05

sSi NMOS

4.00E-05
2.00E-05
-2.00E-05

0.00E+00
2.00E-01
4.00E-01
6.00E-01
8.00E-01
1.00E+00
1.20E+00
1.40E+00
1.60E+00
1.80E+00
2.00E+00
2.20E+00
2.40E+00
2.60E+00
2.80E+00
3.00E+00

0.00E+00

Figure 5.3: ID-VGS of NMOS and strained Silicon NMOS at VDS = 0.1V

From Figure 5.3, graph of ID-VGS of NMOS and strained Silicon NMOS at VDS
= 0.1V, it can be observed that strained silicon NMOS has a threshold voltage around
0.26V. Comparing with conventional NMOS, the same threshold adjustment results a
different threshold voltage. This is one of short channel effects that occur when the
channel length is too small.

The concentration at threshold voltage adjustment is the same, which is 1.0×1010
cm-3. Unfortunately, the conventional NMOS suffers hot electrons effect. Hot electron
effect has increased the actual value of threshold voltage, thus, degraded the device
performance. This effect is not something that can be reduced by simply reducing the
concentration of the threshold implant, even the purpose of altering threshold implant
concentration is suppose to adjust the threshold voltage.

67

ID - VGS PMOS at VDS = 0.1V
-0.000005

0.00E+00
-2.00E-01
-4.00E-01
-6.00E-01
-8.00E-01
-1.00E+00
-1.20E+00
-1.40E+00
-1.60E+00
-1.80E+00
-2.00E+00
-2.20E+00
-2.40E+00
-2.60E+00
-2.80E+00
-3.00E+00

0

-0.00001
-0.000015

PMOS
sSi PMOS

-0.00002
-0.000025
-0.00003

Figure 5.4: ID-VGS of PMOS and strained Silicon PMOS at VDS = 0.1V

From Figure 5.4, graph of ID-VGS of PMOS and strained Silicon PMOS at VDS =
0.1V, it can be observed that strained Silicon PMOS has a threshold voltage around
0.80V. Comparing with conventional PMOS, the same threshold adjustment or threshold
implant concentration results a different threshold voltage. This is one of short channel
effects that occur when the channel length is too small.

The concentration at threshold voltage adjustment is the same, which is 1.0×1010
cm-3. Unfortunately, the conventional PMOS suffers hot electrons effect. Hot electron
effect has increased the actual value of threshold voltage, thus, degraded the device
performance. It also affects the MOSFET’s conveyed conductance.

68
5.4

Drain Current versus Drain Voltage (ID vs. VDS)

As the drain voltage increases, the voltage drop across the oxide near the drain
terminal decreases, which means that the induced inversion charge density near the drain
also decreases. The incremental conductance of the channel at the drain decreases which
then means that, the slope of the ID versus VDS curve will decrease1.

When VDS increases to the point where the potential drop across the oxide at the
drain terminal is equal to threshold voltage, the induced inversion charge density is zero
at the drain terminal. At this point, the incremental conductance at the drain is zero,
which means that the slope o the ID versus VDS curve is zero1.
where
VDS(sat) = VGS - VT

Figure 5.5: ID-VDS Graph of NMOS

................ (4)

69
As shown in Figure 5.5 of ID-VDS graph, the characteristics of conventional and
strained Silicon NMOS are compared. Results showed that strained Silicon NMOS
drives better drain current compared to the conventional one, for 3V, 2V and 1V gate
voltage. As for PMOS, the strained Silicon added device also proves that it is better
when compared to the conventional PMOS. Since PMOS suffers one of the short
channel effects – that is hot electrons effect, the characteristics obtained is not 100%
accurate, but roughly, it compares the performance between strained and conventional
MOSFET.

Figure 5.6: ID-VDS Graph of PMOS

70
5.5

Drain Induced Barrier Lowering

As mentioned in Chapter 2, drain induced barrier lowering effect or simply
DIBL, is one the projects’ scope. The aim is to decrease the effect of DIBL, thus
improving the overall performance of the device. By using ATLAS, DIBL can be
calculated directly from the ID vs. VGS graph. Two major steps included in determining
DIBL. First, drain terminal is biased with 0.025V to 0.3V and step by +0.025V. Gate
voltage is ramped from 0V to 1.5V with voltage step at +0.1V. Secondly, drain is biased
with higher value and Tonyplot the graph.

DIBL value is the difference between the first
line and the second.

(a)

(b)

Figure 5.7: Determining DIBL from graph (a) NMOS (b) PMOS

Comparing the DIBL values of conventional NMOS and PMOS by varying the
channel length, the shorter the channel length, the device suffers less DIBL effect, as
shown in Figure 5.4.

71

Figure 5.8: DIBL effect of conventional MOSFETs
Since strained Silicon improves DIBL in both MOSFETs, the effects can be
observed by comparing strained Silicon MOSFETs with conventional MOSFETs. The
effect is almost similar to scaling down the size of the MOSFET half from the original
size.

Figure 5.9: Comparison of DIBL effect between conventional and strained Silicon
MOSFETs

72
Overall, DIBL has been improved quite much by adding strained Silicon into the
MOSFETs’ structures. The significant improvement concludes that strained silicon is
another alternative besides scaling down the device which will reach its limit.
Table 5.1: Comparison of DIBL with different channel length
DIBL (mV/V)
Effective channel
length, Leff (nm)

5.6

sSi NMOS

NMOS

sSi PMOS

PMOS

45

218

145

695

348

90

35412

410

-

-

100

-

-

693.56410

911

Subthreshold Swing

From ID versus VGS graph, the subthreshold swing can be determined.
Subthreshold swing can be determined at the weak inversion part of the log ID versus
VGS graph. The slope of these lines is called subthreshold slope. The inverse of this
slope is usually referred to as subthreshold swing,

given in units (mV/decade).

Subthreshold swing can be defines as the voltage required to increase or reduce ID by
one decade. Subthreshold swing is enlisted as one of the most critical performance
figures of MOSFET in logic applications1.

73

Weak
inversion

Strong inversion

Figure 5.10: Log ID vs. VGS at VDS = 0.1V

It is highly desirable to have a subthreshold swing as small as possible and still
get large current change. This is the parameter that determines the amount of voltage
swing necessary to switch a MOSFET from OFF state to its ON state. It is especially
important for modern MOSFETs with supply voltage approaching 1.0V12.

74

Figure 5.11: Comparison of subthreshold swing between conventional and biaxial
strained silicon MOSFETs

Nowadays, the technology has become so advanced that MOSFETs has been
scaled down to 32nm. It is widely known that varying channel length improves the
overall performance of conventional MOSFETs. The results are then compared to the
previous research so that the effect of scaling down strained Silicon MOSFET can be
observed.

75

Figure 5.12: Comparison of subthreshold swing with various channel length

The results are then summarized as stated in Table 5.2 below. By comparing the
channel length of the device, it can be seen clearly that the strained Silicon MOSFETs
are better in performance, compared to the conventional ones.

Table 5.2: Comparison of Subthreshold swing with various channel length
Effective channel
length, Leff (nm)

Subthreshold Swing (mV/dec)
sSi NMOS

NMOS

sSi PMOS

PMOS

45

109

155

122

149

90

112.812

16412

-

-

100

-

-

186.15310

21410

76
5.7

Result Comparison

Results are then compared, between varying the channel length of conventional
MOSFETs, and varying the channel length of biaxial strained Silicon MOSFETs, and
comparing results between conventional and biaxial strained Silicon MOSFETs.
Table5.3: Comparison between conventional and biaxial strained Silicon MOSFETs
NMOS 45nm
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Subthreshold
swing
DIBL
Improvement
of
subthreshold
swing
Improvement
of DIBL

PMOS 45nm

5.7

sSi NMOS
45nm
5.7

5.7

sSi PMOS
45nm
5.7

1.50
155

0.2625
109

-1.30
149

-0.80
122

218
-

145
29.68%

695
-

348
18.12%

-

33.49%

-

49.93%

Table 5.4: Comparison between different channel lengths of strained silicon MOSFETs

Gate Oxide
thickness (nm)
Vth at vd=0.1v
Subthreshold
swing
DIBL
Improvement
of
subthreshold
swing
Improvement
of DIBL

sSi NMOS
90nm
11

sSi NMOS
45nm
5.7

sSi PMOS
100nm
-

sSi PMOS
45nm
5.7

0.57153312
112.812

0.2625
109

-0.59689410
186.15310

-0.80
122

35412

145

693.56410

348

-

3.37%

-

34.46%

-

60.58%

-

49.82%

77

CHAPTER 6

CONCLUSION

6.1

Project Summary

Based on the studies conducted in this project, it can be concluded that biaxial
strained Silicon CMOS is the alternative for improving a conventional CMOS rather
than scaling down the current technology of conventional CMOS. By growing a strained
Silicon layer on top of the relaxed SiGe layer at the channel, this technology allows the
enhancement of the carrier mobility, thus delaying the need for the new gate stack
materials and improving the overall performance of the device. The strained silicon
technology allows us to have a powerful device without the need of scaling down and
minimize the short channel effects that often occur in nanoscale devices.

Biaxial strained Silicon NMOS and PMOS have been designed virtually with the
aid of SILVACO TCAD TOOLS – ATHENA and ATLAS. Rather than speeding up the
fabrication process and providing an accurate and optimized result, the simulation also
gave the opportunity to save cost and to alter any design without any hassle. Any small

78
adjustment, in example changing or decreasing the channel length or decreasing the
threshold voltage can be easily done by using ATHENA.

Once simulated, the determination of the characteristics is speed up. It is
important to study the electrical properties simply to determine whether an optimized
result is achieved or not. Even if it is not achieved, the process of altering is not as
painful as refabricate the real device, which would lead to expensive cost and time
consuming process.

The devices are then characterized by comparing the channel length of 45nm and
90nm. Several characteristics have been carefully observed. Significant improvement
has been noticed by comparing the conventional and biaxial strained silicon CMOS.
Overall, four devices have been simulated in this project with these specifications:
Table 6.1: Summary of device characteristics
Specification
Effective
Channel
Length (nm)
Gate Oxide
thickness (nm)
Vth at vd=0.1v
Germanium
fraction

NMOS
45

sSi NMOS
45

PMOS
45

sSi PMOS
45

5.7

5.7

5.7

5.7

1.50
-

0.2625
0.35

-1.30
-

-0.80
0.35

Subthreshold
Swing (mV/dec)
Improvement in
Subthreshold
Swing (%)
DIBL
Improvement in
DIBL (%)

155

109

149

122

-

29.68%

-

18.12%

218
-

145
33.49%

695
-

348
49.93%

79
6.2

Suggestions for Future Work

Since the scope of the project has been narrowed down, there are several
extensions that can be made for future work. This project can be improved in several
ways and can covers wider topics of MOSFET.

6.2.1 Reducing Channel Length

Since the author has improved from 90nm technology to 45nm technology,
which is two steps above, further extension can be made my sizing down the device to
32nm. 32nm is the latest technology adopted by semiconductor companies like Intel
Corporation. Reducing the gate length needs modification in several characteristics,
including the threshold voltage, and doping concentration.

6.2.2 Capacitance-Voltage Characteristics

Another important scope that can be extended from this project is the
capacitance-voltage characteristics (C-V characteristics). C-V characteristics give
information about device performance under high/low frequency. Other parameters, for
instance, junction depth and parasitic resistance can be extracted if necessary12.

80
6.2.3 Strained Silicon in Silicon-on-Insulator (SOI)

Silicon-on-insulator is known for its low subthreshold swing and low
capacitance. Adding strained silicon might improve the carrier mobility with a higher
drift current. The structure of strained silicon implemented on silicon-on-insulator will
have the resemblance of the biaxial strained silicon MOSFETs, with the extra layer of
oxide on top of its substrate.

Figure 6.1: Strained silicon implemented on silicon-on-Insulator (SSOI)

6.2.4 MOSFET with Side Gates

In the era of sub-50-nm MOSFET, a precise control of doping profile in the
channel and source/drain region is needed24. However, it is difficult to implement ultrashallow junctions with a depth less than 10 nm by ion implantation or thermal diffusion.

81
It has been reported that the electrically induced inversion layer is a candidate for ultrashallow source/drain extensions and short-channel effect (SCE) could be suppressed by
using this approach25-27. However, the reported works showed severe decrease of current
level resulting from structural weakness. The structural weakness includes the thick
side-gate oxide, long side-gate length and gate-to-gate capacitance. A device structure
with a thin side-gate oxide is required in order to induce the inversion layer at a low
voltage 24.

Figure 6.2: Formation of MOSFET with Side Gates

6.2.5 Twin well with Field Oxide technology (FOX)

Rather than having only one well in a CMOS, twin well and field oxide (FOX)
technology has been introduced. Field oxide is simply a relatively thick oxide separating
NMOS and PMOS. An extension from this project can be made using this type of
MOSFET and by adding biaxial strained silicon; biaxial strained Silicon twin well with
FOX technology can be created.

82

Figure 6.3: MOSFET with twin well and FOX technology

83

REFERENCE

1. Donald A. Neamen. Semiconductor Physics and Devices: Basic Principles.
(3rd Ed.). New York: McGraw Hill. 2003.
2. C. K. Maiti, N. B. Chakrabarti, S. K. Ray. Strained Silicon Heterostructures:
Materials and Devices. (1st Ed.). London: The Institution of Electrical
Engineers. 2001.
3. F. D’Agostino, D. Quercia. Short-Channel Effects in MOSFETs. Introduction
to VLSI design project. 2000.
4. John D. Cressler. Silicon Heterostructure Handbook: Materials, Fabrication,
Devices, Circuits and Applications of SiGe and Si Strained-layer Epitaxy.
Florida: CRC Press. 2006.
5. Fischetti MV, Laux SE. Band structure, deformation potentials, and carrier
mobility in strained Si, Ge, and SiGe alloys. Journal of Applied Physics.
1994. 80(4):2234–2252.
6. Takagi S, Hoyt JL, Welser JJ, Gibbons JF. Comparative study of phonon
limited mobility of two dimensional electrons in strained and unstrained Si
metal oxide semiconductor field effect transistors. Journal of Applied Physics
1994. 80(3): 1567–1577.
7. Roldan JB, Gamiz F, Lopez-Villanueva JA, Carceller JE. A Monte Carlo
study on the electron transport properties of high performance strained Si on
relaxed SiGe channel MOSFETs. Journal of Applied Physics. 1996.
80(9):5121–5128.
8. Formicone GF, Vasileska D, Ferry DK. Transport in the surface channel of
strained Si on a relaxed Si1_x/Gex/substrate. Solid State Electron. 1997.
41(6):879–885.

84
9. Oberhuber R, Zandler G, Vogl P. Subband structure and mobility of two
dimensional holes in strained Si/SiGe MOSFETs. Physical Review B. 1998.
58(15):9941–9948.
10. Eunice Goh. Design and Characterization of Strained Silicon MOSFET.
Thesis Bachelor of Electrical Engineering. Universiti Teknologi Malaysia.
2007
11. Wong Y.J., Ismail Saad, Razali Ismail. Characterization of Strained Silicon
MOSFET Using Semiconductor TCAD Tools. 2006. Kuala Lumpur:
ICSE2006 Proc.
12. Lau Ngei Ong, Design and Characterization of Biaxial Strained Silicon NChannel MOSFET. Thesis Bachelor of Electrical Engineering. Universiti
Teknologi Malaysia. 2010.
13. K. Rim et al. Strained Si CMOS (SS CMOS) technology: opportunities and
challenges. Solid-State Electronics. 2003. 47. 1133–1139
14. Y.Sun et al. Physics of process induced uniaxially strained Si. Materials
Science and Engineering. 2006. B(135). 179–183.
15. Scott E. Thompson et al. Uniaxial Process Induced Strained Si: Extending the
CMOS roadmap. IEEE Transactions On Electron Devices.2006. 53(5).
16. Scott E. Thompson, Mark Armstrong, et al. A Logic Nanotechnology
Featuring Strained Silicon. IEEE Electron Device Letters. 2004. 25(4): 191193.
17. David J. Walkey. MOSFET Operations, notes given in Physical Electronics
(Lecture 21). 2008.
18. Silvaco International, Interactive Tools: ATHENA: Process Simulation
Framework, Trade Brochure
19. Silvaco International, Interactive Tools: DeckBuild. Trade Brochure.
20. Silvaco International, TCAD Workshop Using Silvaco TCAD Tools. Manual.
21. Shaobo men. Simulation of 0.35um CMOS Process and Device Use
SILVACO TCAD TOOLS. 2008.
22. Reiche. M. et al. Strained Silicon Devices. Solid State Phenomena. 2010.
156-158.

85
23. Baker. R.J. CMOS – Circuit Design, Layout, and Simulation. USA: John
Wiley & Sons Inc. 2005.
24. H. Wakabayashi, et al. 45-nm gate length CMOS technology and beyond
using steep halo. IEDM Technical Digest. 2000. 49–52.
25. H. S. Wong. Gate current injection and surface impact ionization in
MOSFETs with a gate induced virtual drain. IEDM Technical Digest. 1992.
151–154.
26. H. Noda et al. Threshold voltage controlled 0.1um MOSFET utilizing
inversion layer as extremely shallow source/drain. IEDM Technical Digest.
1993. 123–126.
27. H. Kawaura, T. Sakamoto, et al. Transistor characteristics of 14-nm-gatelength EJ-MOSFETs. IEEETrans. Electron Devices. 2000. 47. 856–860.
28. Silvaco International, Interactive Tools: ATLAS: Device Simulation
Framework. Trade Brochure.

86

APPENDIX A
ATHENA INPUT FILE: 45nm BIAXIAL STAINED SILICON NMOS

go Athena
# Establishing Initial Non-Uniform Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.boron=2.0e18 orientation=100 two.d
# Depositing epitaxial layer
epitaxy time=25 temp=800 thickness=0.02 c.boron=4.0e16
# Deposit Si & SiGe layer
deposit silicon thick=0.02 c.boron=1.0e16 divisions=10
deposit sige thick=0.015 c.boron=1.0e16 divisions=5
c.fraction=0.35
deposit silicon thick=0.009 c.boron=1.0e16 divisions=4
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 datafile="gateOxide.final"
# Vth Adjust Implant
implant boron dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.408093

87
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant phosphor dose=5.0e14 energy=13 tilt=0 rotation=0
crystal
# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant phosphor dose=1.0e16 energy=20 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=ssin.str
tonyplot ssin.str
quit

88

APPENDIX B
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
#Bias the drain with small voltage
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=0.1 vdrain=0.3 vfinal=1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init

89
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
solve vdrain=0.25 vstep=0.25 vfinal=3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=0.1 vdrain=3.5 vfinal=1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="ndibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay
quit

dibl_1.log dibl_2.log

90

APPENDIX C
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=ssin1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
#value extraction
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\

91
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin1.log
log off
solve vdrain=0.1
log outf=ssin0_1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_1.log
log off
solve vdrain=0.4
log outf=ssin0_4.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_4.log
log off
solve vdrain=0.5
log outf=ssin0_5.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \

92

1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_5.log
log off
solve vdrain=0.7
log outf=ssin0_7.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssin0_7.log
quit

93

APPENDIX D
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF BIAXIAL STRAINED
SILICON NMOS
go atlas
#
mesh infile=ssin.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=ssin1.log
solve vgate=1.1 outf=solve1
solve vgate=2.2 outf=solve2
solve vgate=3.3 outf=solve3
#
load infile=solve1
log outf=ssin1_1.log

94
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve2
log outf=ssin1_2.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve3
log outf=ssin1_3.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
tonyplot -overlay ssin1_1.log ssin1_2.log ssin1_3.log
quit

95

APPENDIX E
ATHENA INPUT FILE: 45nm CONVENTIONAL NMOS
go athena
# Establishing Initial Non-Uniform Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.boron=2.0e18 orientation=100 two.d
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 datafile="gateOxide.final"
# Vth Adjust Implant
implant boron dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.428
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant phosphor dose=7.5e14 energy=15 tilt=0 rotation=0
crystal

96

# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant phosphor dose=1.0e16 energy=20 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=convn.str
tonyplot convn.str
quit

97

APPENDIX F
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF CONVENTIONAL
NMOS

go atlas
#
mesh infile=convn.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=0.1 vdrain=0.3 vfinal=1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts

98
solve init
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=0.025 vstep=0.025 vfinal=0.3 name=drain
solve vdrain=0.25 vstep=0.25 vfinal=3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=0.1 vdrain=3.5 vfinal=1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="ndibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay

dibl_1.log dibl_2.log

99

APPENDIX G
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF CONVENTIONAL
NMOS
go atlas
#
mesh infile=convn.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=convn1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
#value extraction
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\

100
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn1.log
log off
solve vdrain=0.1
log outf=convn0_1.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_1.log
log off
solve vdrain=0.4
log outf=convn0_4.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_4.log
log off
solve vdrain=0.5
log outf=convn0_5.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \

101

1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_5.log
log off
solve vdrain=0.7
log outf=convn0_7.log
solve name=gate vgate=0 vfinal=3.0 vstep=0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convn0_7.log

102

APPENDIX H
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF CONVENTIONAL
NMOS
go atlas
#
mesh infile=convn.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=1
log outf=convn1.log
solve vgate=1.1 outf=solve1
solve vgate=2.2 outf=solve2
solve vgate=3.3 outf=solve3
#
load infile=solve1
log outf=convn1_1.log

103
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve2
log outf=convn1_2.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
#
load infile=solve3
log outf=convn1_3.log
solve name=drain vdrain=0 vfinal=3.3 vstep=0.3
tonyplot -overlay convn1_1.log convn1_2.log convn1_3.log
quit

104

APPENDIX I
ATHENA INPUT FILE: 45nm BIAXIAL STRAINED SILICON PMOS
go athena
# Establish Initial Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.arsenic=2.0e17 orientation=100 two.d
# Epitaxy
epitaxy time=25 temp=800 thickness=0.02 c.phos=4.0e16
# Deposit Si & SiGe layer
deposit silicon thick=0.02 c.arsenic=1.0e16 divisions=10
deposit sige thick=0.015 c.arsenic=1.0e16 divisions=5
c.fraction=0.35
deposit silicon thick=0.009 c.arsenic=1.0e16 divisions=4
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 \
datafile="gateOxide.final"
# Vth Adjust Implant
implant arsenic dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly

105
etch polysilicon left p1.x=0.408093
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant boron dose=25.0e13 energy=5 tilt=0 rotation=0
crystal
# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant boron dose=1.0e13 energy=9 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=ssip.str
tonyplot ssip.str

106

APPENDIX J
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS
go atlas
#
mesh infile=ssip.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=-0.1 vdrain=-0.3 vfinal=-1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init

107
# Bias the drain to 3 volts, 2 times, with small voltage
first
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
solve vdrain=-0.25 vstep=-0.25 vfinal=-3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=-0.1 vdrain=-3.5 vfinal=-1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="pdibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay

dibl_1.log dibl_2.log

108

APPENDIX K
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS

go atlas
#
mesh infile=ssip.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=ssip1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
#value extraction

109
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip1.log
log off
solve vdrain=-0.1
log outf=ssip0_1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_1.log
log off
solve vdrain=-0.4
log outf=ssip0_4.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_4.log
log off
solve vdrain=-0.5
log outf=ssip0_5.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)

110
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_5.log
log off
solve vdrain=-0.7
log outf=ssip0_7.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot ssip0_7.log

111

APPENDIX L
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF BIAXIAL STRAINED
SILICON PMOS
go atlas
#
mesh infile=ssip.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=ssip1.log
solve vgate=-1.1 outf=solve1
solve vgate=-2.2 outf=solve2
solve vgate=-3.3 outf=solve3
#
load infile=solve1
log outf=ssip1_1.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3

112
#
load infile=solve2
log outf=ssip1_2.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve3
log outf=ssip1_3.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
tonyplot -overlay ssip1_1.log ssip1_2.log ssip1_3.log
quit

113

APPENDIX M
ATHENA INPUT FILE: 45nm CONVENTIONAL PMOS
go athena
# Establish Initial Grid
line x loc=0.00 spac=0.075
line x loc=0.30 spac=0.025
line x loc=0.40 spac=0.025
line x loc=0.50 spac=0.050
#
line y loc=-2.5 spac=0.008
line y loc=-2.4 spac=0.006
line y loc=-2.2 spac=0.005
# Initialize Substrate Material
init silicon c.arsenic=2.0e17 orientation=100 two.d
# Gate Oxidation
diffus time=7 temp=900 dryo2 press=1.00 hcl.pc=3
#Extract Gate Oxide
extract name="GateOxide" thickness material="SiO~2"
mat.occno=1 x.val=0.3 \
datafile="gateOxide.final"
# Vth Adjust Implant
implant arsenic dose=1.0e10 energy=30 tilt=0 rotation=0
crystal
# Deposit Poly of Gate
deposit polysilicon thick=0.2 divisions=8
# Etch Poly
etch polysilicon left p1.x=0.424
# Poly Oxidation
method fermi
diffus time=3 temp=900 weto2 press=1.00
# Poly Doping
implant boron dose=15.0e13 energy=5 tilt=0 rotation=0
crystal

114

# Deposit Spacer oxide
deposit oxide thick=0.12 divisions=10
# Etch Spacer Oxide
etch oxide thick=0.12
# Source/Drain Implant
implant boron dose=1.0e13 energy=7 tilt=0 rotation=0
crystal
# Source/Drain Annealing
method fermi
diffus time=1 temp=900 nitro press=1.00
# Open Contact Window
etch oxide left p1.x=0.21
# Aluminium Deposition
deposit aluminum thick=0.03 divisions=2
# Etch Aluminium
etch aluminum right p1.x=0.18
#Mirror structure
struct mirror right
#Name structure
electrode name=source left
electrode name=gate x=0.5
electrode name=drain right
electrode name=backside backside
struct outfile=convp.str
tonyplot convp.str
quit

115

APPENDIX N
ATLAS INPUT FILE: DIBL CHARACTERISTICS OF CONVENTIONAL PMOS
go atlas
#
mesh infile=convp.str
# material parameter, model, method and output specific
material material=Si taun0=1e-7 taup0=1e-7
material material=SiGe taun0=1.0e-8 taup0=1.0e-8
model bgn consrh auger fldmob conmob print
contact name=gate n.polysilicon
interface qf=3e10
#use newton method
method newton
# save the structure with band diagram and plot it
output con.band val.band
save outf=test.str
#tonyplot test.str
# Bias the drain with small voltage
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
#Ramp the gate
log outf=dibl_1.log master
solve vgate=0 vstep=-0.1 vdrain=-0.3 vfinal=-1.5 name=gate
# extract device parameters
extract init inf="dibl_1.log"
extract name="pvt_1"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
log off
# Start again, ramp the drain to 3 volts
solve init
# Bias the drain to 3 volts......slowly at first....

116
solve vdrain=-0.025 vstep=-0.025 vfinal=-0.3 name=drain
solve vdrain=-0.25 vstep=-0.25 vfinal=-3.5 name=drain
# Ramp the gate again with another opened logfile...
log outf=dibl_2.log master
solve vgate=0 vstep=-0.1 vdrain=-3.5 vfinal=-1.5 name=gate
# extract the next device parameter with the drain now at 3
volts....
extract init inf="dibl_2.log"
extract name="pvt_2"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
- abs(ave(v."drain"))/2.0)
# Calculate a DIBL parameter....in V/V
extract name="pdibl" ($"pvt_1"-$"pvt_2")/(3.0-0.1)
tonyplot -overlay

dibl_1.log dibl_2.log

117

APPENDIX O
ATLAS INPUT FILE: Id-Vgs CHARACTERISTICS OF CONVENTIONAL
PMOS

go atlas
#
mesh infile=convp.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=convp1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
#value extraction

118
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp1.log
log off
solve vdrain=-0.1
log outf=convp0_1.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_1.log
log off
solve vdrain=-0.4
log outf=convp0_4.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_4.log
log off
solve vdrain=-0.5
log outf=convp0_5.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)

119
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_5.log
log off
solve vdrain=-0.7
log outf=convp0_7.log
solve name=gate vgate=0 vfinal=-3.0 vstep=-0.1
extract name="vt"
(xintercept(maxslope(curve(abs(v."gate"),abs(i."drain"))))
\
- abs(ave(v."drain"))/2.0)
extract name="subvt" \
1.0/slope(maxslope(curve(abs(v."gate"),log10(abs(i."drain")
))))
tonyplot convp0_7.log

120

APPENDIX P
ATLAS INPUT FILE: Id-Vds CHARACTERISTICS OF CONVENTIONAL
PMOS

go atlas
#
mesh infile=convp.str
#
models srh cvt boltzman print temperature=300
#
mobility bn.cvt=4.75e+07 bp.cvt=9.925e+06 cn.cvt=174000
cp.cvt=884200 \
taun.cvt=0.125 taup.cvt=0.0317 gamn.cvt=2.5
gamp.cvt=2.2 \
mu0n.cvt=52.2 mu0p.cvt=44.9 mu1n.cvt=43.4
mu1p.cvt=29 mumaxn.cvt=1417 \
mumaxp.cvt=470.5 crn.cvt=9.68e+16 crp.cvt=2.23e+17
csn.cvt=3.43e+20 \
csp.cvt=6.1e+20 alphn.cvt=0.68 alphp.cvt=0.71
betan.cvt=2 betap.cvt=2 \
pcn.cvt=0 pcp.cvt=2.3e+15 deln.cvt=5.82e+14
delp.cvt=2.0546e+14
#
contact name=gate n.poly
#
interface s.n=0.0 s.p=0.0 qf=3e10
#
method newton gummel itlimit=25 trap atrap=0.5 maxtrap=4
autonr \
nrcriterion=0.1 tol.time=0.005 dt.min=1e-25 damped
delta=0.5 \
damploop=10 dfactor=10 iccg lu1cri=0.003 lu2cri=0.03
maxinner=25
solve init
solve vdrain=-1
log outf=convp1.log
solve vgate=-1.1 outf=solve1
solve vgate=-2.2 outf=solve2
solve vgate=-3.3 outf=solve3
#
load infile=solve1
log outf=convp1_1.log

121
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve2
log outf=convp1_2.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
#
load infile=solve3
log outf=convp1_3.log
solve name=drain vdrain=0 vfinal=-3.3 vstep=-0.3
tonyplot -overlay convp1_1.log convp1_2.log convp1_3.log
quit