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**Diode - 1 includes Diode under open circuit, built in potential barrier, electric field,
**

width of potential barrier etc.

1.

**In a uniformly doped abrupt PN junction, the doping level of the N-side is four times the
**

doping level of the P-side. The ratio of the depletion layer widths is

[G’90]

a. 0.25

b. 0.50

c. 1.0

d. 2.0

2.

a.

b.

c.

d.

The built in potential (Diffusion Potential) in a PN junction

[G’93]

**Is equal to the difference in the Fermi level of the two sides, expressed in volts.
**

Increases with the increase in the doping levels of the two sides

Increases with the increase in temperature

Is equal to the average of the Fermi levels of the two sides

3.

**In a P+N junction diode under reverse bias, the magnitude of electric field is maximum
**

at [G’07]

**a. The edge of the depletion region on the p side
**

b. The edge of the depletion region on the n-side

c. The P+N junction

d. The centre of the depletion region on the n-side

4.

**Consider a silicon P-N junction at room temperature having the following parameters :
**

[G’09]

Doping on the n-side = 1 x 1017 cm-3

Depletion width on the n-side = 0.1 um

Depletion width on the p-side = 1.0 um

Intrinsic carrier concentration = 1.4 x 1010 cm-3

Thermal voltage = 26 mV

Permittivity of free space = 8.85 x 10-14 F.cm-1

Dielectric constant of silicon = 12

The built in potential of the junction is

(A) 0.70 V

(B) 0.76 V

(C) 0.82 V

(D) cannot be estimated from the given data

80 MV . cm-1. Injection and subsequent diffusion and recombination of minority carriers Injection and subsequent drift and generation of minority carriers Extraction and subsequent diffusion and generation of minority carriers Extraction and subsequent drift and recombination of minority carriers [G’13] . cm-1. b.The peak electric field in the device is (A) (B) (C) (D) 0. the sequence of events that best describes the mechanism of current flow is a.80 MV . cm-1.15 MV . directed from p-region to n-region 0. directed from p-region to n-region 1. directed from n-region to p-region 5. In a Forward Biased PN junction diode. d. directed from n-region to p-region 1. c.15 MV . cm-1.

Consider the circuit shown in figure (a).Diode . 1. effect of temperature on Io and diode voltage. V-I characteristics. then the output waveform VO is [G’93] . (b) Assuming that the current through the reverse biased diode is saturated at Io. calculate the Voltage drop across the forward biased diode. If the diode used here has the V-I characteristic as in figure (b). (a) Two ideal and identical (ideality factor ƞ = 1) junction diodes are connected in series as shown in figure. static and dynamic resistance.2 includes forward bias. Assume KT = 26meV. [GATE'90] Show that exp (eV1/KT) + exp (-eV2/KT) = 2 where V1 and V2 are the voltage drops across the diodes D1 and D2. reverse bias. 2.

Two identical silicon junction diodes. Log I vs. D1 and D2 are connected back to back as shown figure. [GATE’95] 4. V I vs. Evaluate the voltage VD1 and VD2 across the diode D1 and D2 by assuming KT/q to be 25mV. V . 3. b. log V I vs. The reverse saturation current . IS of each diode is 10-8 amps and the breakdown voltage is 50 volts. c. log V Log I vs. d. The static characteristic of an adequately forward biased PN junction is a straight line. if the plot is of [GATE’98] a.

Under the conditions stated above. In the figure. a certain germanium diode requires a forward bias of 0. IS . c. If the temperature rises to 400C. 6. At 300oK.5. for the diode is 1pA. b.718 volts. then compute the current I through the circuit. When the temperature of the diode is 200C. 1 5 4 x 103 8 x 103 .1435 volts. d. VD is found to be 700 mV. D1 and D2 are identical diodes with ideality factor of unity. VD becomes approximately equal to [GATE’02] 7. a silicon diode is carrying a constant current of 1 mA. The thermal voltage VT = 25mV. For the circuit shown in figure. If the reverse saturation current . the closest approximation of the ratio of reverse saturation current in germanium diode to that of silicon diode is [GATE’03] a. where as a certain silicon diode requires a forward bias of 0. Calculate VF and VR b. for a diode current of 1 mA. [GATE'01] a.

b.9 µm 8 µm 12 µm . c. In abrupt PN junction. For a reverse bias of 7. b. A P+N junction has a built in potential of 0. d. 2. the depletion layer width will be : [GATE’07] a.8 volts.8. d. The reverse saturation current at 40oC for the same bias is approximately [GATE’05] 30 pico Amp 40 pico Amp 50 pico Amp 60 pico Amp 10. a. the doping concentrations on the p-side and n-side are NA = 9 x 1016 /cm3 and ND = 1 x 1016 /cm3 respectively. c. d. A silicon PN junction at a temperature of 20oC has a reverse saturation current of 10 pico Amp.3 µm 2.25 µm 0. The depletion width on the p-side is [GATE’04] a. c.2 volts is 2 µm. The depletion layer width at a reverse bias of 1. The PN junction is reverse biased and the total depletion width is 3 µm. b.2 volts .7 µm 0.75 µm 9. 4 µm 4.

b.11. the forward bias voltage across the PN junction [GATE’11] a. When the temperature is increased by 10oC. The forward dynamic resistance of a junction diode varies __________________ as the forward current. c. d. A silicon PN junction is forward biased with a constant current at room temperature. [GATE'94] . Increases by 60 mV decreases by 60 mV Increases by 25 mV decreases by 25 mV 12.

c. and piece wise linear diode model. 1.This set of questions include Ideal diode model. the voltage Vo is a.1) (D) max (- . the diode is ideal. For the circuit shown in figure. In the circuit shown.1) Vi.1) (C) min(-Vi. The voltage V is given by [GATE’09] (A) Min (Vi.1) (B) max (Vi. [GATE’00] 2 volts 1 volts -1 volts None of the above 3. the current ID flowing through the ideal diode equal to [GATE’97] 2. d. b. Simplified diode model. In the circuit below.

9.67 mA D. 1 – cos(wt) d. 1 – sin(wt) .3 mA 5.2 mA The diodes and capacitors in the circuit shown are ideal. Sin(wt) c. The i-v characteristics of the diode in the circuit given below are [GATE'12] The current in the circuit is A. 6. C. 6.4. Cos(wt) . The voltage v(t) across the diode D1 is [GATE’12] a.1 b. 10mA B.

.25 pF 0. b.5 pF 5. then for Vbi + VR = 4 volts. the capacitance at a reverse bias voltage of 99 volts is equal to …. c. a. d. when its is forward biased 2. CJ. of an abrupt PN junction with constant doping on either side varies with reverse bias. c. [GATE’91] 3. the relative permittivity of silicon Ɛr is 11. The depletion capacitance. c. In a junction diode [GATE'90] The depletion capacitance increases with increase in the reverse bias The depletion capacitance increases with decrease in the reverse bias The diffusion capacitance increases with increase in the forward bias The diffusion capacitance is much higher than the depletion capacitance. VR as [GATE'95] CJ ∞ VR CJ ∞ VR-1 CJ ∞ VR -1/2 CJ ∞ VR -1/3 a. d. the depletion capacitance of the diode per square meter is [GATE’05] . A silicon PN junction diode under reverse bias has depletion region of width 10µm. Cj will be [GATE’04] 4 pF 2 pF 0. If the built in voltage is 1 volt.85x10-12 F/m. Let Vbi be the built in potential of this junction and VR be the applied reverse bias.7 and the permittivity of free space Ɛo = 8. b. If the junction capacitance (Cj) is 1 pF for Vbi + VR = 1 volt. 4.Previous GATE Questions on Diode Capacitances (Diffusion and Transition Capacitance) 1. The small signal capacitance of an abrupt P+N junction is 1 nF/cm2 at zero bias. b. d. a. Consider an abrupt PN junction.

a. c. b. 100 µF 10 µF 1 µF 20 µF 6. Which of the following is NOT associated with a P-N junction ? [GATE'08] (A) Junction capacitance (C) Depletion Capacitance (B) Charge Storage Capacitance (D) Channel Length Modulation . d.

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