Mindanao State University-Iligan Institute of Technology

College of Engineering
Department of Electrical and Electronics
Communications Engineering

Logic Gates: INVERTER

EE 177.1

Submitted by:
Ceferino Kevin A. Tan

Submitted to:
Mr. Jefrey Pasco

December 04, 2014

This bubble denotes a signal inversion (complementation) of the signal and can be present on either or both the output and/or the input terminals. NAND and NOR symbols at their output to represent the logical operation of the NOT function. Logic Gates: INVERTER I. The NOT gate (inverter) Symbol Input Output false true true false Figure 2. The standard NOT gate is given a symbol whose shape is of a triangle pointing to the right with a circle at its end. A NOT gate performs logical negation on its output. OBJECTIVES:  To study the basic logic gate: inverter. is used in digital circuits to produce the desired logical function. its representation by truth table.Activity 1. Truth table for a NOT gate . BASIC CONCEPT A NOT gate. II.  To familiarize with the Quartus II computer-aided design tool in the inverter simulation. logic diagram and Boolean algebra. Figure 1. This circle is known as an “inversion bubble” and is used in NOT. often called an inverter.  To observe the pulse response of the inverter.

A 5-page preliminary project setting will appear.Run the program and use the Quartus II to create the project.a for Project name and directory Figure 4. Boolean algebra III.altera. 2. PROCEDURE: 1. page 3 of 5 (family and device settings) next page 4 of 5. Download and install Quartus II.com) IV. See figure 4. Click the Symbol tool ( ) and choose the NOT gate 6. a design software for a programmable logic devices. Click File Newblock diagram/ schematic fileok 5. Nextpage 2 of 5(add files)next. Click the Pin tool( below) ) for the input and output (follow the logic diagram . Project name and directory 3. (EDA tool settings)next. MATERIALS: Computer Quartus II Web Edition (www. page 5 of 5 (Summary)Finish 4.INPUT OUTPUT A NOT A 0 1 1 0 Figure 3. Click FileNew Project wizard Next.

Press F9 to run 13. Right click Input clock and choose: o Rising ( if you want your input be 1) o Falling ( if you want your input be 0) 12. a window for the Flow summary will appear as the project compiles. Importing input and output to wave output window 11. Click the selected projectcompilecompile selected. Logic Diagram 7. fill in the necessary requirements to proceed Add Existing FileBrowse . Click File NewProject. 8. After compilation.Figure 5. Click Compile . open the folder where the project was saved simulationmodelsim VHO file (usually the first file in the list) OK 9. a check mark in the status column will appear as the compilation finishes simulate start simulation Work the project to be simulatedOK 10. Observe wave output . open the Modelsim to start simulating the project created in the Quartus II. Send the input and output to the wave output window to run test the designed diagram by selecting the input and output then right clickadd towave selected signals Figure 6.

Logic and Computer Design Fundamentals. a false input results in a true output (the rising part of the square wave). CONCLUSION: As observed in the output. It is a single input device which has an output level that is normally at logic level “1” and goes “LOW” to a logic level “0” when its single input is at logic level “1”. . Kime. In other words. then the output will be false (the falling part of the square wave). in other words it “inverts” (complements) its input signal. Prentice Hall. similarly. Mano. 73. Morris and Charles R. The output from a NOT gate only returns “HIGH” again when its input is at logic level “0”. Third Edition. OUTPUT Figure 7. M. 2004. Wave Output VI.V. p. a NOT gate or inverter performs logical negation on the input. If the input is true. References: 1.

2. Joshua Tynjala (2008). Basic Electronics tutorials.html .ws/logic/logic_4.ly/lessons/not-gate 3. NOT gate (Inverter). http://www. Wayne Storr (1999). http://logic.electronics-tutorials.