UNDER PEER REVIEW

Original Research Article
A Proposed Modified Constant Frequency
Variable Duty PWM Based Speed Control
Technique for DC Motor Drives: A New Method
to Achieve More Precise Control over Speed

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ABSTRACT
In this paper, the authors have proposed a new method for speed control of DC motor drives
via modified constant frequency-variable duty (CFVD) pulse width modulation (PWM)
technique. An extra control signal is subtracted from the conventional fixed amplitude CFVD
PWM signal to obtain the modified speed control signal. The peak amplitude of the
subtracted extra control signal provides an additional control over the speed of DC motor
along with the duty cycle of the ordinary PWM signal. A circuit for generating the modified
control signal has been designed and fabricated. Finally the experiments are carried out to
study the speed controlling characteristics of a 9 V DC motor drive. More precise control
over speed, better transient response and abrupt electrical breaking of the motor have been
achieved by using the proposed speed control signal as compared to the conventional CFVD
PWM speed control signal.
Keywords: Pulse width modulation; DC motor, chopper control; duty cycle; modified CFVD
PWM; electronic breaking; transient response.

1. INTRODUCTION
Pulse width modulation (PWM) which is synonymous with pulse duration modulation (PDM)
is a commonly used technique for the speed of DC motor drives [1-4]. The average value of
the voltage and current fed to the DC motor can be controlled by turning an electronic switch
between the supply and motor on and off at a fast pace. Longer the switch is on as
compared to the off periods, higher the power delivered to the motor. Since the speed (in
rpm) of a DC motor is directly proportional to the average power delivered to it, thus by
varying the supplied average power by means of variable on time period of the electronic
switch, the speed of the DC motor can be controlled. The term ‘duty cycle’ is the ratio of the
on time to the regular interval to the total time period. A low duty cycle corresponds to low
power, since the supplied power is off for most of the time and vice versa. The PWM
switching frequency has to be much faster than the response time of an electromechanical
load such as DC motor drives. Typically from a few KHz to tens of KHz switching speed is
used to control the speed of a variable speed DC motor drive [5]. The primary advantage of
PWM based speed control is that, the power loss in the switching devices is almost
negligible. When a switch is off, then there is practically no current through it and when the
switch is on, then there is almost no voltage drop across it. Power loss, being the product of
voltage and current, is thus zero in both the abovementioned cases.
PWM based speed control techniques are also sometimes called chopper control which are
more power efficient, less complicated and less bulky as compared to the ordinary rheostat
based speed control mechanisms of DC motor drives. Generally there are two different types

(b) 30%. Moreover the transient response the rotating drives are poor due to the presence of only a single controlling parameter. A circuit for generating the modified control signal has been designed and fabricated. In the first method. duty cycle of the PWM signal and absence of any other control to minimize the time required to increase or decrease the speed of the drive within any specified range. The extra control signal is subtracted from the conventional fixed amplitude CFVD PWM speed control signal to obtain the modified speed control signal. i. Conventional CFVD PWM Speed Control Technique The typical CFVD PWM control signals of constant time period Tc (constant frequency fc = 1/Tc) and peak amplitude Vc are shown in Figure 1 for different duty cycles (dc = Ton/Tc. the duty cycle is varied keeping the frequency of the controlling signal fixed to vary the average voltage across the DC motor drive. 2. The disadvantages associated with the conventional method are also mentioned. the proposed method of DC motor speed control via modified CFVD PWM is discussed in detail. 2. THEORY In this section. This fact may result damage to the rotating mechanism of the armature which intern may reduce the life of the DC motor drive. such as (a) variable frequency-constant duty (VFCD) PWM and (b) constant frequency-variable duty (CFVD) PWM. Finally the experiments are carried out to study the speed control characteristics of a 9 V DC motor by using the proposed method and those are compared with the characteristics obtained from ordinary CFVD PWM control technique. the frequency of the controlling signal may be varied keeping the duty cycle fixed (say at 50%) to vary the average voltage across the DC motor drive. In this paper.1. The second technique requires less complex circuitry to achieve wide range of variations in speed of the DC motors. Finally.e.UNDER PEER REVIEW 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 of PWM techniques may be used to control the speed of DC drives [6]. The peak amplitude of the extra control signal provides an additional control over the speed of DC motor along with the duty cycle of the ordinary PWM signal. The next section describes the theoretical background associated with the conventional CFVD PWM based speed control technique in brief along with the proposed technique in detail. And in the second case. where Tc = Ton + Toff) such as (a) 10%. But the primary disadvantage of the conventional CFVD PWM technique is large abrupt mechanical shocks (kicks) have to be accepted by the rotating armature of a DC motor due to the application of large amplitude narrow pulse trains to achieve very low speed. The design and fabrication methodologies of the proposed circuit to generate modified PWM signal are discussed in the section 3. which intern makes the entire system more cost effective. initially the conventional method of ordinary CFVD PWM technique for speed control of DC motor drives is discussed in brief. The results obtained from the experiments are presented and discussed in the section 4. better transient response and abrupt electrical breaking of the DC motor drive are achieved by using the proposed method. Mathematically the conventional CFVD PWM control signal may be expressed as v c t   Vc 0 for iTc  t  dcTc  iTc   . Finally the paper is concluded in the section 5. (d) 70% and (e) 90%. the authors have proposed a new method for speed control of DC motors by modifying the conventional CFVD PWM technique via another extra control signal of special form. for dcTc  iTc   t  i  1Tc  (1) . (c) 50%. The rest of the paper is organized as follows. More precise control over speed.

the rotating armature has to accept abrupt mechanical shocks (kicks) consecutively due to applied large amplitude narrow pulse trains. 96 Thus the average voltage Vavc of the control signal (vc(t)) is directly proportional to the duty 97 cycle (dc). (d) 70% and (e) 90%. 2. ………… . peak amplitude 9 V for different duty cycles such as (a) 10%. (c) 50%. 3. the speed of the DC motor can be varied. (b) 30%.2. the average voltage ( Vavc ) can be 98 99 100 101 102 103 104 105 106 107 108 109 110 changed from 0 to Vc. which may cause damage to the armature and consequently reducing the life of the DC motor. Very fast reduction or increase in speed is also cannot be achieved due to the inertia of the armature and absence of any additional control other than dc. the speed of the DC motor can only be varied within a single range by varying dc. But for constant Vc.UNDER PEER REVIEW 88 89 90 91 where i = 0. Thus by varying the duty cycle of the control signal. due to application of train pulses of very small duty cycle (dc ≤ 10%) to run the DC motor in very low rpm for long time. 1. Typical conventional CFVD PWM control signals of frequency 500 Hz. The Proposed Technique . 1. By changing the value of dc from 0 to 100%. Now the average value of the control signal (vc(t)) for duty cycle of dc may be calculated as Vavc  1 Tc i 1 Tc  vc t dt  iTc d T iT  i 1 T  1    Vc dt   0 dt   dcVc . Speed of the DC motor (N in rpm) is directly proportional to Vavc . etc. Moreover. Tc  iT d T iT   c c c c c c c (2) c 92 93 94 95 Fig. 2.

Vs) provides an additional control over speed of the DC motor along with the duty cycle (dc) of the PWM control signal. which intern leads to achieve longer life of DC motors. The second term of the same equation is a function of dc. better transient characteristics can also be achieved due this additional control mechanism. θsc is the initial phase of vs(t) and Ks is a constant associated with the circuit. The value of θsc may remains within the range 0 ≤ θsc ≤ (2π/n).  for dcTc  iTc   t  i  1Tc  for iTc  t  dcTc  iTc  (3) where i = 0. (n – 1). ∴ Ts = nTc. 2. where n is an integer greater than one). ………………. a signal of form vs(t) = Vs(Ks –sin(2πfst)) (where fs = 1/Ts and Ts is the time period) of lower fundamental frequency (i.e. The fundamental frequency of the signal vs(t) is taken to be n-times smaller as compared to the fundamental frequency of vc(t) (i. The average voltage of the overall control signal (i. fs < fc. The peak amplitude of the subtracted signal vs(t) (i.  nTc   (4) The first term of equation (4) may be varied by varying either dc or Vs or both simultaneously. Thus by varying dc. Faster control over the speed reduction or increment.e. i. Moreover. The mathematical expression of the overall control signal is given by   2t  v sc t   Vc  Vs K s  sin   sc   nTc   0   .UNDER PEER REVIEW 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 In the proposed method.e. the average control voltage ( Vavsc ) may be varied and consequently the speed of the DC motor may be varied.Vc . Vavsc ) becomes negative for  Vs   Vc    1 ndcTc        ndc K sTc    K s    ndc K sTc  d c  0 . 1.e. Vs. 3. The abovementioned modified PWM signals are shown in Figure 2 for different duty cycles and for different Vs/Vc ratio. the peak amplitude of the subtracted signal vs(t) (i. sc  ). Moreover. Now the average value of vsc(t) may be calculated as Vavsc  Vs n1   1     v t dt  d V  K V   sc c c s s Ts 0 nTc i 0  Ts dcTc iTc   iTc  2t   sin   sc  dt  . due to gradual increment or decrement of the amplitudes of the consecutive narrow pulses. n and θsc (say dc . n. (5) Thus the direction of the rotation of the DC motor can be reversed by changing the Vs/Vc ratio above the specified value given in equation (5).e.e. Electrical breaking of the DC motor can also be achieved by varying Vs for a particular dc. Vs) provides an additional control over Vavsc which intern leads to an additional control over the speed of the DC motor. ∴ Ts > Tc) is subtracted from the conventional CFVD PWM speed control signal (vc(t)) to obtain the modified control signal vsc(t) = vc(t) – vs(t). fs = fc/n. for constant Vc. possibility of abrupt mechanical shocks on the armature rotating in lower speed may also be avoided. . for smaller duty cycles (dc ≤ 10%).

e. to construct the extra control signal vs(t).e. (f) and (j). i. (g) and (k) and 1. An analog subtractor circuit may be used to obtain the difference between the terms KsVs and Vs sin(2πfst). 0. Finally another analog subtractor circuit may be used to obtain the proposed modified PWM control signal. DESIGN AND FABRICATION OF THE CIRCUIT The block diagram of the system to generate the proposed modified PWM signal for speed control of DC drives is shown in Figure 3. (h) and (l).UNDER PEER REVIEW 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 Fig.22 in (a). Variable amplitude of the sinusoidal signal at the secondary of the transformer may be achieved via a potentiometer (POT) connected across the secondary terminals. The AC main supply voltage (230 V. .67 in (b). the Vs/Vc ratio are taken to be 0. (e) and (i).11 in (c). 2. 1. here the frequency and peak amplitude of the pulse train (vc(t)) are taken to be fc = 500 Hz and Vc = 9 V respectively. i. 3.78 in (d). At first a circuit capable of generating fixed amplitude CFVD PWM signal (vc(t)) has been designed. 50% in (e) – (h) and 90% in (i) – (l). Typical proposed modified PWM control signals (here n = 10). vsc(t) = vc(t) – vs(t) as shown in Figure 3. The adjustable amplitude sinusoidal signal must be first rectified via a full-wave rectifier and then filtered by using a suitably designed low pass filter (LPF) to obtain the term KsVs (where Ks = 2/π). the duty cycles of the pulse train (vc(t)) are taken to be 10% in (a) – (d). 50 Hz) has to be stepped down via a centre-tapped step down transformer.

where Rf2 is the forward resistance of the diode D2. where Rf1 is the forward resistance of the diode D1. The total discharging period may be calculated as Toff = 0. Vs sin(2πfst)) is given as another input to the subtractor circuit at the inverting input terminal. i.69(Rb + Rf2)C [7].69(R1 + Rf1 + Ra)C [7]. but summation of them will remain always fixed. diode D1 and finally Ra. but the frequency (fc) will remain unchanged. the duty cycle (dc) will vary accordingly. Ra + Rb = 10 KΩ. for a particular position of POT1. i. up to 6 V). Say.69(R1 + Rf1 + Rf2 + Ra + Rb)C] and dc = Ton/Tc = (R1 + Rf1 + Ra)/(R1 + Rf1 + Rf2 + Ra + Rb).69(R1 + Rf1 + Rf2 + Ra + Rb)C.e. Thus the expressions of frequency and the duty cycle may be written as fc = 1/Tc = 1/[0. the capacitor will discharge through the resistor Rb and diode D2.09. The output of this circuit (at pin 3) provides a square-wave of fixed amplitude Vc = 9 V and frequency fc = 483. where Ks = 2/π and fs = 50 Hz.3 µF.e. Block diagram of the system to generate the proposed modified PWM signal. The voltage across the POT2 (i. the left side of it. i. After the complete charging up to 2Vcc/3. The duty cycle of the output square-wave may be varied by adjusting the 10 KΩ potentiometer (POT 1). The final designed circuit is shown in Figure 4. . 50 Hz sinusoidal signal. 3 V). 3.1 µF ceramic disk capacitors are connected in parallel to obtain the desired value of the frequency determining capacitor. Finally a motor driver circuit made of CL 100 n-p-n BJT and 1 KΩ resistance is used to drive the 9 V DC motor via the proposed control signal (vsc(t)) as shown in Figure 4. Thus by adjusting POT1. The discharging will occur until the voltage across the capacitor just falls below Vcc/3 (i. A 555 timer IC based astable multivibrator circuit is used to generate fixed amplitude CFVD PWM signal (vc(t)). Therefore the output waveform is the desired CFVD PWM control signal (vc(t)) whose duty cycle (dc) may be changed by adjusting the POT1 keeping the frequency of oscillation (fc) unchanged.e. The time period of the output square-wave is given by Tc = Ton + Toff = 0. from wiper to the cathode of the diode D1 has the value Ra and similarly the right side of POT1.e. then the frequency determining capacitor. Thus at the output of the will provide the desired extra control signal vs(t) = Vs(Ks –sin(2πfst)) with adjustable Vs via POT2. C = 0.e. These charging and discharging processes will be continued repetitively. Thus the total charging time may be easily calculated as Ton = 0.e. Another similar analog subtractor circuit finally used to obtain the difference between vc(t) and vs(t) to construct the proposed modified CFVD PWM signal vsc(t) = vc(t) – vs(t). Initially the offset nullification of the Op-Amp has been achieved by adjusting the 10 KΩ POT3 as shown in Figure 4. The capacitor C will be charged up to 2/3 of Vcc (i. A centre-tapped transformer (T) is used to step down the 230 V. VEE = –20 V). from the wiper to the anode of the diode D2 have the value Rb (obviously Ra + Rb = 10 KΩ). C will be charged from the 9 V DC supply through R1 = 500 Ω resistor. A full-wave rectifier circuit comprising of two rectifying diodes (D3 and D4) cascaded with a shunt capacitor (1000 µF) LPF is used to obtain the steady term KsVs (here Ks = 2/π) which is fed at the non-inverting input of the analog subtractor circuit made of IC 741 operational amplifier (biased via VCC = +20 V. i. i. Three 0. 50 Hz AC main supply to 18 – 0 – 18 V. If the POT1 is adjusted then both the values of Ra and Rb will change simultaneously.e.UNDER PEER REVIEW 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 Fig. after which again the charging will start through the previous path as mentioned earlier.e. A 10 KΩ potentiometer (POT2) is connected across the secondary terminals to obtain the adjustable AC voltage amplitude (Vs) at the secondary.

0 Light” software [8].10. Vs = 2 V.e. 4. 2. the duty cycle of the (dc) of the PWM signal has been varied from 5 – 95% in a step increment of 5% by adjusting the POT1 at each case and observing the PWM waveform at the pin 3 of IC 555 in channel 2 of the DSO display and for each and every value of dc the average value of vsc(t) (i. The complete PCB layout of the designed circuit has been sketched via “EAGLE 5. 12. the said PCB has been fabricated via chemical etching procedure [9] and finally the components are carefully soldered on the fabricated PCB to obtain the complete module to carry out experimental measurements. 10. Vs = 10 V. Initially the accuracy of performance of the fabricated circuit has been verified by measuring average voltages of the modified PWM signal ( Vavsc ) at different duty cycles (dc) of the PWM signal for different peak amplitudes of the extra control signal (Vs). Vs = 8 V. For particular value of Vs. Vavsc ) has been measured by using a DC voltmeter connected across the DC motor (not shown in Figure 4). Vs = 6 V. Both the theoretically (equation (4)) and experimentally obtained variations of average voltage across the 9 V DC motor with duty cycle of the PWM signal for different values of peak amplitude of the extra control signal such as Vs = 0 V. EXPERIMENTAL RESULTS AND DISCUSSION After fabrication of the designed circuit described in the previous section. Vs = 4 V. Vs = 14 V and Vs = 16 V are shown in Figures 5 (a) – (i). Vs = 12 V. 4. 4. It is interesting to observe . After obtaining the layouts.UNDER PEER REVIEW 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Fig. At first the value of Vs has been set at a particular value (any one of 0. the experiments are carried out to study the speed control characteristics of a 9 V DC motor drive via the proposed method and results are compared with those obtained via the conventional CFVD PWM speed control technique. The final designed circuit to generate the proposed modified PWM signal. 6. 8. 14 and 16 V) by adjusting the POT2 and by observing the waveform of Vs sin(2πfst) at the input of the full-wave rectifier section in channel 1 of a digital storage oscilloscope (DSO) display.

Vs = 8 V. Variations of applied average voltage across the 9 V DC motor with duty cycle of the PWM signal for different values of peak amplitude of the extra control signal such as (a) Vs = 0 V. Vs = 2 V. 5. (d) Vs = 6 V.UNDER PEER REVIEW 241 242 243 from Figures 5 (a) – (i). It is observe from Figures 6 (a) – (i) sc sc that for Vs ≤ 14 V both the values of I av 0 and Vav for all dc values are found to be positive sc sc (i. This reversal of sign of Vavsc due to Vs > 14 V indicates the change in the direction of rotation of the DC motor drive. (e) Vs = 8 V. (c) Vs = 4 V. (g) Vs = 12 V. Vs = 10 V. It is also noteworthy that the values of Vavsc become negative for all dc (5 – 95%) while the 244 245 value of Vs exceeds 14 V. Vs = 14 V and Vs = 16 V are shown in Figures 6 (a) – (i). (h) Vs = 14 V and (i) Vs = 16 V. 257 258 259 each and every average voltage across it ( Vavsc ) have been measured by using a DC ammeter connected series with the DC motor drive (not shown in Figure 4). quadrant (I) operation).e. Vs = 12 V. Vs = 6 V. here fc = 483. but for Vs > 14 V both the values of I av 0 and Vav for all dc values . fs = 50 Hz and θsc is chosen to be any random value within the range 0 ≤ θsc ≤ (2π/n) for each case of theoretical calculation. (f) Vs = 10 V.09 Hz. 246 247 248 249 250 251 252 253 254 255 256 Fig. Vs = 4 V. The variations of sc average current through the 9 V DC motor ( I av 0 ) under no load or free running condition with 260 261 262 263 264 sc The average current through the DC motor ( I av 0 ) under no load or free running condition for applied average voltage across it ( Vavsc ) for different values of peak amplitude of the extra control signal such as Vs = 0 V. the theoretical and experimental results are close in agreement which intern proves that the accuracy of performance of the fabricated circuit is sufficient. (b) Vs = 2 V.

(b) Vs = 2 V. 278 279 280 average voltage across it ( Vavsc ) with peak amplitude of the extra control signal (Vs) for different duty cycles (dc) of the PWM signal are shown in Figure 7. 270 271 272 273 274 275 276 277 Fig. (Vs)Critical = πVc/2 = 14. (g) Vs = 12 V. this value is exactly equal to the critical value of Vs obtained from equation (5) above which the sign reversal of sc sc both I av 0 and Vav occur. (f) Vs = 10 V. (d) Vs = 6 V. . i. (e) Vs = 8 V.UNDER PEER REVIEW 265 266 267 268 269 are found to be negative which indicates the quadrant (III) operation leading to reversal in direction of rotation. It is 281 282 283 284 sc Variations of no load average current ( I av 0 ) through the 9 V DC motor drive and applied sc sc interesting to note from Figure 7 that signs of both I av 0 and Vav reversed from positive to negative while the value of Vs increased just above 14. (h) Vs = 14 V and (i) Vs = 16 V. Variations of average current through the 9 V DC motor under no load or free running condition with applied average voltage across it for different values of peak amplitude of the extra control signal such as (a) Vs = 0 V. (c) Vs = 4 V.137 V (where Vc = 9 V).137 V precisely. It is observed from Figure sc sc 7 that both the I av 0 and Vav decrease with the increase of Vs for all values of dc.e. 6.

for any fixed dc > 0) may be achieved by abruptly changing the value of Vs just above critical value of it. i. (Vs)Critical = 14. keeping dc fixed as well as by abruptly varying dc from 90% to 10%. Variations of no load average current through the 9 V DC motor and applied average voltage across it with peak amplitude of the extra control signal for different duty cycles of the PWM signal.e.137 V. breaking time (tb) have been measured for five times via a precise online stopwatch [11] and finally average value of tb has been calculated for each case. keeping dc fixed is more shaper and takes less breaking time as compared to its other counterpart. Photo-contact tachometer enables direct rpm measurements sensed from an easy to aim visible light beam directed toward a rotating shaft without mechanical contact. keeping Vs fixed and the results are given in Tables 1 and 2 respectively. The speed of the 9V DC motor (N) in rpm under no load condition has been measured at different duty cycles (dc) of the PWM signal for different peak amplitudes (Vs) of the extra control signal via a photo-contact tachometer (model DT-205L [10]). For each of the abovementioned cases the time required for achieving the steady state minimum speed. Two types of electronic breaking characteristics of the 9 V DC motor drive are studies by abruptly varying Vs from 0 V to 14.e. starting from minimum speed (Nmin) up to the maximum speed (Nmax)) may be selected by selecting the corresponding value of Vs (easily obtainable from Figure 8 (a)) and the speed of the DC drive may be varied from the selected Nmin to Nmax by varying the duty cycle (dc) of the PWM control signal. A comparative study of both the said electronic breaking methods from Table 1 and 2 reveals that the electronic breaking by abruptly varying Vs from 0 V to 14.137 V for which the speed of rotation will be either zero or its direction will be reversed. The range of the speed (in rpm) of the DC motor (i.e. 7.137 V. Moreover. i. It is interesting to observe from Figure 8 (a) that the parameter Vs provides an extra control over speed along with the dc.e. it is observed from Figure 8 (b) that the electronic breaking of the rotating DC motor drive rotating in any speed (i. . leading to more precise measurement of speed of the rotating shaft of the DC motor under no load or free running condition.UNDER PEER REVIEW 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 Fig. Variations of speed of the DC motor under no load condition with duty cycles of the PWM signal for different peak amplitudes of the extra control signal and with peak amplitude of the extra control signal for different duty cycles of the PWM signal are shown in Figure 8.

90 75.51 Nmin (rpm) 131.60 1136.68 -174. 300 – 500.27 tb (ms) 1059 941 872 797 651 602 523 198 504 The transient speed control characteristics of the DC motor drive under test have been studied for different speed ranges such as 0 – 100.25 819. Electronic breaking characteristics by abruptly varying dc from 90% to 10%.38 56. 500 – 700. Electronic breaking characteristics by abruptly varying Vs from 0 V to 14.82 644. 700 – 900.UNDER PEER REVIEW 319 320 321 322 323 Fig.50 970.89 478. Variations of speed of the DC motor under no load condition (a) with duty cycles of the PWM signal for different peak amplitudes of the extra control signal and (b) with peak amplitude of the extra control signal for different duty cycles of the PWM signal.99 12.13 320. 100 – 300.79 1.84 38. The settling times (ts) have been measured via . Vs (V) 0 2 4 6 8 10 12 14 16 Nmax (rpm) 1323. 900 – 1100 and 1100 – 1300 rpm.26 199.60 1207.32 19.96 Nmin (rpm) 0 0 0 0 0 0 0 0 0 tb (ms) 511 497 463 447 427 395 341 278 167 Table 2.03 761.40 949.83 574. 324 325 326 327 328 329 330 331 332 333 Table 1.00 112. keeping dc fixed.40 93. keeping Vs fixed.99 130.137 V.00 1098.47 387.25 -17. 8. dc (%) 90 80 70 60 50 40 30 20 10 Nmax (rpm) 1323.

Thus the transient speed control characteristics via the extra control parameter Vs are found to be better as compared to the direct control parameter dc. The peak amplitude of the subtracted extra control signal provides an additional control over the speed of DC motor along with the duty cycle of the ordinary PWM signal. Average settling time ( tˆs ) for each case has been calculated from five consecutive measurement data corresponding to that. 5. (a) during speed rise. 9. keeping Vs fixed or varying Vs. keeping dc fixed.UNDER PEER REVIEW 334 335 336 337 338 339 340 341 342 precise online stopwatch [11] for each of the above mentioned ranges during both speed rise and decay by either varying dc. 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 Fig. An electronic circuit for generating the modified control signal for 9 V DC motor drive has been designed and fabricated and the experiments are carried out to study the speed control characteristics of the DC motor under test. It is noteworthy from Figures 9 (a) and (b) that average settling times ( tˆs ) for each of the ranges under consideration during both speed rise and decay are found to be smaller when the Vs is varied keeping dc fixed as compared to when dc is varied keeping Vs fixed. An extra control signal having special form is subtracted from the conventional fixed amplitude CFVD PWM signal to obtain the modified speed control signal. CONCLUSION A new method for the speed control of DC motor drives via modified CFVD PWM technique has been proposed in this paper. better transient response and abrupt electrical breaking of the motor have been achieved by using the proposed speed control signal as compared to the conventional CFVD PWM speed control signal. (b) during speed decay. . Bar graphs showing the average settling times for different speed ranges when the duty cycle of the PWM signal is varied keeping the peak amplitude of the extra control signal fixed and when the peak amplitude of the extra control signal is varied keeping the duty cycle of the PWM signal fixed. More precise control over speed.

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