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始附件

William JH Hsieh

4251 Norwalk Dr Apt# AA-201

San Jose, Ca 95129

Tel: 408-2179609(h) 408-8864570(cell)

Email: whsieh99@gmail.com

<Objective>

Seeking a challenge position fully utilizing my background in semiconductor industry

<Experience Highlights>

Deputy Division Director, QA Division

UMC, Taiwan, May 2006—May 2009

As a deputy director, several area are extensively covered for major responsibility, ranging from
quality assurance of IP design , modeling, process baseline monitor in order to preserve customer
satisfaction and pave the way to long-term business success.

Customer Quality Satisfaction (CQS) & Fab QA operation

 Periodically coordinate cross-dept with customers to review the quality issues. Take actions,
solve problems and feedback to customers timely.
 Monitor the procedures of any excursion and close up with 8D report.
 Handle customer special request (CCR), voice of complaints(VOC)
 Chair various committees for in-line process monitor and quality enhancement

IPDSQA( IP Design & Support Quality Assurance)

Supervising 9 engineers and fully responsible for IP quality, management, and ultimately to assure
the completeness, accuracy, competitiveness and friendliness of IP delivery. Main responsibilities
are:

 Management & validation of IP developments with vendors


 Management & validation of IP development with internal design teams
 Institute SOPM (source & Origin Proactive Management) methodology to provide a robust
IP offerings.
 Developed MDCS (Macro Development Control System) to control IP tracking
 Vendor audit
 Customer’s VOC (Voice of Complaints) handlings.

DSMQA( Design Support Manual Quality Assurance)


Supervising 25 engineers and fully responsible for DSM developments to cope with new technology
migrations. Starting from TLR( Topology Rule), EDR( Electrical Design Rule), Mask Tooling
Rule, Intercap Rule to Spice model, all are developed and managed and distributed to customers.
Main tasks are:

 Schedule and allocate resources of the upcoming DSM from R&D


 Work with BU( Business Unit) to accommodate the customized DSM requirements
 Work with IT( Information Technology) to build a friendly interface for delivery flow.
 Work with BU for VOC handling
 Visit customers and attend QBR (Quality Board Review) to timely respond and take actions
to improve the DSM quality

Senior Design Engineering Manager, Emosyn Inc (Moved to India)

San Jose, CA 2003·2006

Emosyn is a company with leading technology to design and fabrics SOC based on flash memory
system for high secure, high density smart card system application by using TSMC 0.35u
technology. My main accountability was in charge of digital design group.

 Joined marketing for production definition


 Micro-architect the modules and wrote design specification
 Evaluated tools and brought up the design methodology
 Set up the verification strategy for analog/digital mixed together
 Cross-functional dept interfaces and coordinated for chip testing and debugging

Principal Engineer, Coppercom Inc

San Jose, CA 2001·2002

Joined the leading company in Voice Over DSL industry to develop the complicated telephony
gateway system to route the data and voice simultaneously through ATM and CLASS 5 switch.
Supervised 5 design engineers to develop two FPGAs in system line card, including design, system
verification and debug. The projects were finished on time on two different generation gateway
system.

Sr Engineer/ Manager, Softcom Microsystem Inc (Acquired by Intel)

San Jose, CA 1996·2000

Joined the company as a founding member to develop the high speed network processor to process
high speed frames, ATM cells and packets at 622Mbps data rate, full duplex 66 MHz PCI and local
bus to achieve OC-12 line rate . The total gate count was about 800k plus memory with the
deployment of the then·most advanced 0.35u technology. Lead 10 engineers starting from coding
functional mode, gate-level design, post-layout simulation, back-end tape-out and final chip debug.
Finally caught Intel’s attention to acquire..

Staff Design Engineer, Telecommunication Dept, LSI logic

San Jose, CA 1994·1996


Developed and designed the next generation ATMizer. Starting from micro architecture definition
to backend activities. Main responsibilities were:

 Defined algorithm for receive/transmit data paths


 Logic design and verification with CMDE tool
 Coordinated backend with layout design
 Silicon verification with system engineer on ATM test platfor

Sr Circuit/Logic Engineer, CPU Dept, Chips & Technologies

San Jose, CA 1989·1993

Joined Super 386/486 design team and was a member of MMU/BIU design group. Mainly involved
the logic design for TLB, LRU replacement and BIU interface by using LSI’s CMDE design tool.
The details of the tasks included functional simulation, debugging, critical paths analysis and A.C
timing verification. Also responsible for the circuit design of customized critical blocks of MMU
and TLB data paths, critical path timing analysis and heavily involved in silicon debugging.

Process Development/Circuit Design Engineer, AMD

San Jose, CA 1984·1988

Joined the SRAM design team to design 64k SRAM and CMOS high speed, high density (12k)
Content Addressable memory (CAM), including HSPICE circuit simulation, control logic design
and chip debugging using probe station.

Joined the bipolar memory technology development to develop first SLOT isolation process for
high density SRAM, PROM memory, including module development and device integration.

Education:

M.S.E.E The University of Arizona, Tucson, AZ

B.S. Physics National Central University, Taiwan. R.O.C

References:

Furnished upon request