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Computer is a fast electronic calculating machine that accepts digitized input information, processes it according to a list of internally stored instructions, and produces the resulting output information. Depending on size,cost,computational power, and intended use.computers are classified into Personal computer: • The most common computer is the personal computer , which has found wide use in homes, schools, and business offices.
Desktop computers: • • They have processing and storage units, visual display and audio output units, and a keyboard that can all be located easily on a home or office desk. The storage media include hard disks , CD-ROMs, and diskettes.
Note book computers: • Portable notebook computers are a compact version of the personal computer with all of these the dimensions of desktop computers , have significantly more computational power than personal computers. Workstations are often used in engineering applications , especially for interactive design work.
Enterprise systems or Mainframes:
Beyond workstations, a range of large and very powerful computer systems exist are called enterprise systems and servers at the low end of the range, and supercomputers at the high end. They are used for business data processing in medium to large corporations that require much more computing power and storage capacity than workstations can provide.
• • • • •
Serves contain sizable database storage units and are capable of handling large volumes of requests to access the data. In many cases, servers are widely accessible to the education, business, and personal user communities. The requests and responses are usually transported over internet communication facilities. The internet and its associated servers have become a dominant world wide source of all types of information. The internet communication facilities consist of a complex structure of high-speed fiber-optic backbone links inter-connected with broadcast and telephone connections to schools,businesses, and homes.
Supercomputers: • • They are used for the large-scale numerical calculations required in applications such as weather forecastin g and aircraft design and simulation. In enterprise systems, servers , and supercomputers , the functional units , including multiple processors , may consist of a number of separate and often large units.
B).Explain the basic operational concept of a digital computer
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MR D Cn l o tro R0 R1 P c sso ro e r
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Instruction register (IR)-holds the instr currently being used Program counter (PC)-keeps track of the execn of pgm, contains the mem address of the next inst to be fetched and executed. General-purpose register (R0 – Rn-1) Memory address register (MAR)-holds the address of the location to be accessed Memory data register (MDR)-contains the data to be written into or read out of the addressed location Programs reside in the memory through input devices PC is set to point to the first instruction The contents of PC are transferred to MAR A Read signal is sent to the memory The first instruction is read out and loaded into MDR The contents of MDR are transferred to IR Decode and execute the instruction Get operands for ALU General-purpose register Memory (address to MAR – Read – MDR to ALU) Perform operation in ALU Store the result back To general-purpose register To memory (address to MAR, result to MDR – Write) During the execution, PC is incremented to the next instruction
C).Explain the single bus structure?
Figure 1.3. Singlebus structure.
All the functional parts of a computer system must be interconnected in some organized way to obtain an efficient working system. To obtain higher speeds , parallel transfer of data is essential For this purpose , all the functional units are connected using a group of ines called bus. A “bus” is nothing but a group of wires,which carry information from source to destination, in the form of electrical signal.The simplest scheme is to use single common bus as shown in figure. The system has usually has three parts: Data bus :
The data bus is used to carry data (operand) from input device or memory to the processor.
It is also used to transfer data (result of an operation) from processor to memory or output device.Hence it is a bidirectional bus. Address bus: The processor uses this bus to access the memory or any I/O device connected to it. The processor sends “address” of the device for read or write operation.Hence , address is unidirectional. Control bus:
For synchronizing various activities like read,write,reset, etc.,the processor signals to inform the devices about any activity. Hence control lines are needed. Hence control bus is also bidirectional. The control bus thus is a set of individual signals carrying information at different instants of time.
Q2.A)Explain the different types of addressing modes with an example for each There are generally 8 types of addressing modes ---a) Immediate Addressing modes b) Direct Addressing modes c) Indirect Addressing modes d) Register Addressing modes e) Register Indirect Addressing modes f) Relative Addressing modes g) Indexed Addressing modes h) Base-Indexed Addressing modes Immediate Addressing Modes: In this addressing mode the operand is specified in the instruction itself. It has the operand field rather than an address field. The operand is given explicitly in the program. Example: MOV 5, R0 [ R0 5 ] Direct Addressing Modes: - In this mode, the “Effective Address (EA)” is equal to the address part of the instruction. The operands reside in memory (main) and its address is given directly by the address field of the instruction. Example: MOV A, R0 [R0 A]
Indirect Addressing Mode: -In this mode, the address field of the instruction gives the address where the effective address is stored in memory. The effective of the operand is the contents of a register or memory location whose address appears in the instruction. Example: MOV A, R0 MOV [ R0, R1 R0 A ] [ R1 [R0] ]
Register Addressing Mode: It is conceptually same as direct addressing but specifies a register instead of a memory location. In this mode the operands are in registers that reside within the CPU. The particular register is selected from a register field in the instruction. A K-bit field can specify any one 2k register. Example: MOV A, R0 [R0 A]
Register indirect Addressing Mode-In this mode the instruction specifies a register in the CPU whose contents give the address of the operand in the memory. A reference to the register is then equivalent to specifying a memory address. ExampleM OV [X], R0 RO [X] Relative Addressing ModesIn this mode the content of the PC is added to the address part of the instruction in order to obtain the effective address. The address part of the instruction is usually a signed number (2’s complement) which can be either positive or negative. When the number is added to the element of the PC, the result produces an effective address whose position in the memory is real time to the address of the next instruction. EA= [ PC ] + ADR ExampleMOV $ADR [ AC [PC] + [ADR] ]
Indexed Addressing mode:In this mode, the content of an IR is added to the address part of the instruction to obtain the effective address. EA= [IR] + ADR
8) Base-Index register Addressing Mode:In this mode the content of a base register is added to the address part of the instruction to obtain the effective register. This similar to the indexed addressing mode except that the register is now called a base register instead of an index register. EA= [BR] + ADR ExampleX (Ri, Rj) EA [Ri] + [Rj]
4(a) What are the two different I/O techniques in which CPU is directly involved in data transfer? Ans: The two different I/O techniques are: 1. Parallel port: Transfers data in the form of a number of bits, typically 8 or 16, simultaneously to or from the device.
2. Serial port: Transmits and receives data one bit at a time. Parallel port: INPUT INTERFACE The figure below shows the design of the parallel port
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Key or t poes r o nci n b ad o r cs o c n et o .
A typical keyboard consists of mechanical switches that are normally open.
When a key is pressed, its switches close and establish a path for an electrical signal.
This signal is detected by an encoder circuit that generates the ASCII code for the corresponding character. A difficulty with such push-button switches is that the contacts bounce when a key is pressed. The effect of bouncing must be eliminated. For this, a simple debouncing is implemented. The output of the encoder consists of the bits that represent the encoded character and one control signal called valid, which indicates that a key is being pressed. This information is sent to the interface circuit, which contains a data register, DATAIN, and a status flag, SIN. When a key is pressed, the valid signal changes from 0 to 1, causing the ASCII code to be loaded into DATAIN and SIN to be set to 1. The status flag SIN is cleared to 0 when the processor reads the contents of DATAIN register The interface circuit is connected to an asynchronous bus on which transfers are controlled using the handshake signals Master-ready and Slave-ready. The third control line, R/W distinguishes read and write transfers.
DA I TAN D 7 Q7 D7 Key o r b ad d ta a D 0 Q0 D0
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The output lines of the DATAIN registers are connected to the data lines of the bus by means of three-state drivers, which are turned on when the processor issues a read instruction with the address that selects this register The SIN signal is generated by a status flag circuit. This signal is also sent to the bus through a three-state driver. It is connected to bit D0, which means it will appear as bit 0 of the status register. Other bits of this register do not contain valid information. An address decoder is used to select the input interface when the high –order 31 bits of an address corresponds to any of the addresses assigned to this interface. Address bit A0 determines whether the status or the data registers is o be read when the master-ready signal is active. The control handshake is accomplished by activating the slave-ready signal when either read-status or read-data is equal to 1.
The printer operates under control of the handshake signals offers valid and idle in a manner similar to the handshake used on the bus with the master-ready and slave-ready signals. When it is ready to accept a character, the printer asserts its idle signal. The interface circuit can then place a new character on the data lines and activate the valid signal.
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The figure below shows an implementation of this interface. Its operation is similar to the input interface, the only significant difference is the handshake control circuit.
Serial port: A serial port is used to connect the processor to I/O devices that require transmission of data one bit at a time. The key feature of an interface circuit for a serial port is that it is capable of communicating in a bit serial fashion on the device side and in a bit parallel fashion on bus side.
Input shift re gister
D7 D0 DAT AOUT
M yaddress RS1 RS0 R /W Ready Accept Status and control Chip and register select
Output shift re gister
Recei ving clock Transm ission clock
A serial interf
The part of the interface that deals with the bus is the same as in the parallel interface described earlier. The status flags SIN and SOUT serve similar functions. The SIN flag is set to 1 when new data is loaded in DATAIN; it is cleared to 0 when the processor reads the contents of DATAIN. As soon as the data are transferred from the input shift register into the DATAIN register, the shift register can start accepting the next 8 bit character from the I/O device. The SOUT flag indicates whether the output buffer is available. It is cleared to 0 when the processor writes new data into the DATAOUT register and set to 1 when data are transferred from DATAOUT into the output shift register.
(b) With the block diagram of a DMA controller, Explain how data is transferred between disk and memory.
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D A M controlle r
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A program writes the address and word count information into the registers of the corresponding channel of the disk controller. It also provides the disk controller with information to identify the data for future retrieval. When the DMA transfer is completed, this fact is recorded in the status and control register of the DMA channel by setting the done bit. At the same, if the IE bit is set, the controller sends an interrupt request to the processor and sets the IRQ bit. Among the different DMA devices, top priority is given to high-speed peripherals such as a disk, a high speed network interface, or a graphics display device.
Since the processor originates most memory access cycles, the DMA controller can be
said to “steal” memory cycles from the processor. Hence this interweaving technique is called “cycle stealing”.
The DMA controller may be given exclusive access to the main memory to transfer a
block of data without interruption. This is known as block or burst mode.
5.a) Show the organization of bits cells in a 16*8 memory chip and explain how read and write operation are carried out ? Memory cells are usually organized in the form of an array. Each cell is capable of storing one bit of information. Each row of cells constitutes a memory word All cells of a row are connected to a common line referred to as the word line, which is driven by the address decoder on the chip. The cells in each column are connected to a Sense/Write circuit by two bit lines. The Sense/Write circuits are connected to the data input /output lines of the chip. During Read operation, these circuits sense (read) the information stored in the cells selected by a word line and transmit this information to the output data lines
During Write operation, the Sense/Write circuits receive input information and store it in
the cells of the selected word.
This very small memory chip consisting of 16 words of 8 bits each. (16 x 8 organization) The data input and the data output of each Sense/Write circuit are connected to a single
bidirectional data line that can be connected to the data bus of a computer.
Two control lines, R/W and CS (Chip Select) are provided. The R/W input specifies the required operation, and the CS input selects a given chip in a
multichip memory system. It stores 128 bits and requires 14 external connections for address, data and control lines. And also 2 lines for power supply and ground connections. b) Explain memory hierarchy in digital computer? The different types of memory units are employed effectively in a computer. The entire hierarchy of computer memory is shown below diagram. The hierarchy is explained as following. Processor Registers: The fastest access is to data held in processor registers. The processor registers are at the top in terms of the speed of access.
Processor Cache Memory: The next level of hierarchy is relatively small amount of memory that can be implemented directly on the processor chip. This memory called a processor cache, holds copies of instructions and data stored in a much larger memory that is provided externally. The cache memories divided in two levels. A primary cache is always located on the processor chip. This cache is small because it competes for space on the processor chip, which must implement many other functions. The primary cache is referred to as level 1 (L1) cache. A larger, secondary cache is placed between the primary cache and rest of the memory. It is referred to as level2 (L2) cache. It is implemented using SRAM chips. Including a primary cache on the processor chip and using a larger, off –chip, secondary cache is currently the most common way of designing computers. Main memory: The next level in the hierarchy is called main memory. This rather large memory is implemented using the dynamic memory components, typically in the form of SIMMs, DIMM, or RIMMs. The main memory is much larger but significantly slower than the cache memory. In a typical computer, the access time for the main memory is about ten times longer than the access time for the L1 cache. Secondary memory (magnetic Disk): Disk devices provide a huge amount of inexpensive storage. They are very slow compared to the semiconductor devices used to implement the main memory. During program execution, the speed of memory access is of utmost importance.
Increasing in cost per bit Increase in the size
Registers processor Primary cache L1
increase in speed
Secondary cache L2 Main Memory
6 A) Explain the working of a 4-bitMagnetic adder carry ahead
disk secondary memory
working of 4 bit –carry look ahead adder
In this 4 bit carry ahead we use 2 function 1) generate function 2) propagate function They are obtained by sum(si) and carry out (ci+1) Si=xi+yi+ci And Ci+1 =xiyi +xici+yici Factring 2nd equation into Ci+1=xiyi+(xi+yi)ci We can write ci+1=Gi+Pici Where Gi =xiyi generating function Pi=xi+yi propagating function * if the generating function is for stage I is equal to 1. Then ci+1=1 indepande of the input carry ci 4 bit carry ahead adder contain 4 carry C1=G0+P0c0 C2=G1+P1G0+P1P0c0 C3=G2+P2G1+P2P1G0+P2P1P0c0 C4=G3+P3G2+P3P2G1+P3P2P1G0+P3P2P1P0c0. The carries are implemented in the block labeled carry look ahead logic adder implemented in this form is called carry look ahead adder
4bit adder s1512 G3 I P3 I
4bit adder s118 G2 I P 2I
4bit adder s74 G 1I P 1I
4bit adder s30 G 0I P0 I
P 0 II
Figure 6.5. 16bit carrylookahead adder built from 4bit adders (see Figure 6.4 B) multiply 13*(-6) using booths algorithm Ans: Given Multiply 13*(-6)
First we convert the decimal number in to binary system 13 6 1101 0110
The multiplier is –ve we take the 2’s compliment of multiplier i.e 1010 then we use the technique of bit pair bit I 0 0 1 1 bit i-1 0 1 0 1 0 +1 -1 0
Then 1 0 1 0 becomes
-1+1-1 0 Booths algorithm is 01101 -1+1-1 0 0000000 00 111100 11* 0001101** 110011*** 1110110010 Now taking the 2’s compliment of the answer i.e 0 1 0 0 1 1 1 0 the required answer
c) Divide 1110 by 0011 using restoring technique. Ans: For restoring division technique use 3 step they are
1)shift accumulator A and dividend Q left one binary position 2)subtract divisor M from A and place the answer back in A. 3)if sign bit of A is 1 set q0 to 0 and add M back to A (that is restoring ) other wise set q0 to 1. Given divide 1110 by 0011. A M Shift Sub Setq0 Resto 00000 00011 00001 11101 11110 11 00001 Shift Sub 00011 11101 2nd cycle 110 0 100 1st cycle 110 1110
Setq0 0 0 0 0 0
set q0 1 1 1 1 0 Resto 11 00001 Shift Sub Setq0 Resto 00010 11101 11111 11 00010 0 1 0 0 4th cycle 0 00 1 010 3rd cycle
7(a) Explain with block diagram single bus organization of the data path inside a processor.
A group of lines that serves as connecting path for different devices is called a bus.
In addition to the lines that carry the data, the bus must have lines for address and control purposes. The figure below shows the simplest way to interconnect functional units is to use a single bus. The bus can be used for only one transfer at a time, only two units can actively use the bus at any given time. Bus control lines are used to arbitrate multiple requests for use of the bus. The main virtue of the single bus structure is its low cost and its flexibility for attaching peripheral devices.
Input O tput u M ory em P essor roc
F u 1 . S g b s stru tu . ig re .3 in le u c re
The devices connected to a bus vary widely in their speed of operation. Some electrochemical devices, such as keyboards and printers are relatively slow. Memory and processor units operate at electronic speeds, making them the fastest parts of a computer. Because all these devices must communicate with each other over a bus, an efficient transfer mechanism that is not constrained by the slow devices and that can be used to smooth out the difference in timing among processors, memories, and external devices is necessary.
Buffer registers are included with the devices to hold the information during transfers.
Buffer registers smooth out timing differences among processors, memories and I/O device during a sequence of data transfers. This allows the processor to switch rapidly from one device to another, interweaving its processing activity with data transfers involving several I/O devices.
B) Write the control sequence for execution of the instruction ADD(R7)R8 Ans: The control sequence for the execution of the instruction ADD(R7)R8 are Step1: Input data R7R8 gets through the input unit Step2: The execution start when pc(process control) is set to point to first instruction of the program Step3: R7R8 transfer to MAR(memory address register ) and reads R7 R8 Step4: The data R7 R8 loaded to into MDR(memory data register ) Step5: the data fetched from MDR and transferred to IR(instruction register) Step6: R7 R8 are decoded ,the data transferred to ALU through MDR Step7: the addition operation is performed . Step8: the value of R7 R8 are added and stored in R8. Step9: the processed data transferred to MDR . Step10: MDR send the result to memory.
Q8.write a short note on a) ASSEMBLER:
Programs written in an assembly language can be automatically translated into a sequence of machine instructions by a program called an Assembler. (Collection of utility programs – part of the system software) Assembler – like any other program, is stored as a sequence of machine instructions in the memory of the computer. Source program – user program (alpha numeric characters) Object program – when the assembler program is executed, it reads the user program, analyzes it, and then generates the desired machine language program (0s and 1s). Allow programmer to specify other information needed to translate the source program into object program – assembler directives/commands. For eg., SUM is used to represent the value 200. This fact is conveyed to the assembler program through a statement such as SUM EQU 200 - informs the assembler the name SUM should be replaced by the value 200 wherever it appears in the program. Label Operation Operand(s) Comment
Assembler’s task (source → object)
Replace all symbols denoting operations and addressing modes with the binary codes used in machine instructions Replace all names and labels with their actual values Assign addresses to instructions and data blocks (ORIGIN, DATAWORD, RESERVE) Determine the values that replace the names (EQU, label) Branch address (Relative addressing, branch offset- which is the distance to the target) Scan through the source program, keep track of all names and the numerical values that correspond them in a symbol table. – when a name appears second time, it is replaced with its value from the table.
What if a name appears as an operand before it is given a value (forward branch)? - scans source program twice (solution) Two-pass assembler – during first pass, assembler will create a complete symbol table. At the end of this pass, all names will have been assigned numerical values. Second time, subs. Values for all names. b) CACHE MEMORY Main memory is slow compare to the speed of processor a special type of memory called cache memory is designed which reduces the time needed to access the necessary information. There are two types of caches 1) A primary cache is always located on the processor chip referred to as level 1(L1) cache. 2) A larger secondary cache called level 2(L2) cache,is placed between the processor the processor and main memory. The effectiveness of the mechanism is based on a property of computer program called locality of reference.It is manifested in to two types: Temporal and Spatial. Temporal means that a recently executed instructions is likely to be executed again. Spatial means that the instruction in close proximity to a recently used instruction are likely executed soon. The operation of cache memory makes use of the property of locality of reerence .the term block is used to refer to a set of data at contiguous address locations A simple arrangement for L2 caahe memory is shown when a read request is received from the processor the contents of a block of memory words are transferred in to cache from main memory,later when the program references any of the locations in this block,contents can be read directly from the cache instead of referring to main memory.
Connection of cache memory to processor The correspondence between main memory blocks and cache blocks is specified by a mapping function.when a memory word that is not present in cache is referenced the block containing the block containing the required operands has to be brought in to cache from main memory if the cache is full ,then the cache control hardware must decide which block should be removed to create space for the new block. The decision depends on many factors and the set of rules govering this constitutes the replacement algorithm.