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BITS DE CONFIGURACION

Son una colección de datos binarios ubicados en la memoria de programa flash de una PIC®
MCU.
Los Bits de configuración están programados en el PIC® MCU con el código de la aplicación.
Bits de configuración no son código ejecutable como sus direcciones no son accesibles por el
contador de programa.
Cuando se programa en una PIC® MCU configuración de bits circuito completo que activa o
desactiva las características de hardware de la MCU.
Bits de configuración están "leer" al salir de un reinicio y no se pueden modificar en tiempo de
ejecución.
Las características especiales de funcionamiento MCU controladas por los bits de configuración
incluyen:



System Clocking
Gestión de energía
Seguridad del dispositivo
Características de funcionamiento

Bits de configuración se generan a partir de las directivas de compilador/ensamblador
incluidos en los archivos de código fuente.
LOCALIZACION Y FORMATO
Los bits de configuración para la familia de los MCU PIC24/dsPIC33 se combinan en dos
palabras de 24 bits llamados CONFIG1 y CONFIG2. Las palabras de configuración se encuentran
más allá del alcance del contador de programa en la mitad superior del espacio de memoria de
programa del MCU (Configuration Memory Space) a partir de 0xF80000 como se muestra:

Los Bits de configuración se generan por las directivas del compilador insertadas en el código
fuente de la aplicación. Cuando se construye un proyecto PIC® MCU, los valores de los bits de
configuración están incrustadas en el archivo de salida HEX. Los bits de configuración están
programados en el PIC® junto con el programa de aplicación.
Los siguientes registros CONFIG1 & CONFIG2 son registros definidos
PIC24FJ128GA010:

para el MCU

1. The crystal is connected to the OSC1 and OSC2 pins.3 “PLL Configuration”. Primary The primary oscillator can use one of the following as its clock source:    XT (Crystal): Crystals and ceramic resonators in the range of 3 MHz to 10 MHz.37 MHz. EC (External Clock): The external clock signal is directly applied to the OSC1 pin. HS (High-Speed Crystal): Crystals in the range of 10 MHz to 40 MHz. It is also used as a reference clock by the Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). Low-Power RC The LPRC (Low-Power RC) internal oscIllator runs at a nominal frequency of 32. User software can optionally specify a factor (ranging from 1:2 to 1:256) by which the FRC clock frequency is divided.768 kHz. PLL configuration is described in Section 8. The crystal is connected to the OSC1 and OSC2 pins. . HS or EC) Oscillator Primary Oscillator with PLL Secondary (LP) Oscillator Low-Power RC (LPRC) Oscillator FRC Oscillator with postscaler Fast RC The Fast RC (FRC) internal oscillator runs at a nominal frequency of 7.CPU Clocking System The dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices provide seven system clock options:        Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT. This factor is selected using the FRCDIV<2:0> bits (CLKDIV<10:8>). FRC The clock signals generated by the FRC and primary oscillators can be optionally applied to an on-chip Phase Locked Loop (PLL) to provide a wide range of output frequencies for device operation. User software can tune the FRC frequency. The FRC frequency depends on the FRC accuracy (see Table 24-18) and the value of the FRC Oscillator Tuning register (see Register 8-4).

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The PLL Feedback Divisor. which is within the 100-200 MHz ranged needed..2 SYSTEM CLOCK SELECTION The oscillator source used at a device Power-on Reset event is selected using Configuration bit settings. The FRC primary oscillator is the default (unprogrammed) selection. The VCO output is further divided by a postscale factor „N2.5 MHz to 80 MHz. .25-40 MIPS. The oscillator Configuration bit settings are located in the Configuration registers in the program memory. by which the input to the VCO is multiplied. The output of the primary oscillator or FRC. select the oscillator source that is used at a Power-on Reset. 3. (Refer to Section 21. If PLLDIV<8:0> = 0x1E.. FCY.8 MHz to 8 MHz. or 33 before being provided to the PLL‟s Voltage Controlled Oscillator (VCO). POSCMD<1:0> (FOSC<1:0>).8-8 MHz.) The Initial Oscillator Selection Configuration bits. This factor must be selected such that the resulting VCO output frequency is in the range of 100 MHz to 200 MHz. and the Primary Oscillator Mode Select Configuration bits. then M = 32.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. which generates device operating speeds of 6. The output of the oscillator (or the output of the PLL if a PLL mode has been selected) FOSC is divided by 2 to generate the device instruction clock (FCY) and the peripheral clock time base (FP). suppose a 10 MHz crystal is being used with the selected oscillator mode of XT with PLL.1. the PLL output „FOSC‟ is given by: For example.1. For a primary oscillator or FRC oscillator.‟ This factor is selected using the PLLPOST<1:0> bits (CLKDIV<7:6>)..1 “Configuration Bits” for further details.   If PLLPRE<4:0> = 0. Instruction execution speed or device operating frequency. This yields a VCO input of 10/2 = 5 MHz. A block diagram of the PLL is shown in Figure 8-2. shown in Table 8-1. This yields a VCO output of 5 x 32 = 160 MHz. The input to the VCO must be selected in the range of 0. is divided down by a prescale factor (N1) of 2. provides a factor „M‟. FCY defines the operating speed of the device.8. selected using the PLLDIV<8:0> bits (PLLFBD<8:0>). is given by: 8. and must be selected such that the PLL output frequency (FOSC) is in the range of 12. and speeds up to 40MHz are supported by the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 architecture. FNOSC<2:0> (FOSCSEL<2:0>). output „FIN‟. The prescale factor „N1‟ is selected using the PLLPRE<4:0> bits (CLKDIV<4:0>). The PLL provides significant flexibility in selecting the device operating speed. then N1 = 2. 4 or 8. „N2‟ can be either 2. The Configuration bits allow users to choose among 12 different clock modes. which is within the acceptable range of 0. denoted as „FIN‟.

 If PLLPOST<1:0> = 0. then N2 = 2. This provides a Fosc of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. .

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices have a safeguard lock built into the switch process.1 “Configuration Bits” for further details.1 ENABLING CLOCK SWITCHING To enable clock switching. FRC and LPRC) under software control at any time.Programando en el DSPIC Configuracion del oscilador interno con DSPIC Utilizando la ecuacion: ( ) ( ( Este ) ) se declara en la programación: 8.2. the clock switching function and Fail-Safe Clock Monitor function are disabled.) If the FCKSM1 Configuration bit is unprogrammed („1‟). LP. 8. .2 Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary. (Refer to Section 21. To limit the possible side effects of this flexibility. the FCKSM1 Configuration bit in the Configuration register must be programmed to „0‟.

The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. . the clock switch is a redundant operation. However. In this case. Then the application program can either attempt to restart the oscillator or execute a controlled shutdown. Write the appropriate value to the NOSC control bits (OSCCON<10:8>) for the new oscillator source. If they are the same. the hardware waits until a PLL lock is detected (LOCK = 1). The NOSC control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits.This is the default setting. The FSCM function is enabled by programming. 5. the COSC bits (OSCCON<14:12>) reflect the clock source selected by the FNOSC Configuration bits. read the COSC bits (OSCCON<14:12>) to determine the current oscillator source. Once the basic sequence is completed. the NOSC bit values are transferred to the COSC status bits. Perform the unlock sequence to allow a write to the OSCCON register low byte. It is held at „0‟ at all times. In the event of an oscillator failure. If the FSCM function is enabled. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. 8. The old clock source is turned off at this time.3 Fail-Safe Clock Monitor (FSCM) The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure.2 OSCILLATOR SWITCHING SEQUENCE Performing a clock switch requires this basic sequence: 1. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition. If the new source is using the PLL. the FSCM generates a clock failure trap event and switches the system clock over to the FRC oscillator. If a crystal oscillator must be turned on. 3. 8. 2. 4. 5. the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer. If desired. If a valid clock switch has been initiated. Set the OSWEN bit (OSCCON<0>) to initiate the oscillator switch. the system clock hardware responds automatically as follows: 1. with the exception of LPRC (if WDT or FSCM are enabled) or LP (if LPOSCEN remains set). 4. 2. The trap can be treated as a warm Reset by simply loading the Reset address into the oscillator fail t rap vector. The new oscillator is turned on by the hardware if it is not currently running. the hardware waits until the Oscillator Start-up Timer (OST) expires. the LOCK (OSCCON<5>) and the CF (OSCCON<3>) status bits are cleared. 6.2. the OSWEN bit is cleared automatically and the clock switch is aborted.

3 Configuration Bit Pin Select Lock As an additional level of safety. they must be unlocked in hardware. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. some restrictions on peripheral remapping are needed to prevent accidental configuration changes. then locked with a second lock sequence. a specific command sequence must be executed: 1. 10. clearing IOLOCK allows writes. a configuration mismatch Reset will be triggered.2 Continuous State Monitoring In addition to being protected from direct writes. the internal FRC is also multiplied by the same factor on clock failure.3 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time.1 Control Register Lock Under normal operation.6. The register lock is controlled by the IOLOCK bit (OSCCON<6>). the device switches to FRC with PLL on a clock failure. IOLOCK remains in one state until changed. Setting IOLOCK prevents writes to the control registers. and the peripheral pin select control registers cannot be written to.6. In the default (unprogrammed) state. writes to the RPINRx and RPORx registers are not allowed. 10. Write 0x46 to OSCCON<7:0>. 3. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events). IOL1WAY is set. Attempted writes appear to execute normally. the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers.3. the register unlock procedure will not execute.3. 2. restricting users to one write session.3. 10. Clear (or set) IOLOCK as a single operation Unlike the similar sequence with the oscillator‟s LOCK bit.6. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers. . The IOL1WAY (FOSC<IOL1WAY>) configuration bit blocks the IOLOCK bit from being cleared after it has been set once.If the PLL multiplier is used to scale the system clock. To change these registers. but the contents of the registers remain unchanged. Essentially.6. To set or clear IOLOCK. the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. DsPIC33F devices include three features to prevent alterations to the peripheral map:    Control register lock sequence Continuous state monitoring Configuration bit pin select lock 10. If IOLOCK remains set. Write 0x57 to OSCCON<7:0>.

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Programando en el DsPIC33F: .

TRISx: Determina si un pin es Entrada o Salida. LAT y TRIS registro para el control de datos. asociado con cada puerto. PORT and LAT registers.REGISTROS DE CONTROL DE LOS PUETOS DE ENTRADA Y SALIDA (I/O PORT CONTROL REGISTERS) Todos los puertos de entrada y salida tienen los siguientes 4 registros directamente asociados con la operación del puerto. . La salida open-drain característica es compatible tanto pin del puerto y las configuraciones de periféricos. La función de I/O open-drain no es soportado en los pines que tienen funcionalidad multiplexado analógica en el pin. PORTx: I/O Port Register. Solo se usa en modo lectura ya que ocurren problemas con las instrucciones de read-modify write. Open-Drain Control Registers Además del PUERTO. cada pin del puerto también se puede configurar de forma individual. LATx: Registro asociado con los pines de I/O elimina el problema que ocurre con las instrucciones de read-modify-write. PORTx: Los datos en los pines I/O son accedidos a través de este registro. El máximo voltaje open-drain permitido es la misma que la especificación máxima VIH. Configuración de cualquiera de los bits configura el pin correspondiente para actuar como una salida-drenaje abierto. 5 V) en cualquier sólo digitales pines deseados mediante el uso de resistencias pull-up externos. ODCx. La función de open-drain permite la generación de salidas superior a VDD (por ejemplo. ya sea para la salida digital u open-drain. Esto es controlado por el registro de control Open-Drain. mientras una escritura al registro PORTX escribe un valor al el Puerto de data latch. Una lectura del registro PORTx lee los valores de los pines I/O. LATx: I/O Latch register ODCx: Open-Drain Control register Each I/O pin on the device has an associated bit in the TRIS. donde 'x' denota ola particularidad del puerto I/O     TRISx: Data Direction registers. Usado para escribir data en el Puerto.

programmers can better tailor the microcontroller to their entire application.5 Input Change Notification The input change notification function of the I/O ports allows the dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 devices to generate interrupt requests to the processor in response to a change-of state on selected input pins. 10. 10. once it has been established. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping. Peripheral pin select is performed in software. 10. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-13). This feature can detect input change-of-states even in Sleep mode.6. The association of a peripheral to a peripheral selectable pin is handled in two different ways.6. 10.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. Depending on the device pin count.2. Each register contains sets of 5-bit fields. By increasing the pinout options available on a particular device. rather than trimming the application to fit the device. Each CN pin also has a weak pull-up connected to it.2 CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of special function registers: one to map peripheral inputs. The pull-ups are enabled separately using the CNPU1 and CNPU2 registers. Four control registers are associated with the CN module. where “RP” designates a remappable peripheral and “n” is the remappable pin number. The CNEN1 and CNEN2 registers contain the interrupt enable control bits for each of the CN input pins. and eliminate the need for external resistors when push-button or keypad devices are connected. with each set associated with one of the remappable peripherals. Pins that support the peripheral pin select feature include the designation “RPn” in their full pin designation. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Figure 10-2 Illustrates remappable pin selection for U1RX input. For any given device. Because they are separately controlled. the valid range of values for any bit field corresponds to the maximum number of peripheral pin selections supported by the device.6 Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins.1 AVAILABLE PINS The peripheral pin select feature is used with a range of up to 26 pins. Programming a given peripheral‟s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral.6. Programmers can independently map the input and/or output of most digital peripherals to any one of these I/O pins. depending on whether an input or output is being mapped. The number of available pins depends on the particular device and its pin count. .10. and generally does not require the device to be reprogrammed. Setting any of these bits enables a CN interrupt for the corresponding pins. and one to map outputs. up to 31 external signals (CNx pin) can be selected (enabled) for generating an interrupt request on a change-of-state. A control register associated with a peripheral dictates the pin it will be mapped to. The pull-ups act as a current source connected to the pin. a particular peripheral‟s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. when the clocks are disabled. which contain the control bits for each of the CN pins. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins.

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and that peripheral‟s output is mapped to the pin (see Table 10-2 and Figure 10-3). with each set associated with one RPn pin (see Register 10-14 through Register 10-26). The RPORx registers are used to control output mapping.10.2 Output Mapping In contrast to inputs. Like the RPINRx registers. The value of the bit field corresponds to one of the peripherals. The list of peripherals for output mapping also includes a null value of 00000 because of the mapping technique. a control register associated with a particular pin dictates the peripheral output to be mapped. In this case.2. each register contains sets of 5-bit fields. This permits any given pin to remain unconnected from the output of any of the pin selectable peripherals.6. . the outputs of the peripheral pin select options are mapped on the basis of the pin.

Programando en el DsPIC33F: .

Escribiendo un programa básico en el IDE MPLABX con el DSPIC33FJ32MC204: .

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Ejemplo1: .

Podemos Simular el Programa utilizando las herramientas del IDE MPLABX .

Simulando en Proteus: .

Ejemplo2: .