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FILM TRANSISTOR (TFT) MODEL FOR CIRCUIT SIMULATION
by
Chester L i
Memorandum No. UCBERL M93/82
22 November 1993
ELECTRONICS RESEARCH LABORATORY
College of Engineering University of Californlb, Berkeley, CA 94720
A PHYSICAL POLYSILICON THfN
FILM TRANSISTOR (TFT) MODEL
FOR CIRCUIT SIMULATION
Chester Li
Memorandum No. UCBERL M93/82
22 November 1993
A PHYSICAL POLYSILICON THIN
FILM TRANSISTOR (TFT) MODEL
FOR CIRCUIT SIMULATION
by
Chester Li
Memorandum No. UCBERL M93/82 22 November 1993
ELECTRONICS RESEARCH LABORATORY
College of Engineering University of California, Berkeley 94720
Abstract
This report presents a polysilicon thin film transistors model for circuit simulations. The drain current model includes the effects of hot carrier, drain induced barrier lowering (DIBL), channel length modulation (CLM), and gate induced drain leakage (GIDL). The capacitance model is linked to the drain current and its derivatives. This model has been implemented in SPICE. Simulation and experimental results are compared.
Table of Contents
Chapter 1 : Introduction Chapter 2: Drain Current Model Chapter 3: Intrinsic Capacitance Model Chapter 4:Spice Implementation Chapter 5: Simulation Results Appendix A: Equations Lmplemented in SPICE Appendix B: Parameter Extraction Reference Acknowledgments Page 1 Page 2 Page 14 Page 28 Page 31 Page 34 Page 4 4 Page 50 Page 51
Chapter 1: Introduction
Polysilicon Thin Film Transistors (TFTs) are widely used in active matrix liquid crystal displays (LCDs) to drive the pixels and decode the image signals. A common substrate material for TFTs is polysilicon deposited on a glass substrate (fig 1.1). The typical operating bias in the small size LCD environment is about 12V. The characteristics of the TFTs are severely affected by imperfections at the polysilicon surface. Moreover, the TFTs operate with a floating substrate.
As a result, the characteristics of a T I T cannot be modeled accurately by the common bulk MOSFET model in SPICE.
dram
h
n
gate
source
substrate
onde
gate
source
p substrate
quartz
(a) bulk NMOSFET
@) NTFT
Fig 1.1: Cross sections of a bulk NMOSFET and a NTFT This report presents a polyTIT drain current model with an accompanying intrinsic capacitance model. The formulation of the drain current model is similar to BSIM3 [2]. The capacitance model is capacitance based and linked to the drain current. They have been implemented in SPICE. Ring oscillator simulation results will be compared to experimental data. The data used in this study are measured from a LCD wafer with p substrate and top gate structure. The gate oxide thickness is 76nm.The effective channel length ranges from 3.3pm to 5.3pm. Chapter 2 presents the drain current model. Chapter 3 discusses the intrinsic capacitance model. Chapter 4 describes the model implementation in SPICE. Finally, chapter 5 compares the simulation results and experimental data. Equations implemented in SPICE and parameters extraction procedures are summarized in the appendixes.
1
Chapter 2: Drain Current Model
2.1 Overview
This chapter discusses the TFT drain current model. The model is separated into subthreshold and strong inversion regions. The strong inversion region is further divided into the linear and saturation regions. This physical model describes the hot carrier. drain induced barrier lowering (DIBL), channel length modulation [ 11, thermal generation, and gate induced rain leakage (GIDL) [4] effects. A parabolic smoothing function [ 11 is used to ensure continuity of the first order derivative between different regions of operation. Four parameters, Vguanl, Vgumh, Vduanl, and Vdtranh are used to define the transition regions between different bias regions. The transition regions are defined around VT and Vdsat. VT is the threshold voltage. Vdsat is the saturation voltage. Figure 2. la illustrate the boundary values.
i
I
1
d 'l
'dsat
a '
V
'
Saturation
d 's
<
V
Linear
Transition
>
Region
Region
Region
Subthreshold Region
Transition Region
Suong Inversion Region
Figure 2. la: Boundary values for transition region Section 2.2 and 2.3 discuss the model in the strong inversion and subthreshold region. Section 2.4 describes the transition region between the strong inversion and subthreshold region. Section 2.5 compares the model with the measured data. Appendix A summaries the drain current equations implemented in SPICE. The parameters and their meanings are summarized in chapter 4.The following symbols are defined for model derivation (see figure 2.la). T is temperature.
vdh vgh
= vdsat = vT
+ vdtranh
vdl
vgl
= vdsat = vT
IVgtranh
 vdtranl  vgtranl
2
2.2 Strong Inversion Region Model
2.2.1 Linear Region (Vgs > Vgh, 0 < V, < VdI)
Following Huang's [2] approach, the drain current in the linear region is:
Polysilicon TFTs have many interface traps at the SiSi02 interface, especially at or near the grain boundaries. As a result, the electrons (or holes in pchannel TFT) have to hop over the barrier formed at the grain boundaries along the channel during electrical conduction (figure 2.2.la). In@), the logarithm of mobility, is inversely proportional to the barrier height (ob). Since modulated by the gate bias (V,,), mobility has the form of aexp(D/(V,,VT)). a,p, and VT are function of temperature. a and p are po(kT/q)P1 and qp2exp(p3T)/kTCox [ 11. This expression describes the mobility well when V,, is much bigger than VT. An additional p4, the
o b is
minimum mobility at low V,,, is added to the model. Therefore, the effective mobility is modeled as :
po, p1, p2, p3, and p4 are fitting parameters. VT is the threshold voltage, which is approximated as a linear function of temperature [4]. VT = VTO  bT
Figure 2.2.l b shows the temperature dependence of V,. VT decreases when temperature increases, which has the same trend as bulk MOSFET [4]. It indicates that the change in fermi level with temperature is the dominant mechanism. Figure 2.2. ICplots the mobility of a pchannel
(PTFT) and a nchannel (NTFT) polyTFT at V,=O. 1V at room temperature. When V,, increases, @ at the grain boundaries drops. Therefore, mobility increases as V,, increases. The ,
3
mobility of polyTFTs is lower than that for bulk MOSFET. Therefore the current drive is also smaller. Since the conduction is limited by excitation over the barrier, the mobility rises as temperature increases. Figure 2.2. Id plots the mobility of a NTFT at different temperatures.
Gram Boundary
Figure 2.2. la: Band diagram of a polyTFT channel and electron conduction of a nchannel device
I
I
I
I
60
80
100
Temperature (C)
Figure 2.2.lb: Threshold voltage dependence on temperature
4
80 
1120
x
W
<
0
h
60
80
40
cc
E z
0
Y
60 40
2
20
Lines: model
20
I
01 2
1
1
I
I
4
6
0
lo
14
10
12
Figure 2.2. IC: Mobility of a PTFT and an NTFT at room temperature
Tox=76nm
W/L=20/4.3
%
W 0
40
E 30
z
rr
0
3.
5 20
1(
"
increasing
T=300K T=333K
4
6
0
vgs
10
12
14
Figure 2.2. Id: Mobility of a NTFT at different temperatures. Lines are model and symbols are data
5
2.2.2 Saturation Region (Vss > V,,, Vds > Vdh)
Similar to BSIM3 [2] approach, the DIBL. hot carrier, and channel length modulation effect of drain current in the saturation region are modeled. The drain model is expressed as:
Id = Idsat
[
's d
 vdsat
vA
Esat = 2vsat ~ ~ e f f
Idsat is the drain current at V&=Vbat using the linear Id equation. VACLM models the channel length modulation effect. e is a fitting parameter. V L ,, models the DIBL effect. The hot carrier effect, which is caused by the high electric field at the drain, is modeled by fhc. 0 is the DIBL effect coefficient. s1 and s2 are fitting parameters for hot carrier effect.
2.2.3 Transition Region in Strong Inversion Region (Vps > V a , V d < V h < V,)
To improve the convergence property of the model, the first order derivative is made continuous by using a parabolic smoothing function from BSIM3 [2]. The basic concept is illustrated by figure 2.2.3a. 1 is the current in the linear region at vdl and the applied Vgs. Idh is , the current in the saturation region at Vdh and the applied Vgs. L1 is the tangent to the h e a r region at V&=Vdl. L2 is the tangent to the saturation region at v&=vdh. The intersect of L1 and L2 is (vdp, Idp). Once (vdh, I&), (V,,, Id&, and (vdl, I&) are determined, the points between
Vdh and vd1 can be computed using the parabolic smoothing function with first order derivative
continuity, The expression for vdp, Idp, Id, and the first order derivatives are shown below.
6
vdp =
Idh  Id1 (gdshVdh  &dslVdl) gdsl  gdsh
+
Idp = gdsl( vdp  vdl
Id1
gdsh = 
gdsl =
t can be expressed as a function of V, ,
vdp,
and v d h as:
2
t = (vdl vdp)+d(vdlvdp)
(vdlvds)(vdl
2Vdp+Vdh)
vdl  vdp + Vdh
Id
L2
d' d 'p
'dsat
va
> d's
Figure 2.2.3a: Scheme to connect the saturation and linear region
7
2.3 Subthreshold Region Model (Vss < VyVgtranl)
The diffusion current, thermal generation current, and GIDL current are modeled in the subthreshold region. Since the interface traps density is high in TIT, the subthreshold swing (380mV/decade) of the diffusion current is higher than that in the normal MOSFET (  100mV/decade). The subthreshold drain current is expressed as:
Id = Idiff
iIgidl i][thermal 
V,E is the offset voltage for Idff n is the subthreshold slope. I is a function of oxide thickness , and substrate doping [2]. It is treated as a fitting parameter in this model. Agidl, Bgidl, and Vi are fitting parameters for GIDL current. I@ is set to zero when (VdgVi) is less than zero. This equation is same as in [3], except that [3] fixes Vi to 1.2V, where Vi here is kept as a parameter because of the abundance of interface traps between the conduction band and valance band. Ea is the activation energy for the thermal current generation. Ithermalo a fitting parameter for is Ithermala 2.4 Transition Region between Strong Inversion and Subthreshold Region (V&V,cV&) To improve the convergence property of the model, the first order derivative is made continuous by using the same scheme as in section 2.2.3. A parabolic smoothing function in the linearlinear scale is used. The basic concept is illustrated by figure 2.4a.
8
L2
v vgP vT
vgh
> d's
Figure 2.4a: Scheme to connect the subthreshold and strong inversion region . , Id1 is the current in the subthreshold region at Vgl and the applied V I&, is the current in the . , strong inversion region at v g h and the applied V L1 is the tangent to the subthreshold region at vgs=vgl. L2 is the tangent to the strong inversion region at Vgs'Vgh. The intersect of L1 and L2 is (Vgp, Idp). Once (vgh, Id,), (Vgp, Id,), and (Vgl, Idl) are determined, the points between v g h and Vgl can be computed using the parabolic smoothing function with first order derivative continuity. The expression for Vgp, Idp, Id, and the first order derivatives are shown below.
vgs = ( 1 t
>
2
vgl
+ 2t( 1 t)vgp + t 2 v g h
Id =(1t) 2 Id1 +2t(lt)Idp + t 2 Idh
9
g m h =
ald
I
!
i
grnl=
ald
10
2.5 Verification
0.6n
Symbols: data Lines: model
4
W
E
0.4
U
I
2
4
6
8
10
12
14
Figure 2.5a: IdV, of a 20/5.3 NTFT with T0,=76nm
Figure 2.5b: IdVds of a 20/3.3 NTFT with T0,=76nm. The model curve is generated using the same set of parameters extracted from the 20/5.3 device. AL=l.7p.m (extracted by capacitance method)
11
0.6
0.4n
Symbols: data Lines: model
V
V& (V)
Figure 2 . 5 ~IdV, of a 20/4.42 PTFT with T0,=76nm :
1 .o
v
=14v
0.8
4
W
0.6
E
w 0.4 U
0.2
0.0
0
2
4
6
8
10
12
14
Figure 2.5d: ‘ds of a 20/2.42 PTFT with To,=76nm. The model curve is generateG using the same set o parameters extracted from the 20/4.42 device. AL=2.58pm (extracted by capacitance method)
12
W/L=20/5.3
vgs
W)
Figure 2.5e: IdVgs of a 20/5.3 NTFT with T,=76nm
WL=20/3.3
vgs
fl)
Figure 2.5f IdV,, of a 20/3.3 NTFT with Tox=76nm
13
Chapter 3: Intrinsic Capacitance Model
3.1 Overview
A capacitancebase model is developed to model C,, and Cgd. The model is separated into
strong inversion and subthreshold regions. The strong inversion region model is developed from charge equations and linked to the drain current model. The subthreshold region model is empirical. The subthreshold region, strong inversion linear region, and strong inversion saturation region are linked by a linear function to model the gradual change in capacitance when the TFT is switched from one bias region to another. Four parameters are used to define the transition region between different bias regions. They are: Vduanhc, Vduanlc,Vguanhc,and Vgtranlc.The transition regions are defined around VT and Vdsat. VT 1s the threshold voltage. Vdsat is the saturation voltage, which is [ l/(vgsvT)+ l/(EsatLefi)]l.The boundaries are illustrated in figure 3. la. Two additional parameter, Acgs and Acgd, are added to model C,, and Cgd in the GIDL dominant region.
I
<
V A
V A
Linear
Region
Transition Region
Saturation
>
> Subthreshold Transition Strong Inversion
Region Region Region
Region
Figure 3. l a : Definition of the boundaries values Section 3.2 and 3.3 describe the strong inversion and subthreshold model. Section 3.4verifies the model with measured data. The equations implemented in SPICE is summarized in appendix A. The parameters and their meanings are summarized in chapter 4. The following symbols are defined for the model derivation (see figure 3. la).
vdl
= vdsat  vdtranlc
vdh = vdsat k vdtranhc
Vgi = VT  Vguanlc
vgh
= vT
+ vguanhc
14
gds
=av,,
ald
3.2 Strong Inversion Region Model
3.2.1 Cgd in the Linear Region (0 < V, < Vdl, V, > V g J
vs=ov
I
" e 7
ys
inversion layer
'
Y d
Figure 3.2. la: Cross section of a NTFT in linear region Figure 3.2. la shows the cross section of a NTFT In the linear region (V&<Vdsat and Vgs>VT).The inversion charge density gradually drops from Cox(VgsV~Vs) the source (y,) at to c,,(vgSVTvd) at the drain (Yd). The charge at the gate is :
Yd
Qg = Weff
YS
Qn
(YW Q b u k +
()bulk
is the depletion charge in the substrate. Qn(y), the inversion charge, is:
Qn (Y)= Cox Vgs  VT  V(Y
[
I]
Qg can also be rewritten as :
Huang [2] shows that :
15
Therefore, Qg is :
c g d is defined as  Since Qbulk is not aQg . avd
a strong function of v,, Cgd is
Esat
 2vsat Peg
V, > V a )
3.2.2 Cgd in the Saturation Region (V, > V,,
I<
..I> ./
16
Figure 3.2.2a shows the cross section of a NTFT in the saturation region (V&>Vdsat and V,,>V,). The inversion charge density drops from Cox(VgsV~Vs) the source (y,) to at Cox(VgsVTV&at)at Ydsa[, where V(Ydsat)=Vdsa[.Then the charge density stays constant at Cox(Vgs'VTvdsar) from Y&at to the drain (Yd), which is known as the velocity saturation region
141. The gate charge is :
Qg = U i n
+
Qsat
+
Qbulk
YS
Ydsat
Qlin is the charge from ys to Ydsat. Qsat is the charge in the velocity saturation region. Assuming that the gradual channel approximation still holds from y, to Ydsat, Qlin can be expressed as a function of voltage bias in the same way as section 3.2.1.
Qsat is approximated as :
KO [5] shows that :
(
vd
)2 +
17
112
ESat 2
Therefore,  . 1s
a m
av,
cgd
is defined as  Since Qbulk is not a strong function of v d , c g d is : aQg ,
avd
3.2.3 C, in the Linear Region (0 < V& < Vdl, V, > V g J
From charge conservation, one can conclude that
3+ 3 + = 0. Since Cgd is aQg av, av, a v d
and C,, is , aQ, aQg
avd
aS v
C,, can be expressed as :
Using the same approach as in section 3.2.1 and performing the integration, Qg becomes :
2
 'gst
)
+
Q bulk
Therefore, i s : aQg
3%
18
To compute C,,, the above equation and the Cgd equation from section 3.2.1 will be substituted
3.2.4 C, in the Saturation Region (V, > Vdh, V,, > Vsh)
Following the same approach in section 3.2.3 and 3.2.2 (figure 3.2.2a), Q, is expressed as:
Qg = Qbulk + Qlin
+
Qsat
Qsat = Weff CoxVgstdsatAL
Qsatis the charge in the velocity saturation region. Qlinis the charge from ys to Ydsat (figure 3.2). ()bulk is the depletion charge. Since Qbulkis a weak function of Vg, dQg/dVg is :
aQg = aQ1in I aQsat
av,
av,
av,
19
To compute C,,, the above equations and the Cgd equations from section 3.2.2 will be substituted
into Cgs = 3Qg
3%
cgd
3.2.5 Connection Scheme between Linear and Saturation Region (vg>vgh, Vdl<V&<Vdh)
C
a Cg
g
I
'dsat "dsat' 'dtranhc
_ _ _ _
K
Transition Region
4
Sat Model
/
u
va v& Figure 3.2.5a: Strong inversion transition region model scheme
To reduce the discontinuity between the linear and saturation region, a linear function is used to connect the two regions. A straight line is drawn between cgd(cgs) at v d h to cgd(cgs) at vdl. Figure 3.2.5a below illustrates this idea. The linear function used is
c g s = acgsvds + bcgs
acgs 
 Cgsh
 cgsl
vdh  vdl
20
Cgsh
and Cgdh are computed using the equations in the saturation region at the applied V,, and Vdh. cgsl and Cgdl are computed using the equations in the linear region at the applied V,, and
vdl.
3.3 Subthreshold Region Model
W/L=20/5.3
10
8
6
4
2
0
2
4
6
8
10
12
14
Figure 3.3.la : c,, and Cgd vs vg
3.3.1 Cgd Model (Vss < V&)
Figure 3.3. la shows the c,d and C,, data in a Vg sweep. Following the behavior of a bulk
MOSFET, Cgd gradually decreases to 0 when the TFT is switched from the strong inversion to the weak inversion region. Figure 3.3.lb shows the scheme of the empirical model from the
strong inversion to weak inversion region. A linear function, Cgd = (
Vguan
vgs v,l),
is used to
modeled this region. The boundaries of the region are Vgh and V,,. Vguan is Vguanhc+Vguanlc (figure 3.3. lb). Cgdh is computed using the equations in the strong inversion region at the applied V and Vg,. ,
21
Model in the
Model In the strong invenion region
C gdh
Figure 3.3.1 b : Modeling scheme for Cgd weak inversion region However, the RC coupling between the drain and substrate makes c g d increases in the GIDL [ 3 ] dominant region (figure 3.3. la). This does not happen in bulk MOSFET because of the presense of the bulk contact. The coupling efficiency depends of the junction leakage. Acgd describes this coupling efficiency. Therefore, c g d at Vgs<Vgl is modeled as :
Cgd =[
1
weff Leff cox
1
+
Acgdld
The maximum Cgd possible is WeRLeffCox.The above formulation will limit Cgd to WeHLeftCox.
3 3 2 C,, Model (Vp. c V&) ..
C,,, similar to Cgd (figure 3.3.la), also gradually drops to 0 from strong inversion to weak inversion region. The same scheme from section 3.3.1 is applied to model the gradual change in Cg, when Vgs is between Vgl and Vgh, i.e. Vgl<Vgs<Vgh. Vgtran is V g w m c + V g t r d c(figure 3.3.2a). Cgsh is computed using the equations in the strong inversion region at the applied v, and
Vgh.
Vgtran
The RC coupling effect is higher in C,, (figure 3.3.la). Acgs describes this coupling efficiency, Cg, at Vgs<Vgl is modeled as : 1
=
weff Leff cox
1
c,,
22
The maximum C,, possible is WeffLeffCox.The above formulation will limit C,, to WeffLeftCox. c
V
u
>
Figure 3.3.2a: Modeling scheme for subthreshold C,,
23
3.4 Verification The parasitic capacitance from the measuring equipment and the drainsource overlapped capacitance are subtracted from the data in the following graphs. Figure 3.3a and b plot the C,, and C,, vs V,, of a nchannel TFT. Figure 3 . 4 ~ d plot the C,, and C,, vs V,, of a pchannel and TFT. Figure 3.42 and f plot the C,, and Cod vs V,, of a nchannel TFT.
o
V,, =3.5V data V
gst
o
0.025A
=7Vdata
Vgs,=lo.!% data Vi,, =14V data Vgst=3.5V model
v
__
W
Vgst =7V model
0.005
1
.
1
'
1
'
1
0
2
4
6
0
10
12
14
Figure 3.4a : C,, vs V, for NTFT with Weff/Leg=20/5.38 and T0,=76nm
24
0 030

0 028

0 026
0 024
A 0
0
cr
0 022
Vgst =1 O W data
V
9s'
0
0 020
v
=14Vdata
\
__ _
Vgst =3SV model
Vgst =10.5V model
\ \ \
\
\
' l ' l
Vgst =7V model
0.018
Vgst =14V model
"."I"
,
0
.
;
'
1
.
1
'
.
l
4
6
10
12
14
Figure 3.4b : C,, vs V, for NTFT with Weff/Lep20/5.38 and T0,=76nm
0
Vgst =3.5V data
0.020

0
Vgst=7V data Vgst=10.5V data VgSt =14V data
A
v
W
 Vgst=3.5V model  =7V model Vgst  V,, =10.5V model
v,,
(VI
Figure 3 . 4 ~ Cgd vs V, for PTFT with We&efi=20/4.42 and T0,=76nm :
25
Oo2.i
V
0""
1
vgst =3.5V data
0
V, , V , V, ,
=7V data =14V data =3.5V model =7V model
A
Vgst=10.5V data
v
__
 ,, V
_ _ Vgs1 =10.5V model  =14V model Vgs1
0.016I
0
l . I . , . , . I
I
1
2
4
6
8
10
12
14
Figure 3.4d : C,, vs V b for PTFT with W e & e ~ 2 0 / 4 . 4 2 and TOx=76nm
0 0
0 0
0
Vds=3.5V data Vds=10.5V data
A
Vds=7V model
Figure 3.4e : Cgd vs V,, for NTFT with We&,~20/5.38 and TOx=76nm
26
Vas =3.5V data
0
,V ,,
=7V data a
Figure 3.4f : C vs V,, for NTFT with Weff/Leff=20/5.38 T0,=76nm , , and
27
Chapter 4: Spice Implementation
4.1 Overview
The special features of SPICE implementation of the model and the model parameters names are discussed in this chapter. Section 4.2 lists the model parameters, their meanings and their default values. Section 4.3 describes special features in the implementation of the model.
4.2 Model Parameters
Table 4.2 lists all the parameters used in this model. Symbol is the symbol used in the equations summarized in appendix A. Spice Name is the spice model parameter name.
28
iwi I
Default
0.01
0.00308
1010
0.05
t
6.5
108
Vatran,
Va**h
vgtranl vgtranh
transition parameter for Id in V,, domain transition parameter for Id in V,, domain
V
V
1.5
1
V
vdtranlc
29
V
Section 4.3: Implementation of Model 4.3.1: Cgd and C, Model Implementation
c,d and C,, are proportional to l/Id in the strong inversion region. When V a 2
is small, Id
is very small. This may cause Cgd to become unreasonably big and inaccurate. Therefore c,d and C,, are set to 0.5COxwhen V,<O. 1V to prevent this situation. Two capacitance models are implemented. They are (1) the one described in chapter 3, and (2) a simplified version of chapter 3 for speed consideration. The flag cmod is used to specified which model to use. When cmod is 1. (1) will be used. When cmod is 2, (2) will be used.
(1) and (2) are identical in the subthreshold region and strong inversion linear region. The
difference is in the saturation region. C,, and C,, of (2) in the saturation region are set to 0 and 2/3CoxLeEWeg(see fig 4.3. la).
'gsl'gd
'gs IC gd
cmod= 1
0.5c0K I\
"dsat
cmod = 2
Figure 4.3.1.a: Difference between the two capacitance model (cmod=l and 2)
30
Chapter 5: Simulation Results
5.1 Overview
This chapter compares the results of a 33stage ring oscillator simulation with measured data. The drawn size of all pchannel T n is 16pd7pm. The drawn size of all nchannel TFT is 9 p d 7 ~ mThe oxide thickness is 76nm. Section 5.2 compares and discusses the simulation results . and measured data. The data will be presented in both tables and graphs.
5.2 Simulation Results and Measured Data
Table 5.2a tabulates the simulation results and measured data. Figure 5.2a and 5.2b plots the results in the table. A positive error means the simulation overestimate the data. A negative error means the simulation underestimate the data. Table 5.2a: Simulations Results and Measured data
Vcc Freq from (V) Simulation (MH4 6 0.62 7 0.83 8 1.13 9 1.48 10 1.8 11 2.15 12 2.36 13 I 2.78 14 I 3.2
Freq from % Error Measured data (MH4 0.277 124 0.504 65 0.788 43 1.11 33 1.52 18 12 1.92 2.42 2 I 2.99 I 7 I 3.66 112
Power from Simulation (mW) 0.075 0.145 0.255 0.42 0.65 0.935 1.38 I 1.82 1 2.45
Power from Measured Data (mW) 0.033 0.084 0.17 1 0.3 18 0.548 0.854 1.31 I 1.92 I 2.82
% Error
127 73 49 32 19 9.5 5
I
5
113
31
W
4
:3 E
h
W
data
2
1W
V I
I
I
1
I
6
8
10
12
14
Figure 5.2a: Compare simulated and measured frequency of a 33stage ring oscillator.
41 1
3
rn
6
8
10
12
14
v,
(VI
Figure 5.2b: Compare simulated and measured power of a 33stage ring oscillator.
32
The simulation results in the higher V, region is more accurate then those in the lower V, region. In the lower V, region, the simulations overestimate the frequency and power, because the capacitance model underestimates the capacitance data by a large margin. Therefore the percentage error is big. In the higher V, region, the simulations underestimate the frequency and power. because the drain current model underestimates the drain current data by a small margin. Therefore the percentage error is small.
33
Appendix A: Equations Implemented in SPICE
This appendix summaries all equations implemented in spice3e 1. Section 1 lists the drain current model equations. Section 2 lists the capacitance model equations. g, is d1, / dVg,. g b is
a, I av,, .
Section 1: Drain Current Equations First of all, we need to define the boundaries of different regions (Figure 2. la) and some common symbols.
VT = vTo  bT
vgst = vgs  " T
1
cox = €, 0
'o Tx
Vdsat
=[k+ )
1
E sat Leff
vdss = vds  vdsat
2vsat Esat =
Peff
Leg =L2L,
weg ' W  2 W m
vdl
= vdsat
 vdtranl
vdh
= vdsat
+ vdtranh
Vgl= VT  Vguanl
vgh = vT + Vguanh
1.1 Strong Inversion Linear Region: V,>V@ and O<Vds<Vdl
34
35
36
1.3 Subthreshold Region: Vgs < Vgl
Id = Idiff
+
thermal + Igidl
Igidl
= weff Agidl ( vdg  vi
)
. p(
Bgidl vdg  vi
)
gidl vdg  vi
q('gs
 vT
kTn
 voff
]+.gidl[
1+
)ex(
~~~~i
]
)
kT/q
vgsvTvoff)
*gidl
[
1+
Bgidl vdg  vi
)exp[
Bgidl vdg  vi
kT/q
else
(kT s > n
37
1.5 Transition between Strong Inversion and Subthreshold Region: Vgl<Vgs<Vgh
vgs= vgl( 1
t) 2 + 2Vgpt( 1 t ) + Vght 2
t=
(vgl
 vgp) +/(vgp
2
 vgl)
(vgl
2vgp
Vgh)(vgl
 vgs)
vgh  vgp tvgl
38
39
Section 2: Capacitance Model Equations First of all, we need to define the boundaries of different regions (Figure 3. la) and some common symbols.
2.1 cgJ Strong Inversion Linear Region: Vgs>Vg., and o<vh<vd in
2.2 Cgd in the Strong Inversion Saturation Region: Vgs>V& and V&>V& If cmod= 1. then
40
E, =
else if cmod=2, then
cg, = o
2.3 Cgd in the Subthreshold Region: Vgs<Vgh If Vgs>Vgl, then
else,
/
1
1
1
+
Cgdh is the c,d computed at Vgs"Vgh and the applied V, .
If V&>Vdsat, then the equations in section 2.2 are used. Otherwise, the equations in section 2.1 are applied.
2.4 Cgd in the Strong Inversion Transition Region: v,>vgh and Vdl<V&<Vdh
Cgd = acgd vds
+ bcgd
acgd =
Cgdh  cgdl vdh  vdl
Cgdl is the Cgd computed at v & = v d l and the applied Vgs using equations in section 2.1. Cgdh is
the Cgd computed at v&=vd, and the applied v,, using equations in section 2.2.
2.5 C, in the Strong Inversion Linear Region: V,>Vghcgs and O<V&<Vdl
41
Cgd is the c g d computed at the applied Vgs and v,.
2.6 C, in the Strong Inversion Saturation Region: V,>Vgh and V&>V&, If cmod= 1, then
else if cmod=2, then
2.7 C, in the Subthreshold Region: V,cV& If Vgs>Vgl, then
42
else.
 1
Cgs =
I
weff Leff cox
t) '
Acgsld
Cgsh is the Cgs computed at Vgs'Vgh
If V&>Vdsat, then the equations in section 2.6 are used. Otherwise, the equations in section 2.5 are applied.
and the applied V,.
2.8 C, in the Strong Inversion Transition Region: V,>v& and Vdl<V&<Vdh
c g s = acgsvds + bcgs
cgsl the is
acgs 
 Cgsh
 cgsl
vdh  "dl
cgs computed at v&=vd, the applied v,, and
using equations in section 2.5. Cgsh is
the Cgs computed at v & = v d h and the applied Vgs using equations in section 2.6.
43
Appendix B: Parameter Extraction
This section discusses the parameter extraction procedures used in this project. A spreadsheet program, EXCEL 4.0, is used to visually fit the model with the measured data for both the drain current and capacitance model parameters locally. Temperatures are in unit of Kelvin. Section 1 discusses the drain current Parameters extraction. Section 2 discusses the capacitance parameter extraction. Section 1: Drain Current Model Extraction
To extract the drain current parameters with temperature dependence, the following measurements are needed at different temperatures (e.g. 300K, 325K, 350K, and 375K) are needed. If temperature dependence is ignored, only one set of data is necessary. 1) C,V,, data with both drain and source grounded (e.g. V,, = 3V to 12V) 2) IdV, data with several Vgs bias bigger than VT (e.g. V, = OV to 12V and V,, = 3V, 6V, 9V, and 12V) 3) IdV,, data with different V, bias (e.g. Vgs = 5V to 12V and V, = 0.1V and 5V) The gate oxide thickness and process lateral diffusion length must be extracted first. Section 1.1 to 1.5 describes the extraction of the parameters in different regions. Section 1.6 discusses the order of extraction.
1.1: Threshold Voltage (VTo and b) We use the equation Qn = Cox( Vgs  VT) to define VT. First of all, CgVgs data are measured with both the drain and source grounded. Then the parasitic capacitance is subtracted
"ss
from C,. Q, is computed by integrating the CgVgs curve using the relation Qn( Vgs) = j C g d V .
W
A straight line will be fitted to Qnand the xintercept is VT (figure bl).
44
A
subtract
A
capacitance
par
Figure b 1: VT extraction procedure
If the temperature dependence is ignored, VTo is V, and b is 0. To extract the temperature
dependence, b, VT's at several temperature are measured. Then a linear fit is used to determine VTO and b, where VT = VT  bT.
At a particular temperature, peffis modeled with an expression in the form of A exp( B / ( Vgs  VT)) + p4, where A and B are function of temperature, oxide thickness, and mobility parameters. An estimate of A, B, and p4 are obtained by fitting the peffat low drain bias (e.g. 0.lV) using the Idvg, data. When A increases and B decreases, peg increases. p4 determines peffat V,, close to VT. peffincreases when p4 increases. Since the objective is to fit the drain current in the strong inversion linear region, the estimated A and B are further optimized by fitting the Idv& data in the strong inversion linear region (figure b2) with Vgs>V~. Using the IV curves at different temperatures, different sets of A and B are found. Then we can compute po, p1, p2,
P3, and P4.
45
'd
Figure b2: strong inversion linear region
1.3: Saturation Velocity (vsat)
vSataffects the magnitude of the drain current when V, is near Vdsat and the location of
Vdsat. When vSat increases, Vdsat and Id increase. vSat is extracted by visually fitting the drain current near Vdsat and the location of Vdsat (figure b3).
'd
region to be fitted
> "ds
Figure b3: extracting vsat
1.4: DIBL, Channel Length Modulation, and Hot Carrier Effects (e, 8, SI, and s2)
and 8 affects V,. When ! 8 increase, V, drops and Id increases. S I and s2 affect the and hot carrier tail at high V,. When S I increases and s2 decreases, the hot carrier effect will be more pronounced (figure b ) S I is set to 1.2 for NTFT and 2.2 for FTFT in this study. Only s2 is varied 4. to fit the data. However, the user can vary both s1 and s2 as they see fit.
46
'd
A
region affected by sl and s2
region affected by
and € I
?
'
Figure b4: effect of
SI,
"ds
s2,
e, and 8
1.5: Subthreshold Region (n, V , , Ido, Agidl, Bgidl, Vi, E,, and Ithermalo) I&, n, and V,E affect the region where the diffusion current dominates. When n and 1 , increase and Voff decreases, the diffusion current increases. Huang [ 11 shows that I, is a function
of substrate doping. 1 is treated as a model parameter in this model. Agidl, Bgidl, and Vi affects , the region where the GIDL effect dominates (vdg is big). When Agidl increases, Bgidl decreases, and Vi decreases, the GIDL current increases. Ithemaloand E, set the minimum leakage current. The thermal generation current is not a function of bias. When E, decreases and Ithemalo increases, the thermal generation current increases. To extract Ithemalo and E,, Ithema1 at different temperature are extracted first. Then Ithemalo and E, are extracted from the Ithemd found. If temperature dependence are not extracted, then Ithemdo is Ithemd and E, is 0. Figure b5 illustrates the regions that the above parameters affect. In(ld 1
\
thermal current
vss
Figure b5: different regions of the subthreshold region
47
1.6: Order of Extraction
1 ) Extract threshold voltage parameter (VTO and b). 2) Extract mobility parameters in the linear region of I d v d (PO, pl. p2. p3, and pq).
3) Adjust vSat to fit the V&at location and Id near Vdsat. 4)Adjust P , 8, S I , and s2 to fit the saturation region of the IdVd curves. 5 ) Extract n and V,, for diffusion current. 6) Extract Agidl, B,idl, Vi, and Itherrnal together for GIDL and thermal generation current. 7) Repeat the extraction of Ithema1 for different temperature to extract Ithemalo and Ea. 8) Adjust Vgtranl, Vgtranh, Vdtranl, and Vduanh to improve Continuity. Section 2: Capacitance Model Extraction
For C,, and c g d , only A,,,, Acgd, and the transition region parameters need to be extracted. The following measurements are needed.
1) C,, and Cgd in a Vds sweep with different V,, bias (e.g. V = OV to 12V and V,, = 3V, 6V, , 9V, and 12V) 2) C,, and c g d in a Vgs sweep with different V bias (e& V,, = 5V to 12V and V, = 3V, 6V, , 9V, and 12V) The gate oxide thickness and process lateral diffusion length must be known. The parasitic capacitance and the overlap capacitance should be subtracted from the data. Drain current model parameters can also be slightly altered to fit the capcaitance data more accurately.
2.1 Acgs and Acgd
bgS Acgd affects Cg, and Cgd in the GIDL dominant region (V&>o, e.g. high V, and
in
accumulation region). When Acgs and ACgdincrease, C,, and c g d increase. A,,, and Acgd are extracted by fitting the model with the data in the GIDL. The GIDL dominant region in 3.3. la of chapter 3 is from between lOV and 2V. The figure is redrawn below.
48
0.050
0.045
1..
W/L=20/5.3
W
E
0.010
u
d%0.005
O.OO0
10
8
6
4
2
0
2
4
6
8
10
12
14
Figure 3.3. la : c,, and c@ vg vs
To extract those transition region parameters, we can just examine the data and get a reasonable estimate. Vduanlc and Vduanhc are the transition width from saturation to linear region on the V domain in CgsVh and C,,V, , data. A default value of 0.W for both Vduanlc and Vduanhc works well for the data used in this project. When the gate bias decreases below VT, C,, and Cgd gradually drop to 0. Vguanlc is the voltage below VT that C,, and Cgd drop to 0. The Cgd and C,, model assume a linear drop from (V,
+ vguanhc)
to 0 at (VT  Vguadc). Therefore, Vguanhcis the voltage above VT that the
model begin the linear drop (see figure 3.3.2a of chapter 3).
49
Reference
[ 11 J. Levinson. et al, Journal of Appl. Phys. Feb 1982, p. 1193
121 J. H. Huang, et al, IEDM Technical Digest, 1992, p. 569 [3] T. Y. Chan, et al, IEDM Technical Digest. 1987, p.718 [4] M. Sze. Physics of Semiconductor Devices, 2nd Edition S. [ 5 ] P. K. KO, et al, VLSI Electronics: Microstructure Science, Vol. 18, Chapter 1
50
Acknowledgments
I would like to thank Professor Ping KO, Hiroyuki Ikeda, and Takahide Inoue of SONY
Corporation for their assistance and support in this project. Without their technical advice and incredible patience, this project would not be completed. I would like to thank Kelvin Hui, Jian Hui Huang, and Mansun Chan for their useful discussion with me. I also appreciate the encouragement and support from my good friends, Robert Tu, Wilson Chan. Michael Ching, Amy Wang, and Joseph King. Finally, I must thank Hiroyulu Ikeda again for his great help and dedication in this project.
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