ESPRIT

Mixed Signal Design Cluster

Work Shop
Introduction to SigmaDelta Modulation
Prof. Dr. Qiuting Huang
SeedammPlaza, Pfäffikon, Switzerland October 22 ^{n}^{d} , 2001
Outline
q ADC as a Tracking Loop q Linearity and Quantization Noise q First Order SDModulator q Higher Order Loops q Cascaded Modulators q NonIdealities q Conclusions
Motivation for Oversampled Converters
q Need for spectral efficiency in communications systems (ADSL, UMTS, etc. ) => high requirements for A/D and D/A converters (1214 bit of resolution and linearity)
q VLSI technologies: Low component accuracy, decreasing analog signal dynamic range => difficult for Nyquist rate converters and anti aliasing filters
q IDEA: Exchange of speed + complexity vs. analog resolution
q Solution: Oversampled data converters, spectral shaping of quantization noise
Published SigmaDelta Converters
150
NAIKNAWARE00
140
130
Speed vs. Resolution
TradeOff
Audio
KERTH94
120
LEUNG97
Precision
110
FUJIMORI96
Measurement
ADSL
ADAMS86
GSM
100
RABII97
GEERTS00
BOSER88
LONGO93
90
BALMELLI00
Broadband Wireline
Communications
BURGER98
BURGER01
80
Speech
FELDMAN98
70
GEERTS00
HAIRAPETIAN96
Mobile
60
Communications
50
10
100
1k
10k
100k
1M
10M
100M
Dynamic Range [dB]
Input Signal Bandwidth [Hz]
Generic ADC as Tracking Loop
A/D (Quantizer)

u

A(u)

w

q(w)


n
















D/A


n

f(y)




x
y
Examples:

 DualSlope

 SAR

 SD  Modulation

A

o

q

o

x


A q
o
>> 1

y =

in signal band
æææææÆ
y

=

f



1 + A

o

q

o

f

 1
(x)
q D/A converter determines gain and linearity of entire A/D converter
D/A Converter Linearity and Quantizer Levels

q Dynamic Range Is Determined by Linearity and Noise

q Static Linearity Depends on Matching Accuracy of Components Except for a 1bit D/A

q Quantization Noise Decreases with Increasing Quantizer Levels

q Noise Power Is Spread Between DC and f _{s} /2

q DR Can Be Traded with Speed
General SinglePath SD Modulator
e(kT _{s} )
x(kT s )
w(kT s )
y(kT s )
+
H(z)
A/D

D/A
The power spectrum of quantizer error e(kTs) = y(kTs) – w(kTs) can be assumed white and uncorrelated with x(kTs), if the latter is sufficiently active.
The power of quantization error is:
e
1
=
2 p
Ú
E (
W
)
d
W
,
W =
w
T
RMSNoise in Signal Band
O dB corresponds to that of PCM sampled at Nyquist rate
Stability of Higher Order Modulators

j
w
T
1
e
s
2
6 dB
1
0
wT
p
s
0
Solutions:
NTF(z) = (1z ^{}^{1} ) ^{L} implemented with a
chain of integrators can lead to unstable modulator behavior for L ³ 3
Design of Single Loop Modulators
2. Compute H(z) H(z) = 1  1/NTF
1. Choose appropriate topology to implement H(z)
2. Compute coefficients
3. Simulate behavior with quantizer
10
0
10
STF
NTF
20
30
40
50
PassBand
60
70
80
90
100
3
4
5
6
10
10
10
10
c2
b1
b2
b3
d1
d2
d3
a1
a1 = 1/4
c2 = 0.0105
b1 = 1/4
b2 = 1/2
b3 = 1/6
d1 = 4/5
d2 = 3/5
d3 = 3/5
Þ dstoolbox (R. Schreier, ftp://next242.ece.orst.edu/pub/delsig.tar.Z)
Achievable SNR
Butterworth Type NTF (all zeros at DC)
160
L
= 5
140
L
= 4
120
L
= 3
100
L
= 2
80
60
40
20
0
4
8
16
32
64
128
256
Optimized NTF (zeros optimally spread over passband)
160
L
= 5
140
L
= 4
120
L
= 3
100
L
= 2
80
60
40
20
0
4
8
16
32
64
128
256
Stability of Single Loop Modulators
E(z)
X(z)
H(z)
k
+
Y(z)

Quantizer Gain
0 £ k £ 1

1

1
+ kH

(

kH

(
z
)

+ kH
(

z

NTF =
z )
STF =
 Ardalan/Paulos (TrCAS, Jun87)  Maguire/Huang (ISCAS94)
11 Cascaded Modulator
z 1

e
n
'
g
e
n 1
'
g
e
+
e

e
n
2
n
n
 1

X(z)
z 1

'
e
n
'
(
x
+
e

e
)

Y(z)
n
n
'
n  1
z 1
z 1
'
'
y
ª
x
+
(1

g
)(
e

e
)

(
e

2
e
+
e
)
n
n
2
n
2
n

3
n
n

1
n

2
Þ Performance depends on matching of analog and digital transfer functions
SD Modulator NonIdealities I
q
Nonlinear STF due to quantization (Huang/Maguire (ISCAS 93))
 Example: 3 rd order modulator with inv. Chebychev NTF
Output Spectrum at Maximum Input Level
0
20
40
60
89 dB 89 dB
80
Harmonics
100
3rd
120
140
10 3
10 4
10 5
10 6
Frequency [Hz]
Integrated Systems Laboratory
ETH Zürich
SD Modulator NonIdealities II
q Tones
 Limit cycles in the passband
 Tones near f s /2
Output Spectrum of 2x PassBand Width
Output Spectrum Near fs/2
0
0
Tones
 6 dB
20
20
full scale
40
40
 DCinput @ 51 dB
60
60
full scale
80
80
Tones
100
100
120
120
30 kHz sinusoidal input
@43 dB full scale
140
140
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
5.7
5.8
5.9
6
6.1
6.2
6.3
6.4
6.5
x 10 5
Frequency [Hz]
x 10 6
Frequency [Hz]
q Circuit nonidealities ® other presentations
Integrated Systems Laboratory
ETH Zürich
Conclusions
q Linearity of an A/D converter is determined by that of its D/A q Matching accuracy is typically limited, which makes linearity a problem for monolithic integration of A/D converters q Onebit D/A is potentially very linear, but too much noise is generated by a 1bit quantizer q Noise shaping, effected by feedback, enables S and N to be separated q A SD converter is therefore a combination of 1bit quantizer for linearity, noise shaping for S and N separation and digital filtering for noise removal