3rd International Conference on Computing, Communication and Sensor Network, CCSN2014

Dynamic Self Controllable Surfing for Differential On-Chip
Wave-Pipelined Serial Interconnect: A sample Template of CCSN2014
Bhaskar. M, Srinivas Gantasala, Venkataramani. B
Department of Electronics and Communication Engineering
National Institute of Technology, Tiruchirappalli – 620015, INDIA
bhaskar@nitt.edu, srighantasala123@gmail.com,bvenki@nitt.edu

ABSTRACT
Papers for CCSN2014 should be of type: research paper,
survey paper, tutorial paper or published paper taking
permission from previous authority for reprinting. This
word document will be considered as standard template of
paper preparation in all respects like header, paragraphheader, fonts, space, two-columns, caption of figure,
reference etc. Paper page limit is maximum six pages of
A4 size paper. The Title of the paper should be of 14
points, authors names are of 11 points, affiliations and
other body points should be of 10 points of Times New
Roman font. It is a sample text of a paper that got 1 st
award in one of our conference Micro2014 which was
held in Hyatt Regency, a 5 Star Hotel, in Kolkata, India
during 11th to 13th of July 2014. Here, texts of that paper is
deleted/distorted as it is waiting to be published in a
Springer Journal. Authors should follow all other points
mentioned in this papers as caption of figure(9pts),
caption of Tables(8pts capital letter), equations numbering
should be right aligned as fonts mentioned here. No page
numbers should be inserted. Header should contain the
conference name as mentioned in this document.
References should be inserted as [3][4].
Keywords: Controllable inverter pair, Differential
interconnect, Method of logical effort, Repeater insertion,
Self controllable, Serial link, Surfing, Wave-pipelining
I.

Introduction

xxxAs the CMOS technology scales down, transistor
sizes get reduced and this in turn increases the speed of
the logic blocks [1]. However, interconnects used for
routing signals between logic blocksxxx.
xxxThe method of logical effort is proposed in [16] in
order to design a CMOS circuit such that it operates at a
particular frequency consuming the least area and power.
In this paper, the proposed circuits are designed using the
method of logical effortxxx.
XxxThe paper is organized as follows: Section II, III
describe the design of differential wave-pipelined serial
interconnect with surfing using UR and NUR
respectively. Section V provides the post layout
simulation results and the observations. The concluding
remarks are given in Section VIxxx.
II. Drawing figures
All figures should be in black and white color. Our
proceeding book is printed in B/W color. Some Color

figures become non visible after printing in B/W.
Drawing figures, the common problems are: placing all
components inside a same figure, putting text inside the
boxes, giving arrow symbol, making label text inside. To
solve these problems, it is suggested to draw figure within
a canvas drawing area(in word-it is available
insert>shapes>new drawing canvas). In different versions
of word it may be found in different menu-submenu. But
drawing must be within a fixed boundary that if texts of
the paper is deleted or edited, components of figures may
remain in same positions. MSWord version is required for
the printing press where reediting(in some cases) become
easier for press people. They need MSWord version of the
paper.
Figure’s caption should be as mention in this document.
All texts mentioned within figure should be readable. No
color fonts should be used for proceeding book but after
conference if the paper is selected for Journal publication,
then paper should be reformatted according to the authors
guide line of that particular journal. In digital journal,
number of pages may be more and color figures can give
better outlook. As color printing cost is more, we avoid
color figures for proceeding printed book. But, sometime,
for reference color photo may be required to use but we
shall print it in B/W color.
Another way of converting your figure to a picture is that:
press ‘print Screen’ button from keyboard and then insert
in a place of document, then paste the thing pressing
ctrl+v, then double click on the figure, press crop, cut
unnecessary portion of figure and making a picture with
all of its components is done and there are no chance to
be displaced of components of figure.

True True out Comp out Comp RX Dynamic self Controllable Inverter Pair Comp True Fa Fas Fig. . Schematic diagram of differential wave-pipelined serial interconnect with surfing and UR. 2. CCSN2014 Fig.3rd International Conference on Computing. 3 TOUT M1 CIN 1 TOUT M2 (a) a) Surfing signal 3 3 M3 COUT TIN M5 3 M7 TOUT 1 M4 COUT 1 M6 COUT 1 M8 (b) Fig. Communication and Sensor Network. Dynamic Self Controllable inverter pair Surfing circuit for complement path b) Surfing circuit for true data path. Schematic diagram of wave-pipelined segment. 3. 1.

2001.Ho. Alpert.P. power. For our paper.B.52cm. 90–104. 490-504. superscript. and J. (2001). Margin: top. Equations In [15] This paper In [15] This paper 1. 2.” IEEE Trans.parasitic delay of the path (sum of parasitic delay of each stage) � .W. The design of the transceiver with self controllable surfing scheme for uniform repeater and non uniform repeater insertion is carried out using the method of logical effort and their performances are compared. “Optimal interconnection circuits for VLSI. CONCLUSION D = (N F1/N + P) τ (2) where. footer=1. Line spacing. 2001.path effort P . vol.True B. pp.69 R b Cb 0ntt + 0. using especial fonts is a problem in equations printing. The proposed schemes can be used for higher data transfer rates through differential on-chip global interconnectxxx. Communication and Sensor Network. space before paragraph and after paragraph should be as Comp used in this documents. year. no 4. height=29.69 w b [ a+arf+a r 2 f 2 +…+a r N-1 f N-1 ] L + 0. margins are like: Top=2. title of the book. Indent TX The designs of differential wave-pipelined surfing interconnect with UR and NUR is carried out for 40mm metal 4 interconnect in UMC 180nm technology. C.0 340. paper size= A4(21x29. Quay. 2001. 903–909. 89.” Proc. paper. Fishburn. and M. subscript etc can be adjusted through equation editor. J. width=21cm. In this document ‘Cambria Math’ font of 10pts is used. Computer-Aided Design Integrated Circuits and Systems 20 (1). orientation=portrait. pub name. A. bottom=2. Other issues not mentioned should be as applied within this paper. It is found in Page Layout>Margin>custom margin (it may be in other menu of other version. The proposed surfing interconnects with UR and NUR have higher data transfer rates and allow higher input jitter. and S.01. Interconnects section.J.00 366. . R b N-1 ] Rb .0 The absolute delay (D) of a circuit consisting of N stages is given by [16] VI. The post layout simulations are carried out using Cadence Virtuoso tool. Devgan. p.0cm. Do not use condensed spacing or more than single line spacing. CCSN2014 A. “Interconnect synthesis without wire tapering.69 + [ 2 N-1 R b Cw ar a r ar a+ + 2 +…+ N-1 L f f f ] R C + 0. No indenting at beginning of the paragraph.5 5 2. vol. Spacing and position of power symbols. “The future of wires. NUR in [15] and the proposed self controllable surfing for differential wave-pipelined serial interconnect for UR and NUR are given in Table IV. 4 [2] R.0 384.6 3.00 643.7 3 2.38 R w Cw L 2 2. dynamic self controllable inverter pair is proposed for surfing the differential wave pipe-lined serial interconnect.7cm.60 All equations should be in 10 pts.A. Left and right margins =2. IEEE.Horowitz. [ a 2 +a 2 r 2 + a 2 r4 +…+ a2 r 2(N-1) ] [3] (5) [4] V RESULTS Max. two column.D. Delay of the longest segment in NUR(ps) C.49cm. 1985. bottom and columns All margins should be like this paper template.T. this document is prepared under windows vista). f Cb f References fshould contain: authors names. clearly mentioning subscript. pp. Electron Devices ED-32 (5).technology constant (12ps for 180nm) [ T p =0. Semiconductor Industry Association. Meindl. ” IEEE Trans.f Cb +…+ N-1 .7cm). operating frequency in Gb/s H. K. pp. symbols etc.94 xxxIn this paper.Mai. Bakoglu. F .02cm. issue numbers. header= 1.3rd International Conference on Computing. TABLE III DELAY AND POWER OF THE INTERCONNECT WITH NUR FOR DIFFERENT INTERCONNECT RATIO Ratio of interconnect segments (r) Line spacing will be one. References [1] International Technology Roadmap for Semiconductors. Right aligned. Text size of references should be of 9pts.