Revised May 1999

CD4047BC
Low Power Monostable/Astable Multivibrator
■ True and complemented buffered outputs

General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, and the output frequency in the
astable mode.
Astable operation is enabled by a high level on the astable
input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of
Q is available at the Oscillator Output; a 50% duty cycle is
not guaranteed.
Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at − trigger input. The device can
be retriggered by applying a simultaneous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.

■ Only one external R and C required
MONOSTABLE MULTIVIBRATOR FEATURES
■ Positive- or negative-edge trigger
■ Output pulse width independent of trigger pulse duration
■ Retriggerable option for pulse width expansion
■ Long pulse widths possible using small RC components
by means of external counter provision
■ Fast recovery time essentially independent of pulse
width
■ Pulse-width accuracy
approaching 100%

maintained

at

duty

cycles

ASTABLE MULTIVIBRATOR FEATURES
■ Free-running or gatable operating modes
■ 50% duty cycle
■ Oscillator output available
■ Good astable frequency stability
typical= ±2% + 0.03%/°C @ 100 kHz

Features

frequency= ±0.5% + 0.015%/°C @ 10 kHz

■ Wide supply voltage range:

3.0V to 15V

■ High noise immunity: 0.45 VDD (typ.)
■ Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS

deviation (circuits trimmed to frequency VDD = 10V
±10%)

Applications
• Frequency discriminators
• Timing circuits

SPECIAL FEATURES
■ Low power consumption: special CMOS oscillator
configuration

• Time-delay applications

■ Monostable (one-shot) or astable (free-running)
operation

• Frequency multiplication

• Envelope detection
• Frequency division

Ordering Code:
Order Number

Package Number

Package Description

CD4047BCM

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

CD4047BCN

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

© 1999 Fairchild Semiconductor Corporation

DS005969.prf

www.fairchildsemi.com

CD4047BC Low Power Monostable/Astable Multivibrator

October 1987

9. 9. 14 5. Typical Implementation of External Countdown Option tEXT = (N − 1) tA + (tM + tA/2) FIGURE 1. www. 13 tA(10. 13 Positive-Edge Trigger 4. 9. 8.20 RC Complement Gating 6. 14 5. 11. 6. 11) = 4. 12 Figure 1 Figure 1 Note 1: External resistor between terminals 2 and 3. 7. 9. 14 5. 12 10. 5. 9. 14 5.CD4047BC Connection Diagram Pin Assignments for SOIC and DIP Top View Function Table To VDD Function Terminal Connections Output Pulse To VSS From Input Pulse To Typical Output Period or Pulse Width Astable Multivibrator Free-Running 4. 6. 13 tA (13) = 2. 12 4 10. 7.com 2 tM (10. 8. 6. 12 5 10. 6. 7. 6. 9 8. 12 10. 8. 14 7. 14 7. 12 6 10.40 RC True Gating 4. External capacitor between terminals 1 and 3. 7.48 RC Figure 1 . 11.fairchildsemi. 11) = 2. 11 Negative-Edge Trigger 4. 11. 11 Monostable Multivibrator External Countdown (Note 1) 14 5. 9. 11 Retriggerable 4. 7. 8. 12 8 10. 8.

com .CD4047BC Block Diagram Logic Diagram *Special input protection circuit to permit larger input-voltage swings. 3 www.fairchildsemi.

5 2. VO = 0.05 V |IO| < 1 µA VDD = 5V 4.0 µA Note 4: IOH and IOL are tested one output at a time.5V −1.5V or 13.44 0.95 V VDD = 10V 9.05 0 0.com 25°C Min VDD = 10V VDD = 15V.0 VDD = 5V.5V or 4.5V VIH Max 4 .5V to VDD +0.5VDC −65°C to +150°C Storage Temperature Range (TS) 700 mW Small Outline 500 mW −40°C to +85°C Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.0 5.0 8.0 −8.5V or 13.25 11. 260°C DC Electrical Characteristics (Note 3) Symbol IDD VOL VOH VIL Parameter Quiescent Device Current LOW Level Output Voltage HIGH Level Output Voltage LOW Level Input Voltage −40°C Conditions Min IOL HIGH Level Input Voltage LOW Level Output Current (Note 4) IOH HIGH Level Output Current (Note 4) IIN Input Current Typ 85°C Max Min Max Units VDD = 5V 20 20 150 µA 40 40 300 µA VDD = 15V 80 80 600 µA |IO| < 1 µA VDD = 5V 0.8 −2.3 1. VO = 1. VO = 4.5 2.75 3.5V to +18VDC DC Supply Voltage (VDD) Input Voltage (VIN) DC Supply Voltage (VDD) −0.25 1.05 0.3 1.4 mA VDD = 15V.5 3.3 10−5 0.5 V VDD = 10V.52 0.8 2.5V −3.52 −0.25 −0.1 −2.95 9.05 0. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. VO = 0.9 VDD = 15V.0 V 6.88 0. VIN = 15V 0.0 V 4.95 V VDD = 15V 14. VO = 0.95 14.6V −0.25 0.95 5 4.5V 1.95 15 14.5 3.0 4.5V 11. VO = 9.0 8.36 mA mA VDD = 10V. VO = 1V or 9V 7.75 4.05 0 0. www. VO = 1.5 7.CD4047BC Absolute Maximum Ratings(Note 2) Recommended Operating Conditions (Note 3) (Note 3) −0. Lead Temperature (TL) (Soldering.5 V VDD = 10V.0 7.0 3.5 1.95 4. They are not meant to imply that the devices should be operated at these limits. VO = 0.95 10 9.44 −0.5V or 4.05 0.5V 3. VO = 1.5V 1. VO = 1V or 9V 3.1 2.88 −0.95 V VDD = 5V.9 mA VDD = 15V.4 mA VDD = 5V.3 −10−5 −0.4V 0.36 mA VDD = 10V.0 V VDD = 5V.3 −1.5V 3.0 µA VDD = 15V.6 3.05 V VDD = 10V 0.fairchildsemi. 10 seconds) 0 to VDD VDC Operating Temperature Range (TA) Power Dissipation (PD) Dual-In-Line 3V to 15VDC Input Voltage (VIN) Note 3: VSS = 0V unless otherwise specified.05 V VDD = 15V 0.05 0 0.0 V VDD = 15V.3 −1.6 −3.0 11. VO = 13.0 4. VIN = 0V −0.

tPLH tPHL. RL = 200k. CL = 50 pF. tWH tRCL. unless otherwise specified. tTLH tWL. Retrigger to Q Reset to Q. Q Transition Time Q. Osc Out Minimum Input Pulse Duration Conditions Min VDD = 5V 550 900 ns VDD = 10V 250 500 ns VDD = 15V 200 400 ns VDD = 5V 700 1200 ns VDD = 10V 300 600 ns VDD = 15V 240 480 ns VDD = 5V 300 600 ns VDD = 10V 175 300 ns VDD = 15V 150 250 ns VDD = 5V 300 600 ns VDD = 10V 125 250 ns VDD = 15V 100 200 ns VDD = 5V 100 200 ns VDD = 10V 50 100 ns VDD = 15V 40 80 ns Any Input VDD = 5V 500 1000 ns VDD = 10V 200 400 ns VDD = 15V 160 320 ns + Trigger. Parameter VDD = 5V 200 400 ns Astable to Osc Out VDD = 10V 100 200 ns VDD = 15V 80 160 ns Astable. Retrigger. tPLH tTHL. − Trigger to Q + Trigger.com CD4047BC AC Electrical Characteristics TA = 25°C.(Note 5) Symbol tPHL. tPLH tPHL. tFCL CIN Typ Max Units Propagation Delay Time Astable. .fairchildsemi. 5 www. Rise and VDD = 5V 15 µs Fall Time VDD = 10V 5 µs VDD = 15V 5 µs 7. tPLH tPHL.5 pF Average Input Capacitance Any Input 5 Note 5: AC Parameters are guaranteed by DC correlated testing. Astable to Q. input tr = tf = 20 ns. Q + Trigger. tPLH tPHL. Q.

fairchildsemi. Q. Q and Osc Out Period Accuracy vs Temperature Astable Mode Operation A R 2 µs A . Q. Q A 1000 kHz B C R Typical Q.CD4047BC Typical Performance Characteristics Typical Q.com C 22k Typical Q.2M 1000 pF Typical Q and Q Pulse Width Accuracy vs Temperature Monostable Mode Operation C tM C 22k 10 pF B 7 µs 22k 100 pF C 60 µs 220k 100 pF 550 µs 220k 1000 pF 10 pF A 100 kHz 22k 100 pF 10 kHz 220k 100 pF 1 kHz 220k 1000 pF D 6 R 2 µs 22k www.2M 1000 pF tM f Q. Pulse Width Accuracy vs Supply Voltage Monostable Mode Operation C 22k 10 pF 100 kHz 22k 100 pF 10 kHz 220k 100 pF D 1 kHz 220k 1000 pF E 100 Hz 2. Q 1000 kHz B C D R 10 pF B 7 µs 22k 100 pF C 60 µs 220k 100 pF D 550 µs 220k 1000 pF E 5.5 ms 2. Osc Out Period Accuracy vs Supply Voltage (Astable Mode Operation) f Q.

fairchildsemi.CD4047BC Timing Diagrams Astable Mode Monostable Mode Retrigger Mode 7 www.com .

fairchildsemi.com 8 . JEDEC MS-120.150” Narrow Package Number M14A www.CD4047BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC). 0.

and (c) whose failure device or system. can be reasonably expected to result in a significant injury to the www. to perform when properly used in accordance with instructions for use provided in the labeling. JEDEC MS-001. or (b) support or sustain life. (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body.com user. As used herein: 2.300” Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.14-Lead Plastic Dual-In-Line Package (PDIP). A critical component in any component of a life support 1. or to affect its safety or effectiveness. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich. no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 0. Fairchild does not assume any responsibility for use of any circuitry described.fairchildsemi. CD4047BC Low Power Monostable/Astable Multivibrator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) .

.This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.