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Intel 8086 Microprocessor

1.0

Introduction

The Intel 8086 high performance 16-bit CPU is available in three clock rates: 5, 8 and 10 MHz. The CPU is
implemented in N-Channel, depletion load, silicon gate technology (HMOS-III), and packaged in a 40-pin
CERDIP or plastic package. The 8086 operates in both single processor and multiple processor configurations to
achieve high performance levels. It is an example of a general purpose microprocessor with unique approach to
architecture.
Some of i86 features are:

1.1

The use of instruction pipelining to increase throughput.

Flexible addressing capability that minimises the time required in complex data manipulation.

Ability to specify any register or memory location as the destination for the result of mathematical
operation.

Increasing its access ability from 64Kb to 1Mb of physical memory.

The 8086 architecture

The internal functions of the 8086 processor are partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure 1.
These units can interact directly but for the most part perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and
store, and address relocation. This unit also provides the basic bus control. The overlap of instruction prefetching provided by this unit serves to increase processor performance through improved bus bandwidth
utilization. Up to 6 bytes of the instruction stream can be queued while waiting for decoding and execution.
The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently.
Whenever there is space for at least 2 bytes in the queue, the BIU will attempt a word fetch memory cycle. This
greatly reduces ``dead time'' on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from
which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for
example), the first byte into the queue immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes
results to the BIU for storage. See the Instruction Set description for further register set and architectural
descriptions. Figure 2 gives a simplified layout of the i86 microprocessor.

1.2

Summary of 8086 microprocessor system


1.2.1

The Execution unit

(EU) is used mainly to execute instructions. It contains a circuit called the arithmetic and logic unit (ALU). The
ALU performs arithmetic (+, - , *, /) and logic (AND, OR, NOT) operations. The data for operations are stored
in circuit called Registers. A register is like a memory location except that we normally refer to it by a name
rather than address. The EU has eight registers for storing data; their names are AX, BX, CX, DX, SI, DI, BP,
SP and FLAGS register.

1.2.2

Bus interface unit (BIU)

BIU facilitates communication between the EU and memory or I/O circuits. It is responsible for transmitting
address, data, and control signals on the buses. Its registers are named CS, DS, ES, SS, IP; they hold addresses
of memory locations. The IP contains the address of next instruction to be executed by the EU.

1.2.3

The EU and the BIU

Are connected via an internal bus and they work together. While the EU is executing an instruction, the BIU
fetches up to six bytes of the next instruction and places them in the instruction queue. This operation is called
Instruction pre-fetch. The purpose is to speed up the processor.

Figure 1: Architectural layout

1.2.4

Memories

Memory on an Intel compatible processor is managed on three levels:


Physical
Linear (paging)
Logical (segmentation)
A program never actually operates directly on the linear or physical levels, although you will see that it is
possible to give this illusion. The linear address space is typically handled by the paging mechanism. The paging
facilities on the processor allow us to remap physical memory to suit the needs of the program running. Logical
addressing, or segmentation, allows us to separate different aspects of the program from each other, such as the
program code itself and the stack.

1.2.5

I/O Ports:

I/O devices are connected to the computer through I/O circuits. Each of these circuits contains several register
called I/O Ports. Some are used for data while others are used control commands. Like memory locations, the
I/O ports have address and they are connected to the bus system. These addresses are known as I/O address and
can only be use in input (IN) or output (OUT) instructions.

Figure 2: Simplified 8086 Microprocessor

1.3

8086 microprocessor registers

In the CPU, registers are used to store information temporarily. The information can be one or two bytes of data,
or the address of data. Figure 3 (a) shows the 8086 registers. The general-purpose registers can be accessed as
either16-bit or 8-bit registers as shown I figure 3 (b). All other registers (pointer (stack, base and instruction),
Index, segment, and stack) can be accessed as full 16-bit registers.

Figure 3: 8086 microprocessor registers

1.3.1

General purpose registers

The first letter of each general purpose register indicates its use.
AX is used for the accumulator. Can also be used as a counter during multiplication / divide operations
as well as when accessing I /O ports.
BX is used for base addressing register.
CX is used for counter loop operations.
DX is used to point out data in I/O operations. Can also be used in multiply and divide operations
The specific uses of the registers mentioned above can be changed by the programmer depending on the nature
of the program.

1.3.2

Pointer registers

Base pointer (BP) register:

used to access parameters and local variables in a procedure

Stack pointer (SP) register:

maintains the program stack. SP and BP are used to access data in the stack
segment

Instruction pointer register:

contains the address of next instruction to be executed. The instructions


reside in the code segment.

1.3.3

Index registers (SI, DI):

They are used to access data in either the data segment or the extra segment. They can also be used in
arithmetic / logical operations, pointers to data memory and string operations.

1.3.4

Segment registers (CS, DS, SS, and ES)

They are used to select designated segments of physical memory. The CS registers address points to the current
location of the code segment. DS registers address points to the current data segment. SS to stack pointer
while ES to the extra segment address.

1.3.5

The Flag Register (FR)

Figure 4 shows a 16-bit flag register sometimes referred as the status register. Although the register is 16-bit, not
all the bits are used. There are six (6) of the flags called the conditional flags, meaning that they indicate some
condition that resulted after an instruction was executed. These 6 are: CF, PF, AF, ZF, SF, and OF. All the
registers used by i86 are briefly explained below:
CF, the Carry Flag: This flag is set whenever there is a carry out, either from d7 after an 8-bit operation or
from d15 after a 16-bit data operation.
PF, the Parity Flag: After certain operations, the parity of the results low-order byte is checked. If the byte has
an even number of 1s, the parity flag is set to 1; otherwise, it is cleared.
AF, the Auxiliary Carry Flag: If there is a carry from d3 to d4 of an operation this bit is set to 1, otherwise
cleared (set to 0).
ZF, the Zero Flag: The ZF is set to 1 if the result of the arithmetic or logical operation is zero, otherwise, it is
cleared (set to 0).
SF, the Sign Flag: MSB is used as the sign bit of the binary representation of the signed numbers. After
arithmetic or logical operations the MSB is copied into SF to indicate the sign of the result.
TF, the Trap Flag: When this flag is set it allows the program to single step, meaning to execute one instruction
at a time. Used for debugging purposes.
IF, Interrupt Enable Flag: This bit is set or cleared to enable or disable only the external interrupt requests.
DF, the Direction Flag: This bit is used to control the direction of the string operations.
OF, the Overflow Flag: This flag is set whenever the result of a signed number operation is too large, causing
the high-order bit to overflow into the sign bit.

Figure 4: 8086 Flag Register

1.4

Accessing strings

Strings are accessed depending on whether the reference is to the source or the destination. The string
destination is always within the extra segment (ES) with the destination index (DI) as the offset. The string
source can reside in any of the four segments. The instruction will dictate which segment is used and hence
identify the base address to use. The source index (SI) provides the offset value.
ES (Extra segment) need to be defined within the programs so that both the DI and SI registers can be used as
offsets for ES and DS respectively.
..
ASSUME CS: CODSEG, DS: DATSEG, SS: STASEG, ES: DATSEG
MOV AX, DATSEG
MOV DS, AX
MOV ES, AX
Data variables other than the string variables appear in the data segment. Depending on the instruction, the
effective address can be calculated. The registers frequently used in the manipulation of data are BX, BP, SI,
DI. Displacements can be signed 8-bit or unsigned 16-bit values.
Strings can be loaded form memory to registers in bytes or words. They can as well be moved from a segment
to a destination segment (ES) in form of bytes or words. Storing strings from registers can be done but the
destination should always be ES.
Strings can be compared; one string residing in DS and pointed by SI while the other being in ES and pointed by
DI. Compare can be using register AL / AX with memory location in ES

String Operation Summary


Instruction
move string byte
move string word
store string byte
store string word
load string byte
load string word

Mnemonic
MOVSB
MOVSW
STOSB
STOSW
LODSB
LODSW

Destination
ES:DI
ES:DI
ES:DI
ES:DI
AL
AX

Source
DS:SI
DS:SI
AL
AX
DS:SI
DS:SI

Prefix
REP
REP
REP
REP
none
none

compare string byte


compare string word
scan string byte
scan string word

CMPSB
CMPSW
SCASB
SCASW

ES:DI
ES:DI
ES:DI
ES:DI

DS:SI
DS:SI
AL
AX

REPE/REPNE
REPE/REPNE
REPE/REPNE
REPE/REPNE

DF, the direction flag: To process operands in consecutive memory locations requires that the pointer be
incremented or decremented. DF in string operations is used to indicate if SI and DI pointers will increment or
decrement automatically. It is the job of the programmer to specify the choice of increment or decrement by
setting the direction flag high or low.
CLD ;( clear direction flag) will reset (put to zero) DF, indicating that the string instruction should increment
the pointers (SI, DI) automatically. This automatic increment is sometimes referred as auto-increment.
STD ;( set direction flag) will set (put to one) DF, indicating that the string instruction should decrement the
pointers (SI, DI) automatically.
REP prefix; The REP (repeat) allows a string instruction to perform the operation repeatedly. REP assumes that
CX holds the number of times that the instruction should be repeated. As the operation continues the CX register
is decremented until it becomes zero.
REPE/ REPNE prefix; REPE allows a string instruction to perform the operation repeatedly as long as CX is
not zero and the comparison gives equality. REPNE allows a string instruction to perform the operation
repeatedly as long as CX is not zero and the comparison gives inequality.