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# Spring 2013

Name:______________________________
I.D.:____SOLUTIONS________________

Final Exam
May 15, 2013

Problem 1

_______________

(20 pts.)

Problem 2

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(15 pts.)

Problem 3

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(20 pts.)

Problem 4

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(20 pts.)

Problem 5

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(25 pts.)

Problem 6

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(20 pts.)

Problem 7

______________

(20 pts.)

_______________

(140 pts.)

Total

**

## Show all your work (except for multiple choice problems).

Check that you have completed all parts of all problems. Do not spend all your time on
one problem, since time is limited.

**

Write solutions only on the front side of the exam sheets and only on the page associated
with the problem. Solutions given in other locations will not be graded.

***

Read and solve each problem carefully, since partial credit will be limited!

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Problem 1
Answer the following statements with T(rue) or F(alse) only.
(Do not guess, as points may be deducted for incorrect answers).
(a) Questions on combinational logic:
___T__ Limiting the fanin to gates for realizing a combinational logic function will, in
general, increase the propagation delay of the circuit.
___T__ Number zero has two representations in 1s complement system.
___F__ Finite fraction in decimal system can be always converted into finite fraction in
binary system
___T__ If a combinational logic function is realized in a two-level NOR-NOR circuit, it
cannot have static-1 hazards.
___F__ If a combinational logic function is realized in a two-level NAND-NAND circuit,
it cannot have static-1 hazards.
___T__ Any Boolean function can be implemented using only XOR gates and OR gates.
___F__ A dual of a Boolean function f can be obtained by interchanging logical AND and
logical OR operations, replacing each variable with its complement, and interchanging
logical 1 and 0 constants.
(b) Questions on sequential logic:
___F__ Given a Mealy model circuit and a Moore model circuit that realize the same
sequential system, the Mealy model circuit will usually have more states than the Moore
model.
___T__ Given a Mealy model circuit and a Moore model circuit that realize the same
sequential system, both of which use positive edge triggered D flip flops, the
corresponding Mealy model and Moore model outputs occur before and after the positive
edge of the clock, respectively.
___T___For a shift register circuit to work properly, the propagation delay through the
flip-flops must be greater than the clock cycle.
___T__ One reason that ASM chart representation is useful is that large sequential
systems (with many inputs) have state transitions that depend only on a small subset of
the inputs.
___F__ Master-Slave flip flop design can handle the transparency timing problem.
___T__ Master-Slave flip flop design can handle the logic race timing problem.
___T__ Any sequential circuit can be implemented using only JK flip-flops and 2-to-1
multiplexers.
Grading: deduct 1.4 pts for no answer (blank); deduct 2 pts for the wrong answer.

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Problem 2
(a) Draw a Karnaugh map for a completely specified function (of 4 variables) having the
following number of prime implicants:
f(A, B, C, D) has
- one prime implicant containing a single literal,
- one prime implicant containing two literals,
- one prime implicant containing three literals,
- and no other prime implicants.
(b) If this function f(A, B, C, D) is realized using minimum (two-level) NAND-NAND circuit,
does this implementation have:
- static-1 hazards?
- static-0 hazards?
(explain your answer)

SOLUTION
(a)
ab
cd

00

01

11

10

00

01

11

10

## f = A + BC + BCD (other correct solutions possible by interchanging A, B, C, D)

(b) Two-level NAND implementation cannot have static -0 hazards. Solution for f shown in (a)
has no static-1 hazards.

## Grading: (a) 10 pts, (b) 5 pts

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Problem 3
(a) Briefly (3-4 sentences) describe the difference between combinational devices: PLA, PAL,
and ROM, in terms of their implementation of Boolean functions. Which one, PLA or PAL, is
easier to program?
SOLUTION
All these devices have n inputs, m outputs, and they implement m Boolean functions of n
variables. ROM implements the truth table for these functions, whereas PAL and PLA
implement functions in SOP form. PLA implementation minimizes the total number of
product terms (for all m functions), whereas PALs minimize each function separately. So
PAL is easier to program than PLA.

(b) Show how to implement any Boolean function of 10 variables using four ROM modules (of
size 256 x 8 bits each) and a 4-to-1 multiplexer. (i.e., draw a block diagram showing how to
connect these modules, and clearly indicate/label the inputs/outputs for each module).
SOLUTION
Denote the function of 10 variables as F (x0, x1,x7, x8, x9). Then each ROM can
implement any Boolean function of 8 variables, say x0, x1,, x7. (these are address lines
for each ROM). The remaining inputs x8, x9 are forwarded to select inputs of a 4-to-1
multiplexer. The ROM outputs are forwarded to data inputs of the mux, effectively
implementing an expansion of a 10-variable function over variables x8, x9, according to
Shannons theorem. That is, the data inputs to the mux are:
I0 = F (x0,x7, 0, 0) I1=F (x0,x7, 0, 1) I2=F (x0,x7, 1, 0) I3= F (x0,x7, 1, 1)
Note that only a single output (of each ROM) is used in such an arrangement (wasteful).
A more economical implementation is to use 4 outputs of a single ROM module where each
output implements I0, I1, I2 and I3. (This solution requires a single ROM module and a
MUX)

## Grading: (a) 10 pts, (b) 10 pts

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Problem 4
Analyze the circuit implementing single input (x), single output (Z) sequential network, shown
below.
(a) Is this a Mealy or a Moore model circuit? Show the next-state equations and an output
equation for this circuit. (Ignore the asynchronous set and reset inputs to the FFs.)
(b) Assuming the initial state of the circuit is Q1 Q2 Q3 =000, construct a minimal state table for
a circuit that performs the same function as this circuit. Label your states A, B, C, etc. where A
is the initial state. (You do not have to find a circuit realizing your state table.)
Note: a minimal state table ~ state table with minimal number of states.

x
CLK

Q1

Q2
Q

CRQ

CRQ

Q3=Z

CRQ

SOLUTION
(a) This is Moore model.
The next-state equations (or the inputs to the FFs) are
Q1+ = D1 = X
Q2+ = D2 = XQ1
Q3+ = D3 = XQ2
The output equation is Z=Q3
(b) Only four states can be reached from the initial state 000. The next-state table is shown
below
Q1Q2Q3
A-000
B-100
C-010
D-101

X=0
000
010
000
010

## Grading: (a) 10 pts, (b) 10 pts

X=1
100
100
101
100

Z
0
0
0
1

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Problem 5
(a) Show the state diagram for a single-input, single-output Mealy sequence detector such that
Z=1 if and only if the input has been 1010 for the last 4 clock times. Overlapping patterns are
allowed.
(b) Show the state diagram for a single-input, single-output Mealy sequence detector such that
Z=1 if and only if the input has been 1010 for the last 4 clock times. Overlapping patterns are not
allowed.
(c) Implement the sequence detector in part (b) using D flip-flops and one-hot state assignment.
(implementation means showing flip-flop input equations and an output equation)
Example:
Input X
Out Z(a)
Out Z(b)

1101011101010100
0000100000101010
0000100000100010

SOLUTION
(a)
1
10
101
00

A
B
C
D

X=0
B,0
D,0
B,1
D,0

1
A,0
C,0
A,0
A,0

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(b)
1
10
101
00 or 1010

A
B
C
D

X=0
B,0
D,0
D,1
D,0

1
A,0
C,0
A,0
A,0

(c) Using one-hot state assignment, we need four D flip-flops (one for each state). Label the
states A, B, C, and D, and we have the following flip-flop input equations and output equation
A+ = DA = AX +CX +DX
B+ = DB = AX
C+ = DC = BX
D+ = DD = BX +CX +DX
Z = CX
Grading: (a) 8 pts, (b) 8 pts (c) 9 pts
Note: answers with redundant states will be given full credit if the answers satisfy the problem
specifications.

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Problem 6
(a) Show the state table or a state diagram for a Moore FSM with one input X and two outputs Y
and Z. The FSM counts the number of times X is 1 and divides this number by 4, presenting the
current remainder on the outputs Y and Z in binary. (Y is the most significant bit.)
Example: X = 0111101..
Y =? 0011000..
Z =? 0101001..
SOLUTION
X
State
A
B
C
D

0
A
B
C
D

1
B
C
D
A

YZ
00
01
10
11

Note: this is a modulo-4 counter where the outputs YZ~ two bits of a counter
(b) Implement the Moore FSM in part (a) using a counter shown below.

Use two least significant bits A1A0 as outputs YZ, and apply control inputs UP=X and
DOWN=0
Grading: (a) 10 pts, (b) 10 pts
Note: answers with redundant states will be given full credit if the answers satisfy the problem
specifications.

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Problem 7
ASM chart for Add-Shift control of a binary multiplier (discussed in class) has inputs St, M, K,
and outputs Done, Load, Ad, Sh.
(a) Using this ASM chart (shown below) derive the next-state equations and output equations.
Use straight binary state assignment to encode states.
(b) Assuming this ASM chart is implemented using a 2-bit register and a ROM, what is min size
ROM needed?
(c) Can this ASM chart be implemented using a single 16R4 PAL module (with no extra logic)?
This sequential PAL (as discussed in class) has 8 external inputs, 4 input/output terminals and
four D flip-flops. Its AND array can implement up to 8 product terms, so that each next-state
equation can have up to 8 product terms. Briefly explain your answer (YES or NO).

SOLUTION
Inputs St, M, K; outputs Done, Load, Ad, Sh. This system has 3 inputs, 4 outputs and 4 states.
Label the state variables AB. Using straight binary assignment for states, the equations can be
obtained directly from the ASM chart:
(a) Output equations
Done = AB
Load = ABSt
Ad = ABM
Sh = ABM + AB
Next state equations
A+ = ABM + ABMK + ABK
B+ = ABSt + ABMK + ABK + ABK + ABMK = ABSt + ABM + AB

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## (b) Implementation using ROM:

since the system has 3 inputs, 4 outputs, and 2 flip-flops,
the number of ROM inputs is 3+2=5 and the number of ROM outputs is 4+2=6. So the ROM
size is 32 X 6 bits.
(c) Yes, it can be implemented using a single 16R4 PAL module, because it has 3 inputs, 4
outputs and 2 state variables. Boolean equations for the outputs and next states require less than 8
product terms.
Grading: (a) 10 pts, (b) 5 pts (c) 5 pts