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You are on page 1of 34

CHAPTER 2

CONTROL TECHNIQUES FOR MULTILEVEL

VOLTAGE SOURCE INVERTERS

2.1

INTRODUCTION

Pulse Width Modulation (PWM) techniques for two level inverters

have been studied extensively during the past decades. Many different PWM

methods have been developed to achieve the following aims; wide linear

modulation range, reduced switching loss, lesser total harmonic distortion in

the spectrum of switching waveform, easy implementation, less memory

space and computation time on implementing in digital processors for the

proposed work. The two most widely used PWM schemes for multi-level

inverters are the carrier based PWM (sine-triangle PWM or SPWM)

techniques and the space vector based PWM techniques. These modulation

techniques are extensively studied and compared for the performance

parameters with two level inverters.

The SPWM schemes are more flexible and simple to implement, but

the maximum peak of the fundamental component in the output voltage is

limited to 50% of the DC link voltage and the extension of the SPWM

schemes into over-modulation range is difficult. In SVPWM schemes, a

reference space vector is sampled at regular intervals for determination of the

inverter switching vectors and their time durations, in a sampling interval. A

space phasor based PWM scheme for multi-level inverters use only the

instantaneous amplitudes of reference phase voltages. The SVPWM scheme

20

range, using only the instantaneous amplitudes of reference phase voltages.

In the recent past the multilevel power converters have drawn a

tremendous interest in the field of high voltage and high power applications

field in industries. The multilevel inverter approach allows the use of high

power and high voltage electric motor drive systems. Using the multilevel

inverter concept, a divide and conquer approach allows more flexibility and

control over the discrete components that makeup the system. In the

researches on multilevel inverters, their corresponding PWM control

strategies are the emerging research areas.

In high power and high voltage applications, the two level inverters,

however, have some limitations in operating at high frequency mainly due to

switching losses, dv/dt and di/dt stresses in power semiconductor devices and

constraint of the semiconductor power device ratings. For high voltage

applications two or more power devices can be connected in series to achieve

the desired voltage ratings and in parallel to achieve the current ratings.

Multilevel inverters can increase the power by (m-1) times than that of two

level inverter through the series connection of power semiconductor devices.

This research focuses on the different control strategies and a suitable

modulation strategy is selected based on the outputs obtained through the

simulations on the MATLAB SIMULINK software environment.

2.2

The control techniques for the multilevel voltage source inverter are

Pulse Width Modulation (SHEPWM) and Optimized Harmonics Stepped

Waveform (OHSW). PWM can be classified into open and closed loop as

discussed by Carrara et al (1992).

21

few different supplementary names in relation with the triangular carrier

waveforms and are as shown in Figure 2.1. Symmetrical

triangular carrier was

SPWM,

when

SPWM, when the initial slope of triangular carrier signal was infinite, as

shown in Figure 2.1 (b). Trailing edges SPWM, when

slope

of

triangular

carrier

signal

was

the

infinite,

trailing

as

shown

edge

in

(a)

Figure 2.1

(b)

(c)

carrier, c) Trailing edge SPWM carrier

relationship with the position of the carrier signal to the modulation wave.

Synchronous SPWM, both signals were synchronous with each other if the

carrier frequency is a multiple of the sine wave frequency (fs = k*fm).

Asynchronous SPWM, both signals

Based on the applications of PWM signals to multilevel inverters,

the multilevel sinusoidal PWM can be classified according to carrier and

modulating signals as shown in Figure 2.2.

22

Sinusoidal Pulse

Width Modulation

Modulating Signal

Carrier Signal

Pure Sinusoidal

Phase Disposition

Third Harmonic

Injection

Phase Opposition

Disposition (POD)

Dead Band

Alternate POD

Other Techniques

Hybrid (H)

Super Imposed

Carrier

2.3

Multicarrier PWM techniques entail the natural sampling of a single

output frequency of the inversion system, through several carrier signals

typically being triangular waveforms of higher frequencies of several kilo

Hertz discussed by McGrath et al (2002) and Samir Kouro et al (2008). They

can be categorized as follows

23

2.3.1

This technique requires each of the (m 1) carrier waveforms, for

alternately as shown in Figure 2.3. The most significant harmonics are

centered as sidebands around the carrier frequency fc and therefore no

Magnitude (pu)

Time (Seconds)

2.3.2

The carrier waveforms are all in phase above and below the

zero

reference value however, there is 1800 phase shift between the ones above and

below zero respectively as shown in Figure 2.4. The significant harmonics,

once again, are located around the carrier frequency fc for both the phase and

line voltage waveforms. The three disposition PWM techniques that are

APOD, PD and POD generate similar phase and line voltage waveforms.

Furthermore, for all of them, the decision signals have average frequency

much lower than the carrier frequency.

24

M agnitude (pu)

Time (Seconds)

2.3.3

Hybrid (H)

This technique, as mentioned earlier, combines the previously

presented ones (disposition) and the well known phase shifted multicarrier

technique. The bands used for modulation are only two, however, each time

the level of the power converter is increased, and more triangular carriers are

introduced and phase shifted accordingly. The two carriers above zero have

the same peak to peak value and the same frequency fc. However, there is an

1800 phase shift between them. The same applies for the two carriers below

zero. In the case that the number of converter levels is higher, the carriers are

phase shifted accordingly, that is 1200 for a 7 level system and 900 for a 9

level system and so on and so forth.

It is important to note that the significant harmonics are

concentrated around multiples of (m - 1)/2 of the carrier frequency fc. For

instance, for a 5-level converter, the harmonics are located around 2fc, for a 7

level around 3fc and for a 9 level around 4fc. The gap between the

fundamental and the first significant harmonics increases accordingly as

shown in Figure 2.5.

Magnitude (pu)

25

Time (Seconds)

2.4

MODULATING SIGNAL

Sinusoidal PWM can be classified according to the modulating

PWM (THIPWM) and Dead Band PWM (DBPWM) by Salmon et al (2008),

Zhong Du et al (2008) and Zhou and Wang (2002). Sinusoidal PWM is the

most widely accepted PWM technique, where a triangular wave is compared

with a sinusoidal reference known as the modulating signal, shown in

Magnitude (pu)

Figure 2.6.

Time (Seconds)

26

2.4.1

A method to improve the gain of the pulse width modulator in a

from conventional sinusoidal PWM with the addition of a 17% third harmonic

component to the sine reference waveform as shown in Figure 2.7. The

hardware implementation of this technique is straightforward. It should be

noted that the 15% increase in gain over the SPWM technique is achieved at

the expense of introducing third harmonics on the line to neutral waveforms.

However for a balanced load with a floating neutral point, third harmonic

current cannot flow and therefore third harmonic voltages are not present on

the line to line waveforms. Although, the above mentioned switching patterns

for PWM converters provide increased gain compared with the conventional

SPWM technique, they also imply the reference or modulating waveforms

have to be continuous regardless of their shape.

As a result they do not provide any reduction in switching frequency

compared with the SPWM. For third harmonic injection PWM, the reference

waveform is defined as f(,t) = 1.15Ma sin(ot)+0.19 Ma sin(3ot); 0 ot

2 Where, Ma is the modulation index ratio. The zero sequence voltage can

be expressed as,

(2.1)

Magnitude (pu)

Time (Seconds)

;

27

fixed common mode voltage, is added to the reference phase voltage

throughout the duration range. It has been shown that this common mode

addition will not result in a SVPWM like performance, as it will not centre

the middle inverter vectors in a sampling interval. The common mode voltage

to be added in the reference phase voltages, to achieve SVPWM like

performance, is a function of the modulation index for multilevel inverters.

A SVPWM scheme based on the above principle has been

presented in Boys et al (1990), where the switching time for the inverter legs

is directly determined from sampled phase voltage amplitudes. This technique

reduces the computation time considerably more than the conventional

SVPWM techniques do, but it involves region identification based on

modulation indices. While this SVPWM scheme works well for a three-level

PWM generation, it cannot be extended to multilevel inverters of levels

higher than three, as the region identification becomes more complicated. A

carrier based PWM scheme has been presented Celanovic et al (2001), where

sinusoidal references are added with a proper offset voltage before being

compared with carriers, to achieve the performance of a SVPWM. The offset

voltage computation is based on a modulus function depending on the DC

link voltage, number of levels and the phase voltage amplitudes. The

implementation details and the operation of the proposed method in the over

modulation region remain unaddressed.

The objective of this work is to present an implementation scheme

for PWM signal generation for multilevel inverters, similar to the SVPWM

scheme, for the entire range of modulation indices including over modulation.

The PWM switching times for the inverter legs are directly derived from the

sampled amplitudes of the reference phase voltages. The SVPWM switching

pattern generation is not realized with offset voltage computation from a

28

signal is to generate the SVPWM pattern from only the sampled amplitudes of

reference phase voltages. The proposed SVPWM signal generation does not

involve checks for region identification, as in the conventional SVPWM

scheme presented. Also, the algorithm does not require either sector

identification or look up tables for switching vector determination as are

required in the conventional multilevel SVPWM schemes. Thus the scheme is

computationally efficient when compared to conventional multilevel SVPWM

schemes, making it superior for real time implementation.

The proposed SVPWM algorithm can easily be extended to any

multilevel inverter configurations. For experimental verification of the

proposed SVPWM scheme, we are using a five level inverter of cascaded

multilevel inverter configuration.

2.5

The two most widely used PWM schemes for cascaded multilevel

inverters are the carrier-based sine-triangle PWM (SPWM) technique and the

space vector PWM (SVPWM) technique. These modulation techniques have

been extensively studied and compared for the performance parameters with

two-level inverters in Holtz (1992). The SPWM schemes are more flexible

and simpler to implement, but the maximum peak of the fundamental

component in the output voltage is limited to 50% of the DC link voltage in

Li Li et al (2000) and the extension of the SPWM schemes into the overmodulation range is difficult. In SVPWM schemes, a reference space vector is

sampled at regular intervals to determine the inverter switching vectors and

their time durations, in a sampling interval.

The SVPWM scheme gives a more fundamental voltage and better

harmonic performance compared to the SPWM schemes. The maximum peak

29

vector modulation is 15% greater than with the sine triangle modulation

scheme. But the conventional SVPWM requires sector identification and look

up tables to determine the timings for various switching vectors of the

inverter, in all the sectors by Subrata et al (2003). This makes the

implementation of the SVPWM scheme quite complicated. A SVPWM

scheme, extending the modulation range into the over modulation range, has

been presented by Holtz et al (1993), in which extensive offline computations

and look up tables are required, to determine the modified reference vector, in

the over modulation range, extending up to six-step operation. It has been

shown that, for two level inverters, a SVPWM like performance can be

obtained with a SPWM scheme by adding a common mode voltage of suitable

magnitude, to the sinusoidal reference phase voltage.

A simplified method, to determine the correct offset times for

centering the time durations of the middle inverter vectors, in a sampling

interval, is presented by Khambadkone et al (2002) and Holmes (1992), for

the two-level inverter. The inverter leg switching times are calculated directly

from the sampled amplitudes of the reference three-phase voltages with

considerable reduction in the computation time.

The SPWM technique, when applied to multilevel inverters, uses a

number of level shifted carrier waves to compare with the reference phase

voltage signals. The SVPWM for multilevel inverters involves mapping of the

outer sectors to an inner sub hexagon sector, to determine the switching time

duration, for various inverter vectors. Then the switching inverter vectors

corresponding to the actual sector are switched, for the time durations

calculated from the mapped inner sectors. It is obvious that such a scheme, in

multilevel inverters, will be very complex, as a large number of sectors and

inverter vectors are involved. This will also considerably increase the

30

A modulation scheme is offered, where a fixed common mode

voltage is added to the reference phase voltage throughout the modulation

range. It has been shown that this common mode addition will not result in a

SVPWM like performance, as it will not centre the middle inverter vectors in

a sampling interval. The common mode voltage to be added in the reference

phase voltages, to achieve SVPWM like performance, is a function of the

modulation index for multilevel inverters. A carrier based PWM scheme has

been presented, where sinusoidal references are added with a proper offset

voltage before being compared with carriers, to achieve the performance of a

SVPWM. The offset voltage computation is based on a modulus function

depending on the DC link voltage, number of levels and the phase voltage

amplitudes.

In the SPWM scheme for two level inverters, each reference phase

voltage is compared with the triangular carrier and the individual pole

voltages are generated, independent of each other.

A novel method is developed to obtain an equivalent SVPWM

pulses for the proposed multilevel inverter from the conventional SPWM. The

offset voltage is obtained as shown in Figure 2.8.

31

phase voltage in linear modulation, a common mode voltage, Voffset1, is added

to the reference phase voltages where the magnitude of Voffset1 is given by,

Voffset1= - (Vmax+Vmin)/2

(2.2)

Where,

Vmax =

Maximum

magnitude

of

the

three

sampled

Vmin =

phase voltages, in a sampling interval.

i.e. Vmax =

max (Van,Vbn,Vcn)

Vmin

min (Van,Vbn,Vcn)

active inverter switching vectors being centered in a sampling interval,

making the SPWM technique equivalent to the SVPWM technique.

Equation (2.2) is based on the fact that, in a sampling interval, the reference

phase which has lowest magnitude (termed the min phase) crosses the

triangular carrier first and causes the first transition in the inverter switching

state. While the reference phase, which has the maximum magnitude (termed

the max-phase), crosses the carrier last and causes the last switching transition

in the inverter switching states in a two level SVPWM scheme.

Figure 2.9

PWM scheme

32

from the (max phase and min phase) sampled reference phase voltage

amplitudes in a two level inverter scheme. The SPWM technique for

multilevel inverters, involves comparing the reference phase voltage signals

with a number of symmetrical level shifted carrier waves for PWM

generation. It has been shown that for an n level inverter, ( n-1) level shifted

carrier waves are required for comparison with the sinusoidal references.

Because of the level shifted multi carriers as shown in Figure 2.9, the first

crossing (termed the first cross) of the reference phase voltage cannot always

be the min phase.

Similarly, the last crossing (termed the third cross) of the reference

phase voltage cannot always be the max phase. Thus the offset voltage

computation, based on Equation (2.2) is not sufficient to centre the middle

inverter switching vectors, in a multilevel PWM scheme during a sampling

period Ts shown in Figure 2.10. In this, a simple technique to determine the

offset voltage (to be added to the reference phase voltage for PWM generation

for the entire modulation range) is presented, based only on the sampled

amplitudes of the reference phase voltages.

The proposed scheme determines the sampled reference phases. The

obtained reference phase which crosses the triangular carrier first is defined as

first cross and the subsequent crosses are referred as second cross and the

third cross. Once the first cross and third cross phase is identified, the

principle of offset calculation given by Equation (2.2) is used to determine the

second cross. The same can be adopted for the multilevel SVPWM generation

scheme. This technique presents a simple way to determine the time instants

at which the three reference phases crosses the triangular carriers.

33

cross,

Tb

cross

and Tc

cross

during

These time instants are sorted to find the offset voltage to be added

to the reference phase voltages for SVPWM generation for multilevel

inverters for the entire linear modulation range, so that the middle inverter

switching vectors are centered (during a sampling interval), as in the case of

the conventional two level SPWM scheme.

2.5.1

Figure 2.9 shows a reference voltage and four triangular carriers

used for PWM generation for a five level inverter. The modified reference

phase voltages are given by,

*

VXN

= VXN + Voffset1 , X=A, B, C

(2.3)

phase voltages during the current sampling interval. The reference phase

voltages are equally spaced between the four carriers as shown in Figure 2.9,

for a five-level inverter. For modulation indexes less than 0.433 (half of the

maximum Modulation Index in the linear range of modulation for a five level

34

inverter), the reference phase voltage spans inner two carriers. For modulation

indexes higher than 0.433, the reference phase voltages expand into the outer

carrier regions. The addition of Voffset1, obtained from Equation (2.2), to the

reference phase voltage ensures that the modified reference voltages always

remain within the carrier regions through the linear modulation range.

The reference phase voltages cross the triangular carriers at different

instants of a sampling period Ts shown in Figure 2.10. Each time a reference

phase voltage crosses the triangular carrier, it causes a change in the inverter

state. The phase voltage variations and their time durations are shown in

Figure 2.10. The sampling time interval Ts, can be divided into four time

intervals T01, T1, T2 and T03. T01 and T03 are defined as the time durations for

the start and end inverter switching vectors respectively in a sampling time

interval Ts. T1 and T2 are defined as the time durations for the middle inverter

switching vectors, in a sampling time interval Ts. It should be noted from

Figure 2.10 that the middle switching vectors are not centered in a sampling

interval Ts. So an additional offset (offset2) needs to be added to the reference

phase voltages, so that the middle inverter switching vectors can be centered

in a sampling interval.

The time duration, at which the A phase crosses the triangular

carrier, is defined as Ta cross. Similarly, the time durations, when the B phase

and C phase cross the triangular carrier, are defined as Tb

cross

and Tc

cross

the carrier region C1 while the B phase and C phase are in carrier region C2,

the time duration, Ta cross, (measured from the start of the sampling interval)

at which the A phase crosses the triangular carrier is directly proportional to

the phase voltage amplitudes, VAN . The time duration Tb cross at which the B

4

35

time duration, Tc cross, at which the C phase crosses the triangular carrier and

it is proportional to V*CN +

Ta_cross = V*AN +

VDC

. Therefore

4

VDC

= T*as

4

(2.4)

V T

4 VDC

(2.5)

V T

4 VDC

(2.6)

Where,

T*as, T*bs, T*cs are the time equivalents of the phase voltage

magnitudes.

The proportionality between the time equivalents and corresponding

voltage magnitudes is defined as follows:

VDC

*

4 = V AN

Ts

T*as

VDC

*

4 = V BN

Ts

T*bs

VDC

*

4 = V CN

Ts

T*cs

(2.6a)

36

Figure 2.11, shows the situation, where the reference phase voltages

span the entire carrier region for a five level inverter scheme. The time

durations, at which the reference phase voltages cross the carrier, can be

determined similarly. As shown in Figure 2.11, Tacross is proportional to

VDC

VDC

*

*

V AN whereas Tbcross is proportional to V BN +

and Tccross is

4

2

proportional to V*CN + DC .

4

cross,

Tb

cross

and Tc

cross

during

switching interval TS

Therefore, from Equation.(2.5)

Tfirst cross= min (Tx cross),

Tsecond cross = mid (Tx cross),

Tthird cross = max (Tx cross),

(2.7)

X= a, b, c

cross,

Tb

cross

and Tc

cross

time durations

obtained above are used to centre the middle switching vectors, as in the case

of two level inverters, in a sampling interval Ts. The time duration at which

the reference phases cross the triangular carriers for the first time, is defined

37

as Tfirst cross. Similarly, the time durations, at which the reference phases cross

the triangular carriers for the second and third time, are defined as, Tsecond cross

and Tthird cross respectively, in a sampling interval Ts. The time durations Tfirst

cross,

Tsecond

cross

and Tthird

cross

interval Ts.

The time durations for the start and end vectors are T01 = Tfirst cross,

T03 = Ts - Tthird cross respectively as shown in Figure 2.10. The middle vectors

are centered by adding a time offset Toffset2 to Tfirst cross, Tsecond cross and Tthird

cross.

The time offset Toffset2 is determined as follows. The time duration for the

Tmiddle = Tthird cross -Tfirst cross

(2.8)

T0 =Ts - Tmiddle

(2.9)

T0/2 = Tfirst cross + Toffset2

(2.9a)

Therefore,

Toffset2 = T0/2 -Tfirst cross

(2.10)

The addition of the time Toffset2 to Ta cross, Tb cross and Tc cross gives the

inverter leg switching times Tga, Tgb and Tgc for phase A, B and C,

respectively.

38

Tga = Ta cross+Toffset2

Tgb = Tb cross+Toffset2

(2.11)

Tgc = Tc cross+Toffset2

The traces of different timing signals, for the proposed PWM

scheme, are shown in Figure 2.13 and Figure 2.14, for a five level PWM

generation. The traces of Ta cross for various modulation indices are shown in

Figure 2.12. The traces of Tfirst

cross,

Tsecond

cross

first cross,

Tg

and Tthird

second cross

cross

are shown in

and Tg

third cross

are

shown in Figure 2.13b. It can be seen from Figure 2.13b, that the time

durations for the start vector (Tg first cross) and for the end vector (Ts - Tg third cross)

are equal. Thus the middle vectors are always centered, in a sampling time

interval Ts. The corresponding traces of the total offset, Tas* + Toffset2, added to

the sinusoidal reference phase voltage to make the SPWM equivalent to the

SVPWM is shown in Figure 2.14.

2.5.2

The following are the steps involved to find out the switching

Step: 1

the

Step: 2

Determine the time equivalents of phase voltages, i.e. Tas, Tbs and

Tcs.

Step: 3

Find Toffset1 using Tmax and Tmin, Tmax, Tmin are the maximum and

minimum of Tas, Tbs and Tcs.

39

Step: 4

Determine Teffective.

Step: 5

Step:6

cross

and

Tthird cross.

i.

ii.

remaining one is Tsecond cross.

Step:7

phase according to the phase which determines Tfirst cross,Tsecond cross

and Tthird cross.

Step: 8

40

(a)

(b)

Figure 2.13 Traces of Tfirst cross, Tsecond cross and Tthird cross (a) Non-centered

time duration for middle vectors (b) Centered time duration

Voltage (V)

Time (S)

index=0.85

41

2.6

Table 2.1 Comparison of SPWM and SVPWM

S.NO

SPWM

Proposed SVPWM

or current

2

supply voltage

supply voltage

Vdc

4

DC utilization of SPWM is

low

SPWM

quantities separately

equation known as space vector

Independent on number of

modulation modes

modes

42

2.7

SIMULATION

OF

CONTROL

TECHNIQUES

FOR

Figure 2.15 shows the MATLAB/SIMULINK model for five level

PSPWM based cascaded multilevel inverter. In this model the two H bridge

inverters are connected in series in order to form five level cascaded

multilevel inverters.

The two level carrier based PWM techniques was extended to

multilevel inverters by making use of several triangular carrier signals and

one reference signal per phase. For m level inverter, (m-1) carriers with the

same frequency fc and same peak to peak amplitude Ac are disposed such that

the bands they occupy are contiguous. The reference is continuously

compared with each of the carrier signals. If the reference signal is greater

than a carrier signal, then the active device corresponding to that carrier is

switched ON, and if the reference signal is less than a carrier signal, then the

active device corresponding to that carrier is switched OFF.

Figure 2.15(b)

zero sequence voltage is added to pure sinusoidal modulating wave.

2.7.1

Simulation Results

A comparison between different carrier techniques for a 5 level

carrier and modulating signal frequencies are 5 kHz and 50 Hz respectively.

For the PSPWM and THIPWM technique, Figure 2.15(a) and 2.15(b) indicate

the multilevel SIC carrier based control technique which shows the carrier

bands. Modulation waveform and inverter output waveforms are obtained for

ma=1, mf =20.

43

(a)

(b)

Figure 2.15 MATLAB/SIMULINK model for 5-level cascaded multilevel

Inverter (a) PSPWM (b) THIPWM

44

2.7.2

The SVPWM is implemented in the MATLAB/SIMULINK

environment based on the equations from Equation 2.1 to Equation 2.11. The

individual blocks are modeled with the corresponding equations and are

linked together to obtain the simulation results. The blocks used to simulate

the SVPWM control technique for three phase cascaded multilevel inverter

are shown in Figure 2.16.

inverter with the proposed SVPWM

The offset voltage waveforms are derived based on the equations for

offset voltage and from the sampled intervals of phase voltages. The offset

voltages are obtained for individual crosses like first_cross, second_ cross and

etc., The obtained offset voltage waveform for three phase five level cascaded

multilevel inverter are as shown in Figure 2.17. This offset voltage waveform

45

is for the first_cross in similar way the other offset voltages are obtained for

Magnitude (V)

every cross.

Time (Seconds)

After obtaining the offset voltages for individual crosses the time

equivalents are obtained with the addition of the time, Toffset2 to Ta cross, Tb cross

and Tc cross gives the inverter leg switching times Tga, Tgb and Tgc for phases A,

B and C, respectively which is shown in Figure 2.19. This switching time

intervals are given to the respective phase power switches and the effective

voltages for all the phases are obtained and the same is captured with the aid

of scope block in the MATLAB/SIMULINK editor and the same is shown in

Figure 2.18. The respective phases A, B, C are as shown in red, blue and

green respectively.

The phase sequence for the output effective voltage waveform is A,

B and C. The output waveform coincides with the desired pattern which

confirms that the respective switches are turned ON and OFF at correct

instances without any crossovers.

Magnitude (V)

46

Time (Seconds)

Magnitude (V)

Time (Seconds)

Figure 2.19 Four triangular waveforms and the time equivalents of the

phase voltages

To obtain the switching pulses for the five level cascaded

Configurations, the (n-1) triangular carrier waveforms are chosen and the

same is shown in Figure 2.19. The carrier waveforms and their respective

time equivalents obtained for the respective phase voltages are shown in

Figure 2.19. The same pattern is obtained for different time instances for

47

sequence is presented. The output phase voltage waveforms obtained with the

aid of the derived pulses from the modelling is shown in the Figure 2.20. The

Figure 2.21 shows the line voltage waveforms for the modelled system with

Magnitude (V)

the SVPWM control algorithm for three phase five level inverter.

Time (Seconds)

Magnitude (V)

Time (Seconds)

48

2.7.3

Results

The simulation is done for all the discussed control techniques for

analyzed. The parameters such as output voltage level, various levels of THD

obtained for individual algorithm are captured at the required instances and

the same is plotted for the study of the particular control algorithm and the

selection of an suitable algorithm is done. The output line voltage levels of the

simulated system for different harmonics order is shown in Figure 2.22. Here

the output is plotted for all the control techniques employed for simulation.

Among these of these the APOD and SVPWM give the better fundamental

voltage magnitude when compared with the other techniques.

The plot also reveals that the lower order harmonics are also less for

these two techniques when compared to other control algorithms for

multilevel configuration. As the harmonics order increases the magnitude of

output harmonics is reduced significantly. At higher order harmonics the

APOD and SVPWM techniques give better results for the elimination of the

lower order harmonics. Even though the higher order components present at

the output can be easily filtered out with least values of L and C components

and the losses on the filtering.

techniques

49

output THD by varying the modulation index for the different techniques

adopted for simulation of the multilevel inverter configuration. The MI is

varied from 0.1 to 1 and the output THD levels are captured and the same is

plotted as shown in Figure 2.23.

The percentage THD is very higher for lower MI and it is almost

seventy percentage when the MI = 0.1 and slightly differs for different control

techniques. As MI is increased progressively the output THD levels reduced

considerably for specific control techniques. As far as the output THD levels

are concerned the SVPWM technique is showcasing the better performance

when compared to the other control techniques adopted for simulation. From

the Figure 2.23 it is evident that SVPWM gives the least THD level when the

MI is greater than 0.866.

different control technique

The current drawn by the load is noted for different modulation

indices for the different control techniques as shown in Figure 2.24. As the

50

MI increases the current drawn by the load is increased but it differs for

different control techniques. At MI is 0.8, all the control techniques almost

draws the same load current but for higher MI the few control strategies gives

the better results in terms of the magnitude of the current. If the current level

decreases the losses on the system will get decreased which is the indication

of the higher magnitude of fundamental component, which is a desired

outcome for the control techniques. The magnitude of the current is low at the

higher modulation index for certain control techniques (for APOD, PS and

SVPWM) as indicated in Figure 2.24. Among these proposed control

techniques the PS, APOD and SVPWM. The SVPWM gives at the better

performance in all the operating conditions.

technique

The graphs were plotted for output percentage THD for different

control techniques as shown in Figure 2.25. From the graph it is inferred that

for the given MI the output THD levels get differed based on the control

technique. As far as THD levels are concerned the control techniques such as

APOD, PD,SIC and SVPWM, only SVPWM shows the better performances,

51

of which the other techniques like PD and SIC are not satisfied in terms of

output voltage magnitude and load currents.

Even though some control techniques are showcasing the similar

results in certain aspects, it should be noted for the flexibility in

implementation for different levels, consistency in performance with slight

modifications in load parameters. Based on these, SVPWM control technique

is considered as a superior one for the hardware implementation with the

latest digital processors.

2.8

CONCLUSION

The performance of any power converter depends on the modulation

modulation techniques for the two and three level inverters were implemented

but for higher level inverters. The modulation techniques are still mostly

unexplored because of large number of inverter switching states and they

increase the computational difficulties. The various modulation techniques

52

parameters were presented and elaborately discussed. The analysis is done

richly with respect to the fundamental output voltage levels, output total

harmonics distortion levels, different modulation indices for multilevel

configuration with the different control techniques.

In SVM for three phase five level inverter, five kinds of switching

states exist in each phase. The five level inverter has 53 = 125 switching

states/space vector combinations, 96 sectors, 61 locations and four layers. A

novel voltage modulation scheme of the SVPWM has been presented which

gives the performance like that of SVM techniques for cascaded multilevel

inverter. The implementation and performance of the proposed scheme yields

best results and also the centering of the middle inverter switching vectors of

the SVPWM is achieved by the addition of an offset time signal to the

inverter gating signals, derived from the sampled amplitudes of the reference

phase voltages.

The proposed SVPWM scheme covers the entire modulation range

and over-modulation too. The proposed technique does not need any sector

identification and voltage vectors as the case in conventional SVM schemes.

Complicated calculations for inverter switching vector times and look-up

tables for selecting the inverter switching vectors are also avoided in this

proposed method. This reduces the computation time required to determine

the switching times for inverter legs and memory requirement of the digital

processors making the algorithm suitable for real-time implementation. The

simulated output of the proposed method gives the least total harmonic

distortion and also the reduced losses on the power circuit.

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