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**Dan Wang, Maofeng Yang, Wu Cheng, Xuguang Guan, Zhangming Zhu, Yintang Yang
**

Institute of Microelectronics, Xidian University, Xi’an 710071, PR China Email: danwang_xdu@yahoo.cn

Abstract—This paper proposes four low power adder cells using different XOR and XNOR gate architectures. Two sets of circuit designs are presented. One implements full adders with 3 transistors (3-T) XOR and XNOR gates. The other applies GateDiffusion-Input (GDI) technique to full adders. Simulations are performed by using Hspice based on 180nm CMOS technology. In comparison with Static Energy Recovery Full (SERF) adder cell module, the proposed four full adder cells demonstrate their advantages, including lower power consumption, smaller area, and higher speed. Key words—CMOS, Full Adder, Low Power

characteristics of these newly designed full adders. The simulation and comparison of performance are illustrated in section V. Finally, the conclusion is drawn in section VI. II. PRELIMINARIES

A. Logic Equations for the Proposed Full Adders The full adder operation equations presented below can be stated as follows: given the three 1-bit inputs A, B and Cin which calculate two 1-bit outputs Sum, for sum and Cout, for carry out.

Sum = A ⊕ B ⊕ Cin

I.

INTRODUCTION

(1) (2) (3) (4)

The blooming development of Computer Science has led to the growth of integrated circuit (IC) devices. Most of the Very Large Scale IC (VLSI) applications, such as digital-signal processing and microprocessors, use arithmetic operations extensively. In addition, among these widely used operations, subtraction and multiplication are most commonly applied. The 1-bit full adder is the building block of these operation modules. Therefore, enhancing its performance is crucial to ameliorating the performance of overall modules. Meanwhile, as the widespread use of portable IC devices, such as MP3 players, mobile phones and PDAs etc., IC engineers are required to improve the performance of existing operation modules in some aspects, especially in power depletion and size. Since the battery technology available does not advance at the same rate as the microelectronics technology, IC designers have encountered more constraints: high speed, high throughput, small silicon area, and at the same time, low power dissipation. Hence, the research of establishing low power, high performance adder cells is becoming feverish. One efficient method to accomplish this task is derived from the structural level. This approach to designing and analyzing an adder cell is decomposing it into smaller modules for further analysis and improvement. In this way, an optimized full adder cell can be constructed by connecting these improved smaller modules. This paper is organized as follows: some preliminaries are presented as essential fundamentals in Section II. This part contains three logic equations relevant to 1-bit full adder and four optimized XOR and XNOR modules, using the proposed design in [1] and GDI technique in [2] respectively. In section III, four redesigned full adders based on the proposed XOR and XNOR gates are described. In section IV, authors present some

Project supported by the National Natural Science Foundation of China ( Nos. 60676009, 60776034 ) and the National Outstanding Young Scientist Foundation of China ( No. 60725415 )

Sum = A ⊕ B ⊕ Cin

Sum = (Cin i( A ⊕ B)) + (Cin i( A ⊕ B ))

Cout = ( Ai( A ⊕ B )) + (Cin i( A ⊕ B )) = ( Bi( A ⊕ B )) + (Cin i( A ⊕ B ))

B. Redesigned XOR and XNOR Gates As shown in the equations above, XOR and XNOR gates are the essential parts in full adders. The authors provide two diverse pairs of XOR and XNOR gates to improve the performance of full adders. All these gates are implemented with CMOS transistors. The obvious advantages of small transistor number and special structures make them better alternatives for future uses. The major aim of using these newly designed XOR and XNOR gates is to reduce power consumption in CMOS full adders. 1) XOR and XNOR gates using 3 transistors (3-T) Fig. 1 shows XOR and XNOR gates using 3 transistors (3-T) in [1]. Each of these two gates uses only 3 transistors and has a small delay of mere 1 transistor (1-T). However, for certain input combinations, they give bad output logic levels. We can manipulate the (W/L) ratios of PMOS and NMOS transistors to solve this problem until an acceptable logic level is restored.

Figure 1.

(a) 3-T XOR gate (b) 3-T XNOR gate

978-1-4244-2800-7/09/$25.00 ©2009 IEEE

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2) XOR and XNOR gates based on Gate-Diffusion-Input cell The Gate-Diffusion-Input (GDI) method is based on the use of a simple cell as shown in Fig. 2. One may be reminded of the standard CMOS inverter at the first glance of this circuit, but there are some important differences: (1) The GDI cell contains three inputs—G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS), and N (input to the source/drain of NMOS). (2) Bulks of both NMOS and PMOS are connected to N or P (respectively), so it can be arbitrarily biased in contrast to CMOS inverter. The basic GDI cell is shown in Fig. 2.

Figure 3. (a) GDI XOR gate (b) GDI XNOR gate

III.

THE PROPOSED LOW POWER FULL ADDERS

Figure 2. Basic Gate-Diffusion-Input cell [2]-[5]

The GDI cell with four ports can be recognized as a newly multifunctional device, which can achieve six functions with different combinations of inputs G, P and N. TABLE I. shows that simple configuration changes in the inputs G, P, and N of the basic GDI cell can lead to very different Boolean functions [5] at the output Out. Most of these functions are complex (usually consume 6-12 transistors) in CMOS, while very simple (only 2 transistors per function) in the GDI design methodology. Meanwhile, multiple-input gates can be implemented by combining several GDI cells.

TABLE I. Input

P G N

A. Full Adders Based on 3-T XOR and 3-T XNOR Gates 1) 8 transistors (8-T) full adder As shown in Fig. 4, the 8-T full adder contains three modules—two 3-T XOR gates and a 2-transistor multiplexer (2-T MUX) as shown in Fig. 6. The Sum and Cout can be obtained using (1) and (4) respectively. Owing to the appealing traits of a small number of transistors and a mere 2-transistor (2-T) delay, it can work at high speed with low power dissipation.

FUNCTIONS OF THE BASIC GDI CELL [2-5] Out Function F1 F2 OR AND MUX NOT Figure 4. 8-T full adder

B 1 B 0 B 1

A A A A A A

0 B 1 B C 0

Ai B A+ B

A+ B

Ai B

Ai B + AiC

A

2) 10 transistors (10-T) full adder As shown in Fig. 5, the 10-T full adder consists of four modules, including one 3-T XOR gate, one 3-T XNOR gate, and two 2-T multiplexers (2-T MUX). This circuit uses (3) and (4) to generate its Sum and Cout, respectively.

The XOR and XNOR gates based on GDI cells are applications of the GDI technique. As can be seen in Fig. 3, each of them requires only four transistors. Obviously, the proposed GDI XOR and XNOR gates use less transistors compared with the conventional CMOS counterparts. Due to some attractive features which allow improvements in design complexity, transistor counts, static power dissipation and logic level swing, research on GDI is becoming feverish in VLSI area. However, the GDI scheme suffers the defect of special CMOS process, specifically, it requires twin-well CMOS or silicon on insulator (SOI) process, which are more expensive than the standard p-well CMOS process. This challenges its applicability in many CMOS circuits.

Figure 5. 10-T full adder

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Figure 6. 2-T MUX [7]

B. Full Adders Based on Gate-Diffusion-Input XOR and XNOR Gates According to the logic equations mentioned above and the GDI XOR and XNOR gates in Fig. 3, full adders can be redesigned in two patterns: GDI XOR full adder and GDI XNOR full adder. Each of the two proposed full adders in Section III.B includes ten transistors. Compared to the 8-T full adder, the GDI adders may be slightly slower, since more transistors are used in GDI circuits. As is well known, the number of transistors in circuits can influence performance in many aspects, especially speed. 1) GDI XOR full adder The transistor level implementation of GDI XOR full adder is shown in Fig. 7. This full adder consists of three modules— two GDI XOR gates and a multiplexer. The Sum and Cout can be calculated using (1) and (4). In the worst case, Sum has 4-T delay while Cout has 3-T delay. However, due to the advantages of GDI cell, this circuit still can achieve its benefit of low power consumption.

Figure 8. GDI XNOR full adder

P = Ps + Pd

(5)

Usually, under the circumstance of 180nm, the static power loss is far less than its counterpart—dynamic power dissipation. Therefore, in most cases, the total power loss is approximate to dynamic power consumption, which is also considered to be related to the internal node capacitance and the probability of switching. However, we should take into account that this becomes false as we enter in the deep submicron world where the parasitics are significant. The four proposed full adder cells have less internal capacitance because of the reduced number of transistors compared to traditional full adder cells implemented by 14 and 28 transistors.

B. Short Circuit Current The short circuit current occurs when both NMOS and PMOS transistors are simultaneously active. It is the direct current passing through the supply and the ground. In all the proposed adder circuits, this short circuit current is quite low. C. Timing Response The proposed 8-T and 10-T full adder cells have the same 2-transistor delay, while for the proposed full adder cells based on GDI technique, each of the GDI adders has 4-transistor delay in its worst route. For instance, in GDI XOR full adder, when the input combination (A, B, Cin) is (1, 0, 1), the logic value of Vdd (equals to ‘1’) has to pass through two transistors (a PMOS and a NMOS) before turning on the NMOS in the following XOR gate. After the activation of this NMOS, the logic value of Gnd (equals to ‘0’) also needs to get through two NMOS transistors before getting to the Sum output. Similar situations can be met in other combinations of input and in the GDI XNOR full adder as well. Also, in Sum outputs of the 10T and GDI adder cells, there is no signal generated internally to control the selection of these multiplexers’ outputs. Instead, the input signal Cin is used to drive the multiplexers. In this way, overall delay can be reduced since Cin has full voltage swing and no extra delay.

V. SIMULATION AND COMPARISON

Figure 7. GDI XOR full adder

2) GDI XNOR full adder Fig. 8 is the GDI XNOR full adder which is another basic architecture of the application of GDI cells. This scheme also includes three modules. It contains two GDI XNOR gates and a multiplexer. In the worst route, Sum has 4-T delay and Cout has 3-T delay. The Sum and Cout can be calculated from (2) and (4) respectively.

IV. CHARACTERISTICS OF THE PROPOSED FULL ADDERS

A. Dynamic Power Total power dissipation in CMOS circuits is composed of two parts. One is static power consumption, the other is dynamic power depletion. As described in (5), where P is the total power consumption, Ps and Pd represent static power depletion and dynamic power loss respectively[7].

A. Simulation Environment The proposed XOR, XNOR gates and the four low power full adders are simulated using Hspice in Cadence Tools. All the results are obtained in 180nm CMOS process technology

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Delay product. In addition, three out of the four newly designed full adders—the 8-T and GDI series adders have very small delay at 200MHz. Meanwhile, it is evident that the static power consumption is far less than the dynamic power dissipation, as we mentioned in Section IV.A. VI. CONCLUSION In this paper, four low power full adder cells are proposed. The newly designed modules possess the merits of low power depletion, small delay, small Power-Delay product, and area saving due to lower transistor counts and special structures. The simulation results demonstrate that these four proposed full adder cells can be better alternatives in divergent fields for various uses.

Figure 9. Simulation input patterns

REFERENCES

[1] Sreehari Veeramachaneni and Hyderabad, “New improved 1-bit adder cells”, CCECE/CCGEI, Niagara Falls. Canada, May 5-7 2008, pp. 735738. Po-Ming Lee, Chia-Hao Hsu, and Yun-Hsiun Hung, “Novel 10-T full adders realized by GDI structure”, 2007 IEEE International Symposium on Integrated Circuits (ISIC-2007), pp. 115-118. Alireza Saberkari, Shahriar Baradaran Shokouhi, “A novel low-power low-voltage CMOS 1-bit full adder cell with the GDI technique”,2006 IJME-INTERTECH Conference. A. Morgenshtein, A Fish, I.A. Wagner, “An efficient implementation of D-Flip-Flop using the GDI technique”, Proc. Of ISCAS’04 Conference, Canada, pp. 673-676, May 2004. A. Morgenshtein, A. Fish, I. A. Wagner, “Gate Diffusion Input (GDI) – A Novel Power Efficient Method for Digital Circuits: A Design Methodology,” 14th ASIC/SOC Conference, Washington D.C., USA, September 2001. R. Shalem, E. John, and L. K. John, “A novel low power energy recovery full adder cell”, in Proc. IEEE Great Lakes VLSI Symp., pp.380-383, Feb. 1999 John P. Uyemura, “Introduction to VLSI Circuits and Systems,” Wiley, John & Sons, Inc., 2002.

with a 1.8V supply voltage. In order to establish an impartial simulation circumstance, authors prefer the input patterns in Fig. 9, which covers every possible inputs combination of A, B, and Cin.

[2]

B. Comparison Power consumption and working speed (frequency and delay) are yardsticks for the performance of CMOS circuits. These are listed in TABLE II. in order to compare the four proposed full adders with the SERF adder in [6].

Another important standard for CMOS circuits is PowerDelay product ( P × D ). This parameter is applied often in testing characteristics of CMOS circuits. Since, in many cases, requirements of low power and high speed cannot be accomplished simultaneously, comparisons only using these two metrics may become problematical. Please pay attention to the shaded areas which indicate the minimum value of each column. As shown in TABLE II. , the proposed GDI XNOR full adder has the minimal Power-Delay product and the lowest Pd at 200MHz (working frequency). Also, the proposed 10-T full adder possesses very small Power-

[3]

[4]

[5]

[6]

[7]

TABLE II.

COMPARISON OF THE PROPOSED FULL ADDERS WITH SERF ADDER Power consumption(W) P× D (at 200MHz) (TT) 6.1632e-16 8.4533e-17 2.2393e-16 1.4753e-17 2.4873e-15

Cell name

Ps 100MHz 200MHz

Pd 250MHz 333MHz

Delay(s) (at 200MHz)

8-T 10-T GDI XOR GDI XNOR SERF

1.432e-10 2.334e-10 8.015e-10 3.420e-10 2.592e-10

3.504e-06 6.955e-08 7.162e-07 9.586e-08 5.563e-07

3.600e-06 9.013e-08 1.384e-06 5.542e-08 2.581e-06

2.389e-06 1.274e-07 1.626e-06 8.929e-07 3.729e-06

3.750e-06 6.696e-07 2.439e-06 9.518e-07 4.928e-06

1.712e-10 9.379e-10 1.618e-10 2.662e-10 9.637e-10

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