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Bipolar IC process

The major steps in the IC bipolar process are listed in the diagram below.
Crystal growth

Wafer slicing and polishing

Buried layer

Epitaxial growth

Isolation diffusion

Base diffusion

Emitter and collector diffusion

Open contact windows

Interconnect and metallization

Separate and mount chips

2. The function of this layer is to reduce the collector resistance of the transistor. Boron is again diffused (but this time not as deeply) or implanted to forms bases and resistors. The first masking step defines the area for n+ buried layers. 3. The p-type diffusion uses boron as impurity. 5. The n-type collector is converted to p-type when the density of p-type impurities exceeds that of n-type impurities. The resulting structure is shown in the figure below. an n-type layer is grown. This is shown in the figure below. Again conversion of p-type base to n-type requires impurity compensation. islands of n-type silicon are bounded on all sides by p-type Si. n+ buried layer region. Thus. The wafer with the epitaxial layer is then oxidized at an elevated temperature in an H2O ambient. The resulting structure is shown in figure below. Isolation is achieved by applying voltages such that this p-n junction is always reverse. A second masking step defines a border completely enclosing n-type islands of silicon that are to be electrically isolated collectors of transistors. approximately 0. or 150 mm. . By epitaxial deposition. A new layer of thermal oxide is grown over the isolation areas.Wirebond connction to header Seal package Bipolar IC Fabrication Steps The starting material is a p-type single crystal silicon wafer having 5 to 20 ohm-cm resistivity and thickness of approximately several hundred micrometers. Thermal diffusion or ion implantation forms the desired heavily doped n-type. 75. The SiO2 masking layer is removed. This forms a layer of SiO 2. The third masking step defines base regions of n-p-n transistors. The diameter can be 50. The fourth photolithographic step defines n-type transistor emitters and n-type regions for low resistance contacts to collector regions.biased. as in the figure below. It is n-type single-crystal silicon 2 to 5 micro meter thick with its resistivity in the range of 0. P-type diffusion into the border areas is continued until the entire epitaxial layer has been penetrated. that is. 4. over the entire surface. exposing the entire silicon wafer surface. The SiO 2 is removed in these areas by chemical etching. The most standard size is 100 mm or about 4 inches 1. 100. as shown in the figure below.1 to 1 ohm-cm. During the epitaxial process. the n-type dopant previously introduced in the buried layer areas diffuses in all directions. Patterns of resistors are formed simultaneously in separate isolated n-type regions. (also called sub-collector). A thin layer of SiO2 is formed on all surfaces of a p-type silicon wafer by exposing it to oxygen or water vapour in an electric furnace.5 micro meters thick over the entire surface of silicon. 125.

This is necessary because there are many faulty chips after such highly complicated fabrication steps. However before finished form. The probe test is automatically carried out by contacting the pads of every chip with microelectrode probes. Metal (AI) is then deposited by vacuum evaporation. If the chip passes all test vectors. This protects the surface of the wafer from contamination. The 6thmasking step is not shown in figure. Glassivation is done using chemical vapour deposition. the ICs are in finished state. The figure below shows the contact areas (defined by 5 th mask) to collector. upto 16000 test vectors are tested for each chip of a wafer in some minutes. This process is repeated until all chips have been tested. The chip is then tested using a set of test vectors. (5 th mask) those regions where contact is to be made to the silicon are defined.6. which consist of a sequence of input voltages. base. and the remaining metal is removed. Chips that failed to pass all test vectors are marked with an ink dot. a protective passivating layer using glass is deposited over the entire wafer. An oxide is again thermally grown over the entire wafer and via photolithography. in higher yields and in better reliability. stimuli (to chip input pads) and expected output voltage responses (from chip output pads) that have been previously generated by the design engineer. A final masking step removes the above insulating layer over the pads where contacts will be made. Registration of each chip with respect to the probes is done automatically by final mechanical adjustment. and emitter. namely all outputs provide the correct results for all input stimuli then the probes are automatically stepped to the next chip position and all test vectors are applied to that chip. The photolithographic process (6th mask) is then used to define the appropriate metallization inter-connection pattern. . or glassivation. Now the IC chip undergoes a probe test. Due to computer controlled operation of wafer probe equipment. This is known as die passivation or scratch protection. Bipolar IC Manufacture Steps At this point. This added step paysoff in protection before and after packaging.

The chips are bonded to either metal headers or ceramic substrate. pins) of container with gold (or aluminium) wires is referred to as bonding. Lead Bonding and Encapsulation Connecting the pads (metallised contact areas) to the terminal (that is. the entire wafer is broken into individual chips. For this purpose small-diameter (20 to 40 micro meters) gold wires are used. and may extend more than halfway through the wafer. In the diamondtipped scribe method.  Diamond-tipped scribe  High-intensity laser beam (laser scribing). This is discussed below. Aluminium wire is used especially for high-current power devices. Faulty chips are identified using probe test mentioned above. Kovar is an iron-nickel-cobalt alloy whose thermal expansion coefficient is a close match to that of silicon. The metal headers are usually gold-plated Kover. In laser scribing method. the grooves are very shallow. The same process is used for discrete components. The chips are then bonded to the headers by means of the formation of a gold-silicon alloy that results in a good mechanical bond and a low-resistance electrical contact. or  High-speed circular saw Since this process is similar to glass culling it is called scribing and breaking. Now. A popular process for chip separation is to use a wafer saw to cut entirely through the wafer. such as transistor. the grooves are somewhat deeper. In the high-speed circular saw method. . Hence. the wafer will have a pattern of orthogonally oriented “scribing streets” which are kept clear of oxide and metal and are aligned along certain crystallographic directions to promote the easy and smooth cleavage of the wafer.Faulty chips will be thrown away later. This contact will be the substrate of the IC chip. The headers axe heated to temperatures in the range of 400 to 420°C in an inert-gas atmosphere (N 2 or a mixture of about 90% N2 and 10% H2). The wafer is mounted on adhesive-coated tape prior to the sawing operation so that after sawing the chips will remain in matrix form for convenience in further operations. Chip Separation The entire wafer is divided up into individual chips by “scribe-and-break” operation using any one of the following ways. only good chips are mounted in containers. Take a look at the figure below. where large-diameter round or flat ribbon leads may be used. In that case the contact will be the collector of the transistor.

. The plastic package is the lowest in cost.Lead Bonding The IC chip is now encapsulated in a metal. ceramic or plastic package. but the metal and ceramic package offer the advantage of providing a hermetic seal and a higher operating temperature range.