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Introduction to FinFET technology Part II

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Introduction to FinFET technology Part II
by ChipGuy
Published on 04-27-2012 08:00 AM


The previous post in this series provided an overview of FinFET devices. This
article will briefly cover FinFET fabrication.
The major process steps in fabricating silicon fins are shown in Figures 1 through
3. The step that defines the fin thickness uses Sidewall Image Transfer (SIT).
Low-pressure chemical vapor (isotropic) deposition provides a unique dielectric
profile on the sidewalls of the sacrificial patterned line. A subsequent (anisotropic)
etch of the dielectric retains the sidewall material (Figure 1). Reactive ion etching
of the sacrificial line and the exposed substrate results in silicon pedestals (Figure
2). Deposition of a dielectric to completely fill the volume between pedestals is
followed by a controlled etch-back to expose the fins (Figure 3).

Figure 1. Cross-section of sidewalls on sacrificial lines after CVD etch.

Figure 2. Cross-section of silicon pedestals after RIE etch, using Sidewall Image

Figure 3. Cross-section of silicon fins after oxide deposition and etch-back, and
gate deposition.
Low-pressure dielectric deposition to create sidewalls on a polysilicon line is a
well-known technique – it is commonly used to separate (deep) source/drain
implant areas from the planar FET transistor channel. FinFET fabrication extends
this technique to pattern definition for silicon fin etching.
There is no photolithography step associated with SIT, just the patterning of the
sacrificial lines. As a result, the fin thickness can be smaller than the
photolithographic minimum dimensions. The fin thickness is defined by
well-controlled dielectric deposition and etching steps rather than photoresist
patterning, reducing the manufacturing variation. However, there is variation in
fin height, resulting from (local) variations in the etch-back rate of dielectric
removal. (For FinFET's on an SOI substrate, the fin height is defined by the silicon
layer thickness, with a 'natural' silicon etch-stop at the insulator interface in
contrast to the timed-etch fin height for bulk substrate pedestals.)
There are several characteristics to note about SIT technology. Nominally, fins
come in pairs from the two sidewalls of the sacrificial line. Adding fins in parallel
to increase drive current typically involves adding a pair of fins: delta_w =
(2*(2*h_fin + t_fin)).
To “cut” fins, a masked silicon etching step is required. There are two
considerations for cutting fins. The first involves breaking long fins into individual
pairs. The other is to create an isolated fin, by removing its SIT-generated
neighbor. Critical circuits that require high density and/or different device sizing
ratios may justify the need for isolated fin patterning – e.g., SRAM bit cells.
Compared to cutting, isolated fin patterning may involve different design rules and
separate (critical) lithography steps, and thus additional costs.
Additional process steps are required to introduce impurities of the appropriate
type below the fin to provide a punchthrough stop (PTS), ensuring there is no
direct current path between drain and source that is not electrostatically

2/3/2015 9:49 PM

especially as the gate must now traverse conformally over parallel fins. the gate length is the 'critical dimension' that is typically quoted as the basis for the process node – e. However. The advantage of using multiple gate metals will be to reduce the RDF source of Vt variation substantially. although the recent introduction of metal gate materials has certainly added to the complexity. The top corner profiles also have an impact upon the transistor behavior. which would otherwise negate the drive current benefits of the FinFET topology. a spacer oxide is deposited on the FinFET gate sidewalls. To increase the volume of the source/drain. The disadvantage is the additional process complexity and cost of providing multiple metal gate compositions. providing multiple FinFET threshold voltage (Vt) offerings requires significant additional process engineering. as the electric fields from the gate to the silicon fin are concentrated in this region. variations in t_fin have significant impact upon the transistor model. Figure 4 shows the source/drain cross-section after the SEG step. The uniformity and control of the final fin dimensions are important process characteristics. dielectric. the silicon fin is effectively undoped. The resistivity is further reduced by silicidation of the top of the S/D region. The gate material traversing between parallel fins is well-separated from the substrate. Original fin is in blue -. Figure 4. (The profile of the pedestal below the fin is less critical. From Kawasaki.Introduction to FinFET technology Part II 2 of 3 http://www. separated from the FinFET gate by the sidewall spacer. et al.SemiWiki. The epitaxial growth from the exposed crystalline surface of the silicon fin results in a “faceted” volume for the S/D regions. IEDM 2009. Another key FinFET process technology development is the fabrication of the source/drain regions.note the faceted growth volume. p. The fin thickness at the bottom is also dependent upon the uniformity of the etch-back – the goal is to minimize any dielectric “foot” remaining at the bottom of the fin. The 2/3/2015 9:49 PM . minimizing the Cgx parasitic capacitance. In planar FET's. To reduce the Rs and Rd parasitics. 289-292. As was mentioned in the first series installment.. and may be quite tapered. multiple Vt offerings are readily provided by shallow (masked) impurity implants into the substrate prior to gate deposition. The dielectric between pedestals that remains after etch-back serves as the field oxide. the undoped fin results in high series resistance outside the transistor channel. compared to a planar surface.. In the case of pFET's. originating from both the sidewall and top gate materials. 20nm. as denoted in Figure 3. Cross section of source/drain region. The incorporation of impurities of the appropriate type (for nFET or pFET) during epitaxial growth reduces the S/D resistivity to a more tolerable level. The exposed S/D regions of the original fin serve as the “seed” for epitaxial With FinFET's. controlled by the gate input. Depending upon the fin spacing and the amount of epitaxial growth. a 'silicon epitaxy growth' (SEG) step is used. the variation in the (very small) dosage of impurities introduced in the planar channel results in significant Vt variation. after epitaxial growth. The current density in the S/D past the device channel to the silicide top is very non-uniform. the S/D regions of parallel fins could remain isolated. for both the fin thickness and fin corner profiles.semiwiki. as . the incorporation of a small % of Ge during this epitaxy step transfers silicon crystal stress to the channel. Although advantageous for the device characteristics. However. In contrast to planar FET technologies. Gate patterning follows conventional photolithographic steps. The threshold of any FET is a function of the workfunction potential differences between the gate. in the same manner as sidewalls were patterned earlier for SIT fin etching. adjusting the workfunction potential between dielectric and channel. or could potentially “merge” into a continuous volume.g. metal-to-dielectric workfunctions) as the preferred method for Vt adjust. as shown in Figure 3..) Tolerances in the fin thickness arise from variations in the vertical. due to the nature of the exposed fin S/D nodes. as compared to implanting a (very. very small) impurity dosage into the fin volume. As will be discussed in the next series installment. increasing hole carrier mobility significantly. due to 'random dopant fluctuation' (RDF). and silicon substrate interfaces. there is ongoing process development to provide different metal gate compositions (and thus. Raised S/D epitaxy has been used to reduce Rs/Rd for planar FET's. there are a couple of interesting characteristics to FinFET S/D process engineering. The topography of the top surface for subsequent metallization coverage is very uneven. As with a planar FET technology. anisotropic SIT silicon etch.

intel 22nm. then the gate is removed and the replacement metal gate composition is patterned. finfet.. finfet fabrication. FinFET's also require a unique process step after gate patterning and S/D node the effective Rs and Rd) is quite The time now is 08:56 AM. Copyright © 2014 SemiWiki. In a gate-last sequence. <script src="//platform. General Tags: eda.js" type="text/javascript"></script> <script type="IN/Share"></script> Share 46 Like 5 Tweet 1 Categories: Intel. to suitably fill the three-dimensional “grid” of parallel fins and series gates with a robust (low K) dielectric material. Legal / Sponsor Disclosure 2/3/2015 9:49 PM .SemiWiki. FinFET's could be fabricated with either a HKMG 'gate-first' or a 'gate-last' process. current distribution in the S/D nodes outside the channel (and thus. tsmc 20nm All times are GMT -7. All rights . semiconductor. Contacts to the S/D (and gate) will leverage the local interconnect metallization layer that has recently been added for planar 20nm technologies. The next installment of this series will discuss some of the unique FinFET transistor modeling requirements.linkedin. a dummy polysilicon gate is initially patterned and used for S/D formation. although gate-last is likely to be the prevalent to FinFET technology Part II 3 of 3 http://www.