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INSTRUCTION MANUAL

DESIGN AND SIMULATION OF INVERTER WITH
TANNER TOOL

Under The Guidance
of
Dr. Manisha Pattanaik

Designed by –
Basanta Bhowmik
Jayveer Singh Bhadauriya

Contents:

Schematic design……………………………………………..03-19
Pre layout simulation………………………………………..20-26
Layout design………………………………………………….27-50
Design rule check(DRC)…………………………………….51-53
Extraction………………………………………………………54-56
Layout Vs schematic(LVS)………………………………….57-62
Post layout simulation………………………………………63-65
Generation of GDS II file(MASK)…………………………..66-72
Appendix ……………………………………………………….73-76
MOSIS Design rule …………………………………………….73
Extracted file/Layout Netlist…………………………………74
GDSII Export file……………………………….....................75
GDSII Import file….….…………………………………………76

Schematic design of Inverter
What is schematic Design: There are many phases or progressions of a design. A common term you will
hear when working with a Designer is “Schematic Design”. This phase is early in the design process.
Schematic Design establishes the general scope, conceptual ideas, the scale and relationship of the
various program elements. The primary objective of schematic design is to arrive at a clearly defined
feasible concept based on the most promising design solutions.

Opening S-edit platform:
First of all double click on the icon of s-edit on the desktop
or
Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0

A new window will open: .

Go to >>file >> New >> New Design Select New Design .

Then Click on ‘OK’ .One dialog box will appear Design Name : Give the name your design as you wish Create a Folder : Give the path where you want to save the S-Edit Files.

0\Libraries\All\All. As for example C:\Documents and Settings\Bhowmik.Now to add libraries in your work click on Add .tanner .IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13. left on the library window. Give the path where Libraries are stored .

Now to create new cell Go to cell menu >> New view -Select ‘New view’ .

. Design name should be changed only when you are going to design another circuit) View type = schematic Interface name = “by default” View name = “by default” Then press “OK”.The new cell will appear like below: Design = your design name Cell = cell no. ( cell no you can change but your design name inv will be same for different cell.

In the black window you have seen some white bubble arranged in specific order. You can change grid distance by clicking on black screen and then scroll the mouse. then you can close the Find & command window. You can again bring these window from view menu bar.Then a cell will be appeared where we can draw the schematic of any circuit. This is called grid. If you want your screen big enough for design space . .

for example inverter a) Go to >>libraries & click on device then all device will be open. .To make any circuit schematic .

NMOS Device.) . :. then click on . instance (then the dailog box instance cell will appear.b) Select any device e.g.

.  Go to properties >> change the parameter values as your requirement. Then click DONE or press ESC.In instance cell  You can change the values of various device parameters according to your requirements.  Now before clicking DONE you have to DRAG the selected device into the cell and drop it where you want it to FIX .

For inverter we need another Pmos. .Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit.

Now connect two device with wire. Go to tool bar and select wire. .

Similarly to give input & output port in the circuit . . select input port that shown by red ellipse.

Now you can give Port name as you wish in the dailog box. . Then click OK Similarly give Output Port name. NOTE : you can rotate the port (short cut key “R”).

Now. after completed these steps. you should give the supply (VDD) & ground (GND). For that Go to liberaries >> MISC >>Select VDD or GND .

For that go to libraries >>spice_element >> and then select voltage source of type DC . you can give any value in vdd .lets take vdd =5v.Now you have to create a source of VDD. By doing all the above steps you have completed schematic of Inverter .

That’s why you need to simulate the design which is called Pre layout simulation.Pre layout simulation After schematic design you have to check whether your design match with the specification required or not . For simulation go to>> tools>> T-spice>> ‘ok’ .

A T-spice window will open. Then click on the bar shown by red ellipse .

On the T-spice command you can see in the left hand side Analysis. Current source Files Initialization. Output Settings Table Voltage source Optimization .A “T-spice command Tool “ dialog box will open as shown beow.

18um\MODEL_0. C:\Documents and Settings\Bhowmik.18µm files >> Insert command.18.18 µm Technology file .md . Step 1 : You have to include TSMC 0. For that Go to >> T-spice command tool >> Files >> Include >> browse TSMC .IIIT-3AC288AD0A\Desktop\TSMC 0.Lets start doing transient analysis of Inverter.

Step2 : Then to give Input T-spice command tool >> Voltage source >> select type of input you want to give(lets take bit) >> Insert command Step 3: Analysis T-spice command tool >> Analysis >> select type of analysis you want to give(lets take transient) >> Insert command step 4: Output T-spice command tool >> Output >> which output you want to see >> Insert Command .File is included shown by highlight.

Then Run by clicking red ellipse shown on left above corner.The total spice netlist will come like this. Now save it . .

Output of Pre layout simulation of Inverter .

Procedure of Layout Design in 0. There is a continuing need for the creation of new layoutdesigns which reduce the dimensions of existing integrated circuits and simultaneously increase their functions.Layout Design What is Layout Design: A layout-design of an IC refers essentially to the 3-dimensional character of the elements and interconnections of an IC.18µm CMOS Technology(MOSIS>> Mamin08) Opening L-edit platform: First of all double click on the icon of L-edit on the desktop or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 .0 >> L-Edit v 13.

5 µm L= 3.5 µm L =2.A window will come like below.75 µm w= 1. We will start the layout of Inverter with NMOS PMOS w= 1.50 µm .

>> select A dialog box will come as shown in fig Select layout and then press ‘ok’.For inverter layout Go to file>> new…. .

A new layout window will open .

Carefully observe the Red ellipse which will be frequently used for your Design. .

In TSMC .Before starting layout design you have to set the Technology you want to used.18 µm Technology. available Technology are Charterd China_hj Generic0_25 µm Mosis Orbit So to set the Technology Go to >> File >> Replace setup and then select .

Mosis design rule are given in appendix. . Click on browse >> Tanner EDA >> Tanner Tools v13. Lets take in the above set up you set Mosis ->Mamin08 Technology.A dialog box will come.A small dialog box will come and it tells you .0 >>L-edit and LVS >> TECH >> Mosis >> mamin08 or mamin12 or …………or………… >> press ok After pressing ‘ok’ . In that stage press ok. That means you have to follow Mosis design rule in your entire design.Technology are going to be changes.

I have choosen Lambda rule for convenience.Now lets recheck your technology set up. For that Go to >> set up >> Design >> then select In the” Set up design layout2 “dialog box you have seen there are many technology units. .5 micron .you can choose any one of them for your design. You can choose your own for better understandig and drawing the design. Also for “Technology to micron mapping “ I have taken 1 lambda=0.

Atlast press ok . Now you properly create the environment for design. I have taken Major diplayed grid=10 lambda Minor diplayed grid=1 lambda (You put according to your calculation) Like that many other parameter you can change that’s depends upto you. .In the same way select grid For design convenience and properly maintain the DRC .

But In the library some standard devices available which are not enough for your requirement all the time .That’s why you need a good practice to Design all the way from start to end of the Design. The device will come in cell window.This is a bad practice. BY default The cell window is P-type.source and drain will be P-type and pollysilicon Gate.You have two option for any Design .which is already available.g mamin08) >> press ok >> a series of devices which are available in the library will come >> seect EXT_NMOS or EXT_PMOS >> press ok .Lets take example of Inverter First: For inverter design first of all you have to create a PMOS and a NMOS in the same window. So for design Pmos you need N-substrate that means Select N-well >> select switch to draging box (left upper corner of the window) >> draw . So first of all design a PMOS. For that Go to Cell >> Instance >> browse the Technology what you are using (e. For PMOS you need a N –type substrate . We will follow first procedure. Or Second:You can bring a PMOS and NMOS from the Library .

Then Select P-select >> select switch to draging box (left upper corner of the window) >>
draw

Now Select Active >> select switch to draging box (left upper corner of the window) >>
draw

Now Select Active >> select switch to draging box (left upper corner of the window) >>
draw

So the procedure is first draw a n-select then then draw the active area and then polysilicon gate.In the same way draw Nmos .Here not required p-well because the window is already p-type. .

After designing Nmos and Pmos you have to connect them . Pmos . e. For source .Vdd and Gnd you have to take Metal 1 layer.drain .Nmos drain are connected to output and both gate are connected to Input.g PMOS source and substrate will be connected to VDD and Nmos source and substrate will be connected to Gnd. To connect Pmos substrare to Vdd you need N-select and Metal -1 layer .

To connect Nmos substrare to Gnd you need P-select and Metal -1 layer .

Now connect source and vdd of pMOS by Metal-1 layer .

Put active contact of size 2µm×2 µm .

.Now connect nMOS drain to pMOS drain and nMOS source to Gnd by metal-1 layer.shown by red ellipse.

.Put active contact .

To make contact on Polysilicon.Now Connect both Gate as shown below. you need metal-1 (3µm×3 µm)layer and Poly contact of size (2µm×2 µm) .

click to “Switch to drawing ports” as shown below: .To give name to input output port.

As for example to give name Vdd you have to select the Metal-1 layer shown in figure. click on that part of the layout where you want to give name of the port. .After clicking on the “Switch to drawing ports”.

After giving name to each port. Then save your design. . your layout look like as shown below.

Go to >>setup DRC >> select One dialog box will come as shown below.DESIGN RULE CHECK(DRC) Design Rule Check (DRC) is the area of Electronic Design Automation (EDA) that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules. Design rule checking is a major step during Physical verification signoff on the design. Design rules are specific to a particular semiconductor manufacturing process. check out “DRC Standard Rule Set” then press OK. Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. .

Now run” DRC” shown by red ellipse. .

if there is no error that means your design satisfies Design rule check. .After running “DRC”.

e.EXTRACT To verify the functionality and timing of this inverter. The extracted view also allows you to run LVS (Layout vs Schematic). . then a setup extract dialog box will open. but we can still generate the extracted view from which a netlist can be generated (once we fix the installation). you need to extract the spice netlist from the layout then simulate it. probably for the same reason the netlisting is broken) allows you to compare a schematic and an extracted physical layout to verify that they are equivalent ( i. This tool (which is also not working at the moment. signals are connected the same way) To extract. the netlisting is not working at that moment. Unfortunately. click on “setup extract”. check extract standard rule set if it is not checked and then click on pencil icon as shown below.

0 >> L –edit and LVS >> Tech >> Mosis >> mamin08.After clicking on pencil icon.write . All others are optional. Subcircuit-> optional. in that window give path of Extract Definition File. Browse >> My document >> Tanner EDA >> Tanner Tools v13.md file must be included in spice included Statement.End statement . Then Press ‘OK’. If you not give proper path of Extract definition file then a dialog box will come showing you “I/O Error cannot open file”.include mamin08. Note: (check General -> open output file after extracting and all others are optional . Output-> Names. . “Setup Extract Standard Rule Set” window will open.Write verbose spice statements.

. perimeter. A extracted file or netlist contaninig device details like connections. Then warning will come like below.aspect ratio .and juntion capacitances will come .At this stage click on Ignore all.source area. Netlist or Extracted file of the inverter shown in appendix.drain area.To extract click on EXT toolbar shown by highlighting.

LVS Checking involves : 1. the wiring conductors and via structures. If the two netlists match. It then runs the database through many area based logic operations. . A similar reduction is performed on the "source" Schematic netlist. LVS checking software recognizes the drawn shapes of the layout that represent the electrical Components of the circuit. Area based logical operations use polygon areas as inputs and generate output polygon areas from these operations. These operations are used to define the device recognition layers. 3. then the circuit passes the LVS check and a message will come “the circuit are equal”. and the locations of pins (also known as hierarchical connection points). the terminals of these devices. 2. Comparison: The extracted layout netlist is then compared to the netlist taken from the circuit schematic. Extraction: The software program takes a database file containing all the layers drawn to represent the circuit during layout. as well as the connections between them. At this point it is said to be "LVS clean .Layout Vs schematic(LVS) The Layout Versus Schematic (LVS) is the class of EDA verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design. This netlist is compared by the "LVS" software against a similar schematic or circuit diagram's netlist. Reduction: In the time of reduction the software combines the extracted components into series and parallel combinations if possible and generates a netlist representation of the layout database.

0 .Opening LVS platform: First of all double click on the icon of LVS V13.0 on the desktop or Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> LVS v 13.

.A new window will come as shown below.

Then go to >>file >> new >> LVS setup >> ok .

paracitics. merge device. After checking click on run verification(shown by red ellipse) . the are basically optional. device parameter.Select input.performance . In the input you have to import Layout netlist and Schematic netlist.include……………… . Note: (don’t forget to remove .options.md file from both netlist ). Select output.

In final report a message will shows “The circuits are equal”. .A dialog box verification will come. That means your LVS checking is complete and your layout design perfectly same as schematic of your design.

you should perform a post-layout simulation from the extracted view. and should have passed the DRC and LVS steps with no violations. This may require multiple iterations on the design. i. . and any glitches that may occur due to signal delay mismatches. the designer should have a complete mask layout of the intended circuit/system.Post layout simulation The parasitic capacitances extracted according to how your layout is designed might be critical in affecting the actual performance of your design. until the post-layout simulation results satisfy the original design requirements. The detailed (transistor-level) simulation performed using the extracted net-list will provide a clear assessment of the circuit speed..e. in order to achieve the desired circuit performance under "realistic" conditions. At this point. In order to get an idea of how the design would work from your layout. If the results of post-layout simulation are not satisfactory. the influence of circuit parasitics (such as parasitic capacitances and resistances). The electrical performance of a full-custom design can be best analyzed by performing a postlayout simulation on the extracted circuit net-list. you should modify some of the transistor dimensions and/or the circuit topology. taking into account all of the circuit parasitics. The procedure is identical to that for simulating from the schematic view.

For post layout simulation Open layout netlist >> rest of the process is same as prelayout simulation. .

Output of post layout simulation : .

transferring artwork between different tools. text labels. It is a format that ASIC Foundries accept for the manufacture of ASICs/VLSIs (mainly standard cells). route problems. The data can be used to reconstruct all or part of the artwork to be used in sharing layouts. critical placements. and other DRCs are taken under account to shorten up the "Timing Closure" cycle process. GDSII contains Masks layers (as many as 24 to 30). Crosstalk. Alike Gerber. Signal Integrity. including Metal top layer(s). GDSII is like Gerber for PCBs. This is especially true for the new nanometer technologies (below 0. The Term RTL-to-GDSII refers to a design methodology where already in the RTL stage.13um) To generate GDS II file go to >> File >> Export Mask Data >> GDSII >> ok . is a database file format which is the de facto industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary file format representing planar geometric shapes. or creating photomasks. common acronym GDSII.Generation of GDS II file(MASK) GDS II stream format. and other information about the layout in hierarchical form.

Shown by red ellipse .A Export GDSII dialog box will come . click on the “Export” button.

If you want log file to save . Elapsed Time: 0.This is basically optional.a GDSII Export file will come .00 seconds Then close the layout cell(not layout window) and import GDSII (MASK) file. Like below.then first click on it and give a new name . Summary: Export Successful. After Exporting . . It will tell you the details of Exporting. Last of the report something written .

For that go to >> File >> Import Mask Data >> GDSII >>ok Click on the “Import”. .

Press “ok” .

.

As for example in the below shows a mask of Inverter Appendix .After Importing you will get MASK of your Design.

MOSIS Design rule Rule number RI R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 Description Active area rules Minimum active area width Minimum active area spacing Polysilicon rules Minimum poly width Minimum poly spacing Minimum gate extension of poly over active Minimum poly-active edge spacing (poly outside active area) Minimum poly-active edge spacing (poly inside active area) Metal rules Minimum metal width Minimum metal spacing Contact rules Poly contact size Minimum poly contact spacing Minimum poly contact to poly edge spacing Minimum poly contact to metal edge spacing Minimum poly contact to active edge spacing Active contact size Minimum active contact spacing (on the same active region) Minimum active contact to active edge spacing Minimum active contact to metal edge spacing Minimum active contact to poly edge spacing Minimum active contact spacing (on different active regions) Extracted file/Netlist of Layout λ Rule 3λ 3λ 2λ 2λ 2λ 1λ 3λ 3λ 3λ 2λ 2λ 1λ 1λ 3λ 2λ 2λ 1λ 1λ 3λ 6λ .

01 .000 sec * Total Extract Elapsed Time: 10.484 sec .include mamin08. * TDB File: E:\layout\layout\Layout2.md * Warning: Layers with Unassigned AREA Capacitance.END .20 * Extract Definition File: C:\Documents and Settings\Bhowmik.5u AS=11.tdb * Cell: Cell0 Version 1.5 28 34.19:26 .5u AD=14.01 / Extract Version 13.5u AS=15.75u AD=12.5) * Total Nodes: 4 * Total Elements: 2 * Total Number of Shorted Elements not written to the SPICE file: 0 * Output Generation Elapsed Time: 0.6875p PS=14u $ (25 7 28 12.5u W=2.875p PD=15.5) M2 Out In Vdd Vdd PMOS L=1.5u W=3.* Circuit Extracted by Tanner Research's L-Edit Version 13.ext * Extract Date and Time: 08/28/2011 . * <PMOS Capacitor> * <Pad Comment> * <NMOS Capacitor> * <PCAP Capacitor> M1 Out In Gnd Gnd NMOS L=1.IIIT-3AC288AD0A\My Documents\Tanner EDA\Tanner Tools v13.0\L-Edit and LVS\Tech\Mosis\mamin08. * <PMOS Capacitor> * <NMOS Capacitor> * <PCAP Capacitor> * Warning: Layers with Unassigned FRINGE Capacitance.75p PS=16u $ (25 27.375p PD=14.

Checking GDSII Numbers ..001 Lambda All ports with port boxes will be converted to point ports Checking XrefCell links .. All cells are being exported Use custom GDSII units: 1 database unit = 0.0005 microns..00 seconds . 1 database unit = 0....gds Option Settings: Do not export hidden objects: ON Overwrite data type on export: ON Calculate MOSIS checksum: OFF Check for self-intersecting polygons and wires: OFF Write XrefCells as links: OFF Preserve case of cell names: ON Restrict cell names to 32 characters.tdb GDSII File: E:\layout\layout\Layout2. Writing actual GDSII data . TDB File: E:\layout\layout\Layout2.. Fracture polygons: OFF Manufacturing grid for circle and curve approximation: 0. Summary: Export Successful.. Elapsed Time: 0.001 user units...GDSII Export File GDSII Export. Completed writing actual GDSII data .. Checking for Hidden Layers and Objects ..

... Resolving External Cell References.gds .tmp Option Settings: Treat unique GDS data types on a layer as different layers: ON Using original GDSII database resolution: 0...0 error(s). 8 warning(s) Import Successful Elapsed Time: 1.GDSII Import File GDSII Import.gds SetupFile: C:\DOCUME~1\BHOWMI~1. GDSII File: E:\layout\layout\Layout2.III\LOCALS~1\Temp\tdb6C. Summary: E:\layout\layout\Layout2.08 seconds .0005 microns Warning #33: Found unknown GDSII layer 47 (Action: Created a new layer GDS_47_DT_00 for GDSII number 47 and Data type 0) Warning #33: Found unknown GDSII layer 46 (Action: Created a new layer GDS_46_DT_00 for GDSII number 46 and Data type 0) Warning #33: Found unknown GDSII layer 43 (Action: Created a new layer GDS_43_DT_00 for GDSII number 43 and Data type 0) Warning #33: Found unknown GDSII layer 49 (Action: Created a new layer GDS_49_DT_00 for GDSII number 49 and Data type 0) Warning #33: Found unknown GDSII layer 42 (Action: Created a new layer GDS_42_DT_00 for GDSII number 42 and Data type 0) Warning #33: Found unknown GDSII layer 45 (Action: Created a new layer GDS_45_DT_00 for GDSII number 45 and Data type 0) Warning #33: Found unknown GDSII layer 44 (Action: Created a new layer GDS_44_DT_00 for GDSII number 44 and Data type 0) Warning #33: Found unknown GDSII layer 48 (Action: Created a new layer GDS_48_DT_00 for GDSII number 48 and Data type 0) Checking for Cell Name Conflicts..