Professional Documents
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Data Sheet
28/40/44-Pin Flash-Based,
8-Bit CMOS Microcontrollers
Preliminary
DS41341B
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, rfPIC and SmartShunt are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
DS41341B-page ii
Preliminary
PIC16F72X/PIC16LF72X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers
Devices Included In This Data Sheet:
PIC16F72X Devices:
PIC16F722
PIC16F723
PIC16F724
PIC16F726
PIC16F727
Low-Power Features:
Standby Current:
- 60 nA @ 2.0V, typical
Operating Current:
- 7.0 A @ 32 kHz, 2.0V, typical
- 110 A @ 1 MHz, 2.0V, typical
Low-Power Watchdog Timer Current:
- 0.5 A @ 1.8V, typical
PIC16LF72X Devices:
PIC16LF722
PIC16LF723
PIC16LF724
PIC16LF726
PIC16LF727
Peripheral Features:
Preliminary
DS41341B-page 1
PIC16F72X/PIC16LF72X
Device
PIC16F722/
PIC16LF722
PIC16F723/
PIC16LF723
PIC16F724/
PIC16LF724
PIC16F726/
PIC16LF726
PIC16F727/
PIC16LF727
DS41341B-page 2
Program
Memory
Flash
(words)
SRAM
(bytes)
I/Os
Interrupts
8-bit A/D
(ch)
AUSART
CCP
Timers
8/16-bit
2048
128
25
12
11
Yes
2/1
4096
192
25
12
11
Yes
2/1
4096
192
36
12
14
Yes
2/1
8192
368
25
12
11
Yes
2/1
8192
368
36
12
14
Yes
2/1
Preliminary
PIC16F72X/PIC16LF72X
Pin Diagrams 28-PIN PDIP/SOIC/SSOP/QFN (PIC16F722/723/726/PIC16LF722/723/726)
28
RB7/ICSPDAT
27
RB6/ICSPCLK
AN1/RA1
26
RB5/AN13/CPS5/T1G
AN2/RA2
25
RB4/AN11/CPS4
24
23
RB3/AN9/CPS3/CCP2(1)
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
VSS
CLKIN/OSC1/RA7
PIC16F722/723/726/
PIC16LF722/723/726
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
RB2/AN8/CPS2
22
21
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
20
VDD
19
(1)
CCP2 /T1OSI/RC1
12
17
RC6/TX/CK
CCP1/RC2
SCL/SCK/RC3
13
16
RC5/SDO
14
15
RC4/SDI/SDA
T1CKI/T1OSO/RC0
11
28
27
26
25
24
23
22
RA1/AN1
RA0/AN0/SS(2)/VCAP(3)
10
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5/AN13/CPS5/T1G
RB4/AN11/CPS4
18
VSS
RC7/RX/DT
VCAP(3)/CLKOUT/OSC2/RA6
1
2
3
PIC16F722/723/726/
4 PIC16LF722/723/726
5
6
7
21
20
19
18
17
16
15
RB3/AN9/CPS3/CCP2(1)
RB2/AN8/CPS2
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
VDD
VSS
RC7/RX/DT
CCP1/RC2
SCL/SCK/RC3
SDA/SDI/RC4
SDO/RC5
CK/TX/RC6
T1CKI/T1OSO/RC0
CCP2(1)/T1OSI/RC1
8
9
10
11
12
13
14
AN2/RA2
VREF/AN3/RA3
T0CKI/CPS6/RA4
VCAP(3)/SS(2)/CPS7/AN4/RA5
VSS
CLKIN/OSC1/RA7
VCAP(3)/CLKOUT/OSC2/RA6
Preliminary
DS41341B-page 3
PIC16F72X/PIC16LF72X
TABLE 1:
I/O
28-Pin
PDIP,
SOIC,
SSOP
28-Pin
QFN
A/D
Cap Sensor
Timers
CCP
AUSART
SSP
RA0
27
AN0
SS(3)
VCAP(4)
RA1
28
AN1
RA2
AN2
RA3
AN3/VREF
Interrupt Pull-Up
Basic
RA4
CPS6
T0CKI
RA5
AN4
CPS7
SS(3)
VCAP(4)
RA6
10
OSC2/CLKOUT/VCAP(4)
RA7
OSC1/CLKIN
RB0
21
18
AN12
CPS0
IOC/INT
RB1
22
19
AN10
CPS1
IOC
RB2
23
20
AN8
CPS2
IOC
RB3
24
21
AN9
CPS3
CCP2(2)
IOC
RB4
25
22
AN11
CPS4
IOC
RB5
26
23
AN13
CPS5
T1G
IOC
RB6
27
24
IOC
ICSPCLK/ICDCLK
ICSPDAT/ICDDAT
RB7
28
25
IOC
RC0
11
T1OSO/T1CKI
RC1
12
T1OSI
CCP2(2)
RC2
13
10
CCP1
RC3
14
11
SCK/SCL
SDI/SDA
SDO
RC4
15
12
RC5
16
13
RC6
17
14
TX/CK
RC7
18
15
RX/DT
RE3
26
Y(1)
MCLR/VPP
20
17
VDD
8,19
5,16
VSS
Note
1:
2:
3:
4:
DS41341B-page 4
Preliminary
PIC16F72X/PIC16LF72X
Pin Diagrams 40-PIN PDIP (PIC16F724/727/PIC16LF724/727)
VPP/MCLR/RE3
(3)
40
RB7/ICSPDAT
39
RB6/ICSPCLK
AN1/RA1
38
RB5/AN13/CPS5/T1G
AN2/RA2
37
RB4/AN11/CPS4
VREF/AN3/RA3
36
RB3/AN9/CPS3/CCP2(1)
T0CKI/CPS6/RA4
35
RB2/AN8/CPS2
/CPS7/AN4/RA5
AN5/RE0
34
33
RB1/AN10/CPS1
RB0/AN12/CPS0/INT
AN6/RE1
32
VDD
AN7/RE2
10
31
VSS
VDD
11
30
RD7/CPS15
VSS
12
29
RD6/CPS14
(3)
/SS
(2)
PIC16F724/727/
PIC16LF724/727
VCAP
(2)
CLKIN/OSC1/RA7
13
28
RD5/CPS13
VCAP(3)/CLKOUT/OSC2/RA6
14
27
RD4/CPS12
T1CKI/T1OSO/RC0
15
26
RC7/RX/DT
CCP2(1)/T1OSI/RC1
16
25
RC6/TX/CK
CCP1/RC2
SCL/SCK/RC3
17
24
RC5/SDO
18
23
CPS8/RD0
19
22
RC4/SDI/SDA
RD3/CPS11
CPS9/RD1
20
21
RD2/CPS10
Preliminary
DS41341B-page 5
PIC16F72X/PIC16LF72X
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
NC
PIC16F724/727/
PIC16LF724/727
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSO/T1CKI
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
NC
NC
CPS4/AN11/RB4
T1G/CPS5/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
CPS15/RD7
VSS
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
CCP2(1)/CPS3/AN9/RB3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
DS41341B-page 6
Preliminary
PIC16F72X/PIC16LF72X
PIC16F724/727/
PIC16LF724/727
33
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
RA6/OSC2/CLKOUT/VCAP(3)
RA7/OSC1/CLKIN
VSS
VSS
NC
VDD
RE2/AN7
RE1/AN6
RE0/AN5
RA5/AN4/CPS7/SS(2)/VCAP(3)
RA4/CPS6/T0CKI
CCP2(1)/CPS3/AN9/RB3
NC
CPS4/AN11/RB4
T1G/CPS5/AN13/RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
VCAP(3)/SS(2)/AN0/RA0
AN1/RA1
AN2/RA2
VREF/AN3/RA3
DT/RX/RC7
CPS12/RD4
CPS13/RD5
CPS14/RD6
CPS15/RD7
VSS
VDD
VDD
INT/CPS0/AN12/RB0
CPS1/AN10/RB1
CPS2/AN8/RB2
44
43
42
41
40
39
38
37
36
35
34
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/CPS11
RD2/CPS10
RD1/CPS9
RD0/CPS8
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T1CKI
Preliminary
DS41341B-page 7
PIC16F72X/PIC16LF72X
40/44-PIN PDIP/TQFP/QFN SUMMARY (PIC16F724/727/PIC16LF724/727)
TABLE 2:
I/O
40-Pin
PDIP
44-Pin
TQFP
44-Pin
QFN
A/D
Cap
Sensor
Timers
CCP
AUSART
SSP
RA0
19
19
AN0
SS(3)
VCAP(4)
RA1
20
20
AN1
RA2
21
21
AN2
RA3
22
22
AN3/VREF
RA4
23
23
CPS6
T0CKI
RA5
24
24
AN4
CPS7
SS(3)
VCAP(4)
RA6
14
31
33
OSC2/CLKOUT/VCAP(4)
RA7
13
30
32
OSC1/CLKIN
RB0
33
AN12
CPS0
IOC/INT
RB1
34
10
AN10
CPS1
IOC
Interrupt Pull-Up
Basic
RB2
35
10
11
AN8
CPS2
IOC
RB3
36
11
12
AN9
CPS3
CCP2(2)
IOC
RB4
37
14
14
AN11
CPS4
IOC
RB5
38
15
15
AN13
CPS5
T1G
IOC
RB6
39
16
16
IOC
ICSPCLK/ICDCLK
RB7
40
17
17
IOC
ICSPDAT/ICDDAT
RC0
15
32
34
T1OSO/
T1CKI
RC1
16
35
35
T1OSI
CCP2(2)
RC2
17
36
36
CCP1
RC3
18
37
37
SCK/SCL
RC4
23
42
42
SDI/SDA
RC5
24
43
43
SDO
RC6
25
44
44
TX/CK
RC7
26
RX/DT
RD0
19
38
38
CPS8
RD1
20
39
39
CPS9
RD2
21
40
40
CPS10
RD3
22
41
41
CPS11
RD4
27
CPS12
RD5
28
CPS13
RD6
29
CPS14
RD7
30
CPS15
RE0
25
25
AN5
RE1
26
26
AN6
RE2
10
27
27
AN7
RE3
18
18
Y(1)
MCLR/VPP
11,32
7,20
7,8,28
VDD
12,13
6,29
6,30,31
VSS
Note
1:
2:
3:
4:
DS41341B-page 8
Preliminary
PIC16F72X/PIC16LF72X
Table of Contents
1.0 Device Overview ....................................................................................................................................................................... 11
2.0 Memory Organization ................................................................................................................................................................ 17
3.0 Resets ....................................................................................................................................................................................... 31
4.0 Interrupts ................................................................................................................................................................................... 41
5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 49
6.0 I/O Ports .................................................................................................................................................................................... 51
7.0 Oscillator Module....................................................................................................................................................................... 87
8.0 Device Configuration ................................................................................................................................................................. 93
9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 97
10.0 Fixed Voltage Reference......................................................................................................................................................... 107
11.0 Timer0 Module ........................................................................................................................................................................ 109
12.0 Timer1 Module with Gate Control............................................................................................................................................ 113
13.0 Timer2 Module ........................................................................................................................................................................ 125
14.0 Capacitive Sensing Module..................................................................................................................................................... 127
15.0 Capture/Compare/PWM (CCP) Module .................................................................................................................................. 133
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) .......................................................... 143
17.0 SSP Module Overview ............................................................................................................................................................ 165
18.0 Program Memory Read ........................................................................................................................................................... 187
19.0 Power-Down Mode (Sleep) ..................................................................................................................................................... 191
20.0 In-Circuit Serial Programming (ICSP) .............................................................................................................................. 193
21.0 Instruction Set Summary ......................................................................................................................................................... 195
22.0 Development Support.............................................................................................................................................................. 205
23.0 Electrical Specifications........................................................................................................................................................... 209
24.0 DC and AC Characteristics Graphs and Charts ...................................................................................................................... 239
25.0 Packaging Information............................................................................................................................................................. 241
Appendix A: Data Sheet Revision History......................................................................................................................................... 253
Appendix B: Migrating From Other PIC Devices............................................................................................................................. 253
Index ................................................................................................................................................................................................. 255
The Microchip Web Site .................................................................................................................................................................... 261
Customer Change Notification Service ............................................................................................................................................. 261
Customer Support ............................................................................................................................................................................. 261
Reader Response ............................................................................................................................................................................. 262
Product Identification System ........................................................................................................................................................... 263
Preliminary
DS41341B-page 9
PIC16F72X/PIC16LF72X
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS41341B-page 10
Preliminary
PIC16F72X/PIC16LF72X
1.0
DEVICE OVERVIEW
Preliminary
DS41341B-page 11
PIC16F72X/PIC16LF72X
FIGURE 1-1:
Configuration
13
Program Counter
Flash
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
14
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
Data Bus
RAM
PORTB
RAM Addr
Addr MUX
Instruction
Instruction Reg
reg
7
Direct Addr
Indirect
Addr
FSR
FSR Reg
reg
STATUS
STATUS Reg
reg
PORTC
8
3
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode
Decodeand
&
Control
Timing
Generation
OSC2/CLKOUT
MUX
PORTE
RE3
Watchdog
Timer
Brown-out
Reset
LDO(1)
Regulator
Internal
Oscillator
Block
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
ALU
Power-on
Reset
OSC1/CLKIN
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
W
W Reg
reg
CCP1
CCP1
MCLR VDD
VSS
CCP2
CCP2
T1OSI
T1OSO
Timer1
32 kHz
Oscillator
TX/CK RX/DT
T0CKI
Timer0
VREF
T1G
SDI/ SCK/
SDO SDA SCL
SS
T1CKI
Timer1
Timer2
AUSART
AUSART
Synchronous
Serial Port
Analog-To-Digital Converter
AN0 AN1 AN2 AN3 AN4 AN8 AN9 AN10 AN11 AN12 AN13
Note
1:
PIC16F722/723/726 only.
DS41341B-page 12
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 1-2:
Configuration
13
Program Counter
Flash
Program
Memory
Program
Bus
8 Level Stack
(13-bit)
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
Data Bus
RAM
14
PORTB
RAM Addr
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
Addr MUX
Instruction
Instruction Reg
reg
7
Direct Addr
Indirect
Addr
FSR reg
Reg
FSR
STATUS
STATUS Reg
reg
8
3
Power-up
Timer
Instruction
Decode
Decodeand
&
Control
OSC1/CLKIN
OSC2/CLKOUT
Timing
Generation
Internal
Oscillator
Block
Oscillator
Start-up Timer
PORTC
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
MUX
ALU
Power-on
Reset
PORTD
Watchdog
Timer
Brown-out
Reset
LDO(1)
Regulator
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
W Reg
CCP1
CCP1
PORTE
RE0
MCLR VDD
T1OSI
T1OSO
T0CKI
Timer0
VREF
VSS
RE1
CCP2
CCP2
RE3
Timer1
32 kHz
Oscillator
T1G
RE2
TX/CK RX/DT
SDI/ SCK/
SDO SDA SCL SS
AUSART
Synchronous
Serial Port
T1CKI
Timer1
Timer2
Analog-To-Digital Converter
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS6 CPS7 CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15
Note
1:
PIC16F724/727 only.
Preliminary
DS41341B-page 13
PIC16F72X/PIC16LF72X
TABLE 1-1:
Name
RA0/AN0/SS/VCAP
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/CPS6/T0CKI
RA5/AN4/CPS7/SS/VCAP
RA6/OSC2/CLKOUT/VCAP
RA7/OSC1/CLKIN
RB0/AN12/CPS0/INT
RB1/AN10/CPS1
RB2/AN8/CPS2
RB3/AN9/CPS3/CCP2
Function
Input
Type
RA0
TTL
AN0
AN
SS
ST
Power
Power
RA1
TTL
AN1
AN
RA2
TTL
AN2
AN
RA3
TTL
AN3
AN
VREF
AN
RA4
TTL
Description
VCAP
CPS6
AN
T0CKI
ST
RA5
TTL
AN4
AN
CPS7
AN
SS
ST
VCAP
Power
RA6
TTL
OSC2
CLKOUT
VCAP
Power
RA7
TTL
Power
OSC1
XTAL
CLKIN
CMOS
CLKIN
ST
RB0
TTL
AN12
AN
CPS0
AN
INT
ST
External interrupt.
RB1
TTL
AN10
AN
CPS1
AN
RB2
TTL
AN8
AN
CPS2
AN
RB3
TTL
AN9
AN
CPS3
AN
CCP2
ST
DS41341B-page 14
Output
Type
CMOS Capture/Compare/PWM2.
Preliminary
PIC16F72X/PIC16LF72X
TABLE 1-1:
Name
RB4/AN11/CPS4
RB5/AN13/CPS5/T1G
RB6/ICSPCLK/ICDCLK
RB7/ICSPDAT/ICDDAT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/CPS8
RD1/CPS9
RD2/CPS10
Function
Input
Type
RB4
TTL
Description
AN11
AN
CPS4
AN
RB5
TTL
AN13
AN
CPS5
AN
T1G
ST
RB6
TTL
ICSPCLK
ST
ICDCLK
ST
RB7
TTL
ICSPDAT
ST
ICDDAT
ST
RC0
ST
T1OSO
XTAL
XTAL
T1CKI
ST
RC1
ST
T1OSI
XTAL
CCP2
ST
CMOS Capture/Compare/PWM2.
RC2
ST
CCP1
ST
CMOS Capture/Compare/PWM1.
RC3
ST
SCK
ST
SCL
I2C
RC4
ST
OD
I2C clock.
SDI
ST
SDA
I2C
OD
RC5
ST
SDO
RC6
ST
TX
CK
ST
RC7
ST
RX
ST
DT
ST
RD0
ST
CPS8
AN
RD1
ST
CPS9
AN
RD2
ST
CPS10
AN
Output
Type
Preliminary
DS41341B-page 15
PIC16F72X/PIC16LF72X
TABLE 1-1:
Name
RD3/CPS11
RD4/CPS12
RD5/CPS13
RD6/CPS14
RD7/CPS15
Function
Input
Type
RD3
ST
CPS11
AN
RD4
ST
CPS12
AN
RD5
ST
CPS13
AN
RD6
ST
CPS14
AN
RD7
ST
CPS15
AN
RE0/AN5
RE0
ST
AN5
AN
RE1/AN6
RE1
ST
AN6
AN
RE2/AN7
RE2
ST
RE3/MCLR/VPP
Output
Type
Description
AN7
AN
RE3
TTL
MCLR
ST
VPP
HV
Programming voltage.
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
DS41341B-page 16
Preliminary
PIC16F72X/PIC16LF72X
2.0
MEMORY ORGANIZATION
2.1
FIGURE 2-2:
FIGURE 2-1:
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Page 1
PC<12:0>
CALL, RETURN
RETFIE, RETLW
0FFFh
1000h
13
Wraps to Page 0
17FFh
1800h
Stack Level 1
Stack Level 2
Wraps to Page 1
1FFFh
Stack Level 8
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Wraps to Page 0
0FFFh
1000h
Wraps to Page 0
17FFh
1800h
Wraps to Page 0
1FFFh
Preliminary
DS41341B-page 17
PIC16F72X/PIC16LF72X
FIGURE 2-3:
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
On-chip
Program
Memory
RP0
Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Bank 3 is selected
Stack Level 8
Reset Vector
2.2
2.2.1
Page 1
0FFFh
1000h
Page 2
17FFh
1800h
Page 3
1FFFh
2.2.2
DS41341B-page 18
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 2-4:
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
FSR
04h
FSR
84h
05h
TRISA
85h
105h
FSR
ANSELA
184h
PORTA
PORTB
06h
TRISB
86h
106h
ANSELB
186h
PORTC
07h
TRISC
87h
107h
187h
188h
08h
88h
CPSCON0
108h
185h
189h
PORTE
09h
TRISE
89h
CPSCON1
109h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
110h
190h
18Fh
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD/SSPMSK 93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
RCREG
1Ah
9Ah
11Ah
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
120h
1A0h
EFh
16Fh
1EFh
F0h
170h
1F0h
ADCON1
20h
General
Purpose
Register
32 Bytes
General
Purpose
Register
96 Bytes
BFh
C0h
Accesses
70h-7Fh
7Fh
Bank 0
Legend:
*
Accesses
70h-7Fh
FFh
Bank 1
Accesses
70h-7Fh
17Fh
Bank 2
1FFh
Bank 3
Preliminary
DS41341B-page 19
PIC16F72X/PIC16LF72X
FIGURE 2-5:
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
FSR
04h
FSR
84h
05h
TRISA
85h
105h
FSR
ANSELA
184h
PORTA
PORTB
06h
TRISB
86h
106h
ANSELB
186h
PORTC
07h
TRISC
87h
107h
PORTD(1)
08h
TRISD(1)
88h
CPSCON0
185h
187h
108h
ANSELD(1)
109h
ANSELE(1)
189h
10Ah
PCLATH
18Ah
188h
PORTE
09h
TRISE
89h
CPSCON1
PCLATH
0Ah
PCLATH
8Ah
PCLATH
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
110h
190h
18Fh
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
SSPBUF
13h
SSPADD/SSPMSK 93h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
CCPR1L
15h
WPUB
95h
115h
195h
CCPR1H
16h
IOCB
96h
116h
196h
CCP1CON
17h
97h
117h
197h
RCSTA
18h
TXSTA
98h
118h
198h
TXREG
19h
SPBRG
99h
119h
199h
RCREG
1Ah
9Ah
11Ah
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
1A0h
ADCON1
20h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
EFh
Accesses
70h-7Fh
Bank 1
1EFh
16Fh
Accesses
70h-7Fh
FFh
7Fh
Bank 0
F0h
170h
Accesses
70h-7Fh
17Fh
Bank 2
1F0h
1FFh
Bank 3
Legend:
DS41341B-page 20
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 2-6:
Indirect addr.(*)
00h
Indirect addr.(*)
80h
Indirect addr.(*)
100h
Indirect addr.(*)
180h
TMR0
01h
OPTION
81h
TMR0
101h
OPTION
181h
PCL
02h
PCL
82h
PCL
102h
PCL
182h
STATUS
03h
STATUS
83h
STATUS
103h
STATUS
183h
FSR
104h
184h
FSR
04h
FSR
84h
PORTA
05h
TRISA
85h
105h
FSR
ANSELA
PORTB
06h
TRISB
86h
106h
ANSELB
PORTC
07h
TRISC
87h
107h
PORTD(1)
08h
TRISD(1)
88h
CPSCON0
108h
ANSELD(1)
PORTE
09h
TRISE
89h
CPSCON1
109h
ANSELE(1)
189h
PCLATH
0Ah
PCLATH
8Ah
PCLATH
10Ah
PCLATH
18Ah
INTCON
0Bh
INTCON
8Bh
INTCON
10Bh
INTCON
18Bh
PIR1
0Ch
PIE1
8Ch
PMDATL
10Ch
PMCON1
18Ch
PIR2
0Dh
PIE2
8Dh
PMADRL
10Dh
Reserved
18Dh
TMR1L
0Eh
PCON
8Eh
PMDATH
10Eh
Reserved
18Eh
TMR1H
0Fh
T1GCON
8Fh
PMADRH
10Fh
Reserved
T1CON
10h
OSCCON
90h
TMR2
11h
OSCTUNE
91h
111h
191h
T2CON
12h
PR2
92h
112h
192h
186h
187h
110h
SSPADD/SSPMSK 93h
185h
188h
18Fh
190h
SSPBUF
13h
113h
193h
SSPCON
14h
SSPSTAT
94h
114h
194h
195h
CCPR1L
15h
WPUB
95h
115h
CCPR1H
16h
IOCB
96h
116h
CCP1CON
17h
97h
RCSTA
18h
TXSTA
98h
TXREG
19h
SPBRG
99h
RCREG
1Ah
General
Purpose
Register
16 Bytes
9Ah
117h
118h
119h
General
Purpose
Register
16 Bytes
11Ah
196h
197h
198h
199h
19Ah
CCPR2L
1Bh
9Bh
11Bh
19Bh
CCPR2H
1Ch
APFCON
9Ch
11Ch
19Ch
CCP2CON
1Dh
FVRCON
9Dh
11Dh
19Dh
ADRES
1Eh
9Eh
11Eh
19Eh
ADCON0
1Fh
9Fh
11Fh
19Fh
A0h
120h
1A0h
ADCON1
20h
General
Purpose
Register
80 Bytes
General
Purpose
Register
96 Bytes
EFh
Accesses
70h-7Fh
Bank 0
*
Note 1:
F0h
Bank 1
General
Purpose
Register
80 Bytes
16Fh
Accesses
70h-7Fh
FFh
7Fh
Legend:
General
Purpose
Register
80 Bytes
170h
1EFh
Accesses
70h-7Fh
17Fh
Bank 2
1F0h
1FFh
Bank 3
PORTD, TRISD, ANSELD and ANSELE are not implemented on the PIC16F726/LF726, read as 0
Preliminary
DS41341B-page 21
PIC16F72X/PIC16LF72X
TABLE 2-1:
Address
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 0
00h(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
29,38
01h
TMR0
xxxx xxxx
109,38
02h(2)
PCL
03h(2)
STATUS
IRP
RP1
RP0
TO
PD
DC
0000 0000
28,38
0001 1xxx
25,38
04h(2)
FSR
xxxx xxxx
29,38
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
52,38
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
61,38
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
71,38
08h(3)
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
78,38
09h
PORTE
RE3
RE2(3)
RE1(3)
RE0(3)
---- xxxx
83,38
0Ah(1, 2)
PCLATH
0Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
0Ch
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
0Dh
PIR2
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
16h
CCPR1H
17h
CCP1CON
18h
RCSTA
19h
TXREG
1Ah
RCREG
1Bh
---0 0000
28,38
RBIF
0000 000x
44,38
TMR2IF
TMR1IF
0000 0000
47,38
CCP2IF
---- ---0
48,38
xxxx xxxx
118,38
xxxx xxxx
118,38
TMR1ON
0000 00-0
122,38
0000 0000
125,38
T2CKPS1 T2CKPS0
-000 0000
126,38
xxxx xxxx
167,38
0000 0000
184,38
xxxx xxxx
135,38
xxxx xxxx
135,38
TOUTPS3 TOUTPS2
T1CKPS0
T1OSCEN
T1SYNC
TOUTPS1
TOUTPS0
TMR2ON
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
134,38
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
153,38
0000 0000
152,38
0000 0000
150,38
CCPR2L
xxxx xxxx
135,38
1Ch
CCPR2H
xxxx xxxx
135,38
1Dh
CCP2CON
134,38
1Eh
ADRES
1Fh
ADCON0
Legend:
Note
1:
2:
3:
4:
5:
6:
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
xxxx xxxx
103,39
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
102,39
DS41341B-page 22
Preliminary
PIC16F72X/PIC16LF72X
TABLE 2-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 1
80h(2)
INDF
81h
OPTION_REG
82h(2)
PCL
83h(2)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
xxxx xxxx
29,38
PSA
PS2
PS1
PS0
1111 1111
26,39
0000 0000
28,38
TO
PD
DC
0001 1xxx
25,38
T0SE
RP1
RP0
84h(2)
FSR
xxxx xxxx
29,38
85h
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
52,39
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
61,39
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
71,39
88h(3)
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
79,39
89h
TRISE
TRISE3(6)
TRISE2(3)
---- 1111
83,39
8Ah(1, 2)
PCLATH
8Bh(2)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
8Ch
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
8Dh
PIE2
8Eh
PCON
8Fh
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
TRISE1(3) TRISE0(3)
---0 0000
28,38
RBIF
0000 000x
44,38
TMR2IE
TMR1IE
0000 0000
45,39
CCP2IE
---- ---0
46,39
POR
BOR
27,39
T1GVAL
T1GSS1
T1GSS0
0000 0x00
123,39
90h
OSCCON
IRCF1
IRCF0
ICSL
ICSS
--10 qq--
89,39
91h
OSCTUNE
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
90,39
92h
PR2
1111 1111
125,39
93h
SSPADD(5)
0000 0000
175,39
93h
SSPMSK(4)
1111 1111
186,39
94h
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
185,39
95h
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
62,39
96h
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
62,39
97h
98h
TXSTA
99h
SPBRG
Unimplemented
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
152,39
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
154,39
9Ah
Unimplemented
9Bh
Unimplemented
9Ch
APFCON
9Dh
FVRCON
9Eh
9Fh
ADCON1
Legend:
Note
1:
2:
3:
4:
5:
6:
SSSEL
FVRRDY
FVREN
ADFVR1
Unimplemented
ADCS2
ADCS1
ADCS0
ADREF1
ADREF0
q0-- --00
51,39
107,39
0000 --00
103,39
Preliminary
DS41341B-page 23
PIC16F72X/PIC16LF72X
TABLE 2-1:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Page
Bank 2
100h(2)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
29,38
101h
TMR0
xxxx xxxx
109,38
102h(2)
PCL
103h(2)
STATUS
104h(2)
FSR
IRP
RP1
RP0
TO
PD
DC
0000 0000
28,38
0001 1xxx
25,38
xxxx xxxx
29,38
105h
Unimplemented
106h
Unimplemented
107h
Unimplemented
0--- 0000
131,39
---- 0000
132,39
108h
CPSCON0
CPSON
109h
CPSCON1
GIE
PEIE
T0IE
10Ah(1, 2) PCLATH
CPSRNG1 CPSRNG0
CPSCH3
CPSCH2
CPSOUT
T0XCS
CPSCH1
CPSCH0
---0 0000
28,38
0000 000x
44,38
187,39
10Bh(2)
INTCON
10Ch
PMDATL
xxxx xxxx
10Dh
PMADRL
xxxx xxxx
187,39
10Eh
PMDATH
--xx xxxx
187,39
10Fh
PMADRH
---x xxxx
187,39
INTE
RBIE
T0IF
INTF
RBIF
Bank 3
180h(2)
INDF
181h
OPTION_REG
182h(2)
PCL
183h(2)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
xxxx xxxx
29,38
PSA
PS2
PS1
PS0
1111 1111
26,39
0000 0000
28,38
TO
PD
DC
0001 1xxx
25,38
T0SE
RP1
RP0
184h(2)
FSR
xxxx xxxx
29,38
185h
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
53,39
186h
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
62,39
187h
188h
ANSELD
ANSD7
ANSD6
ANSD5
189h(3)
ANSELE
18Ah(1, 2) PCLATH
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
Reserved
18Bh(2)
INTCON
18Ch
PMCON1
Unimplemented
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
79,39
ANSE2
ANSE1
ANSE0
---- -111
84,39
---0 0000
28,38
RBIF
0000 000x
44,38
RD
1--- ---0
188,39
18Dh
Unimplemented
18Eh
Unimplemented
18Fh
Unimplemented
Legend:
Note
1:
2:
3:
4:
5:
6:
DS41341B-page 24
Preliminary
PIC16F72X/PIC16LF72X
2.2.2.1
STATUS Register
REGISTER 2-1:
R/W-0
IRP
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
R/W-x
R/W-x
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-5
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
Preliminary
DS41341B-page 25
PIC16F72X/PIC16LF72X
2.2.2.2
OPTION register
Note:
Timer0/WDT prescaler
External RB0/INT interrupt
Timer0
Weak pull-ups on PORTB
REGISTER 2-2:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS41341B-page 26
Bit Value
Timer0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Preliminary
PIC16F72X/PIC16LF72X
2.2.2.3
PCON Register
REGISTER 2-3:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-q
R/W-q
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.
Preliminary
DS41341B-page 27
PIC16F72X/PIC16LF72X
2.3
FIGURE 2-7:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
PC
8
PCLATH<4:0>
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
PC
GOTO, CALL
2
PCLATH<4:3>
2.4
11
OPCODE<10:0>
PCLATH
2.3.1
COMPUTED GOTO
2.3.2
EXAMPLE 2-1:
ORG 500h
PAGESEL SUB_P1 ;Select page 1
;(800h-FFFh)
CALL
SUB1_P1 ;Call subroutine in
:
;page 1 (800h-FFFh)
:
ORG
900h
;page 1 (800h-FFFh)
STACK
SUB1_P1
DS41341B-page 28
CALL OF A SUBROUTINE
IN PAGE 1 FROM PAGE 0
Preliminary
:
:
RETURN
;called subroutine
;page 1 (800h-FFFh)
;return to
;Call subroutine
;in page 0
;(000h-7FFh)
PIC16F72X/PIC16LF72X
2.5
EXAMPLE 2-2:
MOVLW
MOVWF
BANKISEL
NEXT CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
020h
FSR
020h
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
FIGURE 2-8:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1
RP0
Bank Select
From Opcode
Indirect Addressing
0
IRP
Bank Select
Location Select
00
01
10
Location Select
11
00h
180h
Data
Memory
7Fh
1FFh
Bank 0
Note:
Bank 1
Bank 2
Bank 3
Preliminary
DS41341B-page 29
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 30
Preliminary
PIC16F72X/PIC16LF72X
3.0
RESETS
FIGURE 3-1:
MCLR/VPP
Sleep
WDT
Module
WDT
Time-out
Reset
POR
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
OST/PWRT
OST
Chip_Reset
Enable PWRT
Enable OST
Note
1:
Preliminary
DS41341B-page 31
PIC16F72X/PIC16LF72X
TABLE 3-1:
POR
BOR
TO
PD
Brown-out Reset
WDT Reset
WDT Wake-up
TABLE 3-2:
Condition
STATUS
Register
PCON
Register
Power-on Reset
0000h
0001 1xxx
---- --0x
0000h
000u uuuu
---- --uu
0000h
0001 0uuu
---- --uu
WDT Reset
0000h
0000 1uuu
---- --uu
WDT Wake-up
PC + 1
uuu0 0uuu
---- --uu
Brown-out Reset
0000h
0001 1uuu
---- --u0
uuu1 0uuu
---- --uu
Condition
PC + 1
(1)
DS41341B-page 32
Preliminary
PIC16F72X/PIC16LF72X
3.1
MCLR
3.3
FIGURE 3-2:
RECOMMENDED MCLR
CIRCUIT
VDD
3.4
(Section 23.0
PIC MCU
R1
10 k
MCLR
C1
0.1 F
3.4.1
3.2
WDT OSCILLATOR
Note:
The on-chip POR circuit holds the chip in Reset until VDD
has reached a high enough level for proper operation. A
maximum rise time for VDD is required. See
Section 23.0 Electrical Specifications for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until VDD reaches VBOR (see Section 3.5
Brown-Out Reset (BOR)).
Preliminary
DS41341B-page 33
PIC16F72X/PIC16LF72X
3.4.2
WDT CONTROL
FIGURE 3-1:
T1GSS = 11
TMR1GE
From TMR0
Clock Source
WDTE
Low-Power
WDT OSC
0
Divide by
512
Postscaler
1
8
PS<2:0>
TO TMR0
PSA
1
WDT Reset
To T1G
WDTE
TABLE 3-1:
WDT STATUS
Conditions
WDT
WDTE = 0
Cleared
CLRWDT Command
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
DS41341B-page 34
Preliminary
PIC16F72X/PIC16LF72X
3.5
FIGURE 3-3:
Note:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
64 ms(1)
VDD
Internal
Reset
VBOR
< 64 ms
64 ms(1)
VDD
VBOR
Internal
Reset
Note 1:
64 ms(1)
Preliminary
DS41341B-page 35
PIC16F72X/PIC16LF72X
3.6
Time-out Sequence
3.7
TABLE 3-2:
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
Sleep
TPWRT + 1024
TOSC
1024 TOSC
TPWRT + 1024
TOSC
1024 TOSC
1024 TOSC
TPWRT
TPWRT
Oscillator Configuration
XT, HS,
LP(1)
TABLE 3-3:
POR
BOR
TO
PD
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
Condition
DS41341B-page 36
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 3-4:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 3-5:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
FIGURE 3-6:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal Reset
Preliminary
DS41341B-page 37
PIC16F72X/PIC16LF72X
TABLE 3-4:
Register
W
Address
Power-on Reset/
Brown-out Reset(1)
MCLR Reset/
WDT Reset
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
00h/80h/
100h/180h
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0
01h/101h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h/
102h/182h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h/
103h/183h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h/
104h/184h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTB
06h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTC
07h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTD(6)
08h
xxxx xxxx
xxxx xxxx
uuuu uuuu
PORTE
09h
---- xxxx
---- xxxx
---- uuuu
PCLATH
0Ah/8Ah/
10Ah/18Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh/
10Bh/18Bh
0000 000x
0000 000x
uuuu uuuu(2)
PIR1
0Ch
0000 0000
0000 0000
uuuu uuuu(2)
PIR2
0Dh
---- ---0
---- ---0
---- ---u
TMR1L
0Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
0Fh
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
10h
0000 00-0
uuuu uu-u
uuuu uu-u
TMR2
11h
0000 0000
0000 0000
uuuu uuuu
T2CON
12h
-000 0000
-000 0000
-uuu uuuu
SSPBUF
13h
xxxx xxxx
xxxx xxxx
uuuu uuuu
SSPCON
14h
0000 0000
0000 0000
uuuu uuuu
CCPR1L
15h
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR1H
16h
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP1CON
17h
--00 0000
--00 0000
--uu uuuu
RCSTA
18h
0000 000x
0000 000x
uuuu uuuu
TXREG
19h
0000 0000
0000 0000
uuuu uuuu
RCREG
1Ah
0000 0000
0000 0000
uuuu uuuu
CCPR2L
1Bh
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCPR2H
1Ch
xxxx xxxx
xxxx xxxx
uuuu uuuu
CCP2CON
1Dh
--00 0000
--00 0000
--uu uuuu
Legend:
Note 1:
2:
3:
4:
5:
6:
DS41341B-page 38
Preliminary
PIC16F72X/PIC16LF72X
TABLE 3-4:
Register
ADRES
ADCON0
Power-on Reset/
Brown-out Reset(1)
MCLR Reset/
WDT Reset
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
1Fh
--00 0000
--00 0000
--uu uuuu
81h/181h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
1111 1111
1111 1111
uuuu uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
OPTION_REG
TRISC
87h
1111 1111
1111 1111
uuuu uuuu
TRISD(6)
88h
1111 1111
1111 1111
uuuu uuuu
TRISE
89h
---- 1111
---- 1111
---- uuuu
PIE1
8Ch
0000 0000
0000 0000
uuuu uuuu
PIE2
8Dh
---- ---0
---- ---0
---- ---u
PCON
8Eh
---- --uu(1,5)
---- --uu
T1GCON
8Fh
0000 0x00
uuuu uxuu
uuuu uxuu
OSCCON
90h
--10 qq--
--10 qq--
--uu qq--
OSCTUNE
91h
--00 0000
--uu uuuu
--uu uuuu
PR2
92h
1111 1111
1111 1111
uuuu uuuu
SSPADD
93h
0000 0000
0000 0000
uuuu uuuu
SSPMSK
93h
1111 1111
1111 1111
uuuu uuuu
SSPSTAT
94h
0000 0000
0000 0000
uuuu uuuu
WPUB
95h
1111 1111
1111 1111
uuuu uuuu
IOCB
96h
0000 0000
0000 0000
uuuu uuuu
TXSTA
98h
0000 -010
0000 -010
uuuu -uuu
SPBRG
99h
0000 0000
0000 0000
uuuu uuuu
APFCON
9Ch
---- --00
---- --00
---- --uu
FVRCON
9Dh
q000 --00
q000 --00
uuuu --uu
ADCON1
9Fh
-000 --00
-000 --00
-uuu --uu
CPSCON0
108h
0--- 0000
0--- 0000
u--- uuuu
CPSCON1
109h
---- 0000
---- 0000
---- uuuu
PMDATL
10Ch
xxxx xxxx
xxxx xxxx
uuuu uuuu
PMADRL
10Dh
xxxx xxxx
xxxx xxxx
uuuu uuuu
PMDATH
10Eh
--xx xxxx
--xx xxxx
--uu uuuu
PMADRH
10Fh
---x xxxx
---x xxxx
---u uuuu
ANSELA
185h
--11 1111
--11 1111
--uu uuuu
ANSELB
186h
--11 1111
--11 1111
--uu uuuu
188h
1111 1111
1111 1111
uuuu uuuu
189h
---- -111
---- -111
---- -uuu
18Ch
1--- ---0
1--- ---0
u--- ---u
ANSELD
(6)
ANSELE
PMCON1
Legend:
Note 1:
2:
3:
4:
5:
6:
Preliminary
DS41341B-page 39
PIC16F72X/PIC16LF72X
TABLE 3-5:
STATUS
Register
PCON
Register
Power-on Reset
0000h
0001 1xxx
---- --0x
0000h
000u uuuu
---- --uu
0000h
0001 0uuu
---- --uu
WDT Reset
0000h
0000 uuuu
---- --uu
WDT Wake-up
PC + 1
uuu0 0uuu
---- --uu
Brown-out Reset
0000h
0001 1xxx
---- --10
uuu1 0uuu
---- --uu
Condition
PC + 1
(1)
TABLE 3-6:
Name
STATUS
PCON
Legend:
Note 1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IRP
RP1
RP0
TO
PD
Bit 0
Value on
POR, BOR
Value on
all other
Resets(1)
DC
0001 1xxx
000q quuu
POR
BOR
---- --uu
Bit 1
u = unchanged, x = unknown, - = unimplemented bit, reads as 0, q = value depends on condition. Shaded cells are not
used by Resets.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41341B-page 40
Preliminary
PIC16F72X/PIC16LF72X
4.0
INTERRUPTS
FIGURE 4-1:
INTERRUPT LOGIC
IOC-RB0
IOCB0
IOC-RB1
IOCB1
IOC-RB2
IOCB2
IOC-RB3
IOCB3
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
SSPIF
SSPIE
TXIF
TXIE
RCIF
RCIE
TMR2IF
TMR2IE
Interrupt to CPU
INTF
INTE
RBIF
RBIE
TMR1IF
TMR1IE
ADIF
ADIE
PEIE
TMR1GIF
TMR1GIE
GIE
CCP1IF
CCP1IE
CCP2IF
CCP2IE
Note 1:
Preliminary
DS41341B-page 41
PIC16F72X/PIC16LF72X
4.1
Operation
The INTCON, PIR1 and PIR2 registers record individual interrupts via Interrupt Flag bits. Interrupt Flag bits
will be set, regardless of the status of the GIE, PEIE
and individual Interrupt Enable bits.
4.2
FIGURE 4-2:
Interrupt Latency
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT (3)
(4)
INT pin
(1)
(1)
INTF flag
(INTCON<1>)
(5)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
2:
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
4:
For minimum width of INT pulse, refer to AC specifications in Section 23.0 Electrical Specifications.
5:
DS41341B-page 42
Preliminary
PIC16F72X/PIC16LF72X
4.3
4.4
INT Pin
4.5
Context Saving
EXAMPLE 4-1:
MOVWF
SWAPF
W_TEMP
STATUS,W
BANKSEL
MOVWF
MOVF
MOVWF
:
:(ISR)
:
BANKSEL
MOVF
MOVWF
SWAPF
STATUS_TEMP
STATUS_TEMP
PCLATH,W
PCLATH_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
STATUS_TEMP
PCLATH_TEMP,W
PCLATH
STATUS_TEMP,W
Preliminary
DS41341B-page 43
PIC16F72X/PIC16LF72X
4.5.1
INTCON REGISTER
Note:
REGISTER 4-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE(1)
T0IF(2)
INTF
RBIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
DS41341B-page 44
Preliminary
PIC16F72X/PIC16LF72X
4.5.2
PIE1 REGISTER
REGISTER 4-2:
Note:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
x = Bit is unknown
DS41341B-page 45
PIC16F72X/PIC16LF72X
4.5.3
PIE2 REGISTER
REGISTER 4-3:
Note:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
DS41341B-page 46
Preliminary
x = Bit is unknown
PIC16F72X/PIC16LF72X
4.5.4
PIR1 REGISTER
REGISTER 4-4:
Note:
R/W-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Preliminary
DS41341B-page 47
PIC16F72X/PIC16LF72X
4.5.5
PIR2 REGISTER
REGISTER 4-5:
Note:
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-1
Unimplemented: Read as 0
bit 0
TABLE 4-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
CCP2IF
---- ---0
---- ---0
OPTION_REG
Legend:
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare and PWM.
DS41341B-page 48
Preliminary
PIC16F72X/PIC16LF72X
5.0
Preliminary
DS41341B-page 49
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 50
Preliminary
PIC16F72X/PIC16LF72X
6.0
I/O PORTS
6.1
REGISTER 6-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
SSSEL
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0.
bit 1
bit 0
Preliminary
x = Bit is unknown
DS41341B-page 51
PIC16F72X/PIC16LF72X
6.2
Note:
EXAMPLE 6-1:
REGISTER 6-2:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
ANSELA
ANSELA
TRISA
0Ch
TRISA
INITIALIZING PORTA
;
;Init PORTA
;
;digital I/O
;
;Set RA<3:2> as inputs
;and set RA<7:4,1:0>
;as outputs
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 6-3:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
DS41341B-page 52
Preliminary
PIC16F72X/PIC16LF72X
6.2.1
ANSELA REGISTER
REGISTER 6-4:
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
ANSA<5:0>: Analog Select between Analog or Digital Function on pins RA<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
Preliminary
DS41341B-page 53
PIC16F72X/PIC16LF72X
6.2.2
6.2.2.6
6.2.2.1
RA0/AN0/SS/VCAP
Figure 6-4 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 6-1 shows the diagram for this pin. This pin is
configurable to function as one of the following:
RA6/OSC2/CLKOUT/VCAP
Figure 6-5 shows the diagram for this pin. This pin is
configurable to function as one of the following:
RA1/AN1
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
6.2.2.3
6.2.2.7
6.2.2.2
RA5/AN4/CPS7/SS/VCAP
6.2.2.8
RA7/OSC1/CLKIN
Figure 6-6 shows the diagram for this pin. This pin is
configurable to function as one of the following:
RA2/AN2
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
6.2.2.4
RA3/AN3/VREF
Figure 6-2 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose input
an analog input for the ADC
a voltage reference input for the ADC
6.2.2.5
RA4/CPS6/T0CKI
Figure 6-3 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a capacitive sensing input
a clock input for Timer0
The Timer0 clock input function works independently
of any TRIS register setting. Effectively, if TRISA4 = 0,
the PORTA4 register bit will output to the pad and
Clock Timer0 at the same time.
DS41341B-page 54
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-1:
PIC16F72X only
To Voltage Regulator
VCAPEN = 00
VDD
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
CK Q
RD
TRISA
ANSA0
RD
PORTA
To SSP SS Input
To A/D Converter
Preliminary
DS41341B-page 55
PIC16F72X/PIC16LF72X
FIGURE 6-2:
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
CK Q
RD
TRISA
ANSAx
RD
PORTA
To A/D Converter
FIGURE 6-3:
Data Bus
D
WR
PORTA
I/O Pin
CK Q
D
WR
TRISA
VSS
CK Q
RD
TRISA
ANSA4
RD
PORTA
DS41341B-page 56
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-4:
PIC16F72X only
To Voltage Regulator
VCAPEN = 01
VDD
Data Bus
D
WR
PORTA
Q
I/O Pin
CK Q
D
WR
TRISA
VSS
CK Q
RD
TRISA
ANSA5
RD
PORTA
To SSP SS Input
To A/D Converter
To Cap Sensor
Preliminary
DS41341B-page 57
PIC16F72X/PIC16LF72X
FIGURE 6-5:
PIC16F72X only
To Voltage Regulator
VCAPEN = 10
Oscillator
Circuit
CLKOUT(1)
Enable
FOSC/4
D
WR
PORTA
VDD
RA7/OSC1
Data Bus
I/O Pin
CK Q
VSS
D
WR
TRISA
CK Q
RD
TRISA
FOSC = LP or XT or HS
(00X OR 010)
RD
PORTA
FIGURE 6-6:
Data Bus
VDD
I/O Pin
D
WR
PORTA
CK Q
D
WR
TRISA
VSS
CK Q
RD
TRISA
OSC = INTOSC or
INTOSCIO
RD
PORTA
DS41341B-page 58
Preliminary
PIC16F72X/PIC16LF72X
TABLE 6-1:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
0000 0000
0000 0000
-000 --00
Name
ADCON1
ADCS2
ADCS1
ADCS0
ADREF1
ADREF0
-000 --00
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
APFCON
SSSEL
CCP2SEL
---- --00
---- --00
CPSCON0
CPSON
CPSCON1
CONFIG2(1)
OPTION_REG
PORTA
SSPCON
TRISA
Legend:
Note 1:
RBPU
INTEDG
CPSRNG1 CPSRNG0
CPSCH3
VCAPEN1 VCAPEN0
T0CS
T0SE
CPSCH2
CPSOUT
T0XCS
0--- 0000
0--- 0000
CPSCH1
CPSCH0
---- 0000
---- 0000
PSA
PS2
PS1
PS0
1111 1111
1111 1111
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx xxxx
xxxx xxxx
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTA.
PIC16F72X only.
Preliminary
DS41341B-page 59
PIC16F72X/PIC16LF72X
6.3
6.3.1
EXAMPLE 6-2:
PORTB
PORTB
ANSELB
ANSELB
TRISB
B11110000
MOVWF
TRISB
Note:
6.3.2
WEAK PULL-UPS
6.3.3
INTERRUPT-ON-CHANGE
INITIALIZING PORTB
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
ANSELB REGISTER
;
;Init PORTB
;Make RB<7:0> digital
;
;Set RB<7:4> as inputs
;and RB<3:0> as outputs
;
b)
DS41341B-page 60
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 6-5:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 6-6:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Preliminary
DS41341B-page 61
PIC16F72X/PIC16LF72X
REGISTER 6-7:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
2:
x = Bit is unknown
REGISTER 6-8:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 6-9:
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
ANSB<5:0>: Analog Select between Analog or Digital Function on Pins RB<5:0>, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS41341B-page 62
Preliminary
PIC16F72X/PIC16LF72X
6.3.4
6.3.4.6
6.3.4.1
RB0/AN12/CPS0/INT
Figure 6-7 shows the diagram for this pin. This pin is
configurable to function as one of the following:
6.3.4.2
Figure 6-10 shows the diagram for this pin. This pin is
configurable to function as one of the following:
6.3.4.7
RB6/ICSPCLK
Figure 6-11 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
In-Circuit Serial Programming clock
6.3.4.8
RB1/AN10/CPS1
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
6.3.4.3
RB5/AN13/CPS5/T1G
RB7/ICSPDAT
Figure 6-12 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
In-Circuit Serial Programming data
RB2/AN8/CPS2
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
6.3.4.4
RB3/AN9/CPS3/CCP2
Figure 6-9 shows the diagram for this pin. This pin is
configurable to function as one of the following:
6.3.4.5
RB4/AN11/CPS4
Figure 6-8 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
a capacitive sensing input
Preliminary
DS41341B-page 63
PIC16F72X/PIC16LF72X
FIGURE 6-7:
Data Bus
D
WR
WPUB
CK
VDD
Weak
D
WR
PORTB
Q
I/O Pin
CK Q
D
WR
TRISB
VDD
RBPU
RD
WPUB
VSS
CK Q
RD
TRISB
ANSB0
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
To External Interrupt Logic
To A/D Converter
To Cap Sensor
DS41341B-page 64
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-8:
D
WR
WPUB
CK
VDD
Weak
VDD
RBPU
RD
WPUB
D
WR
PORTB
Q
I/O Pin
CK Q
D
WR
TRISB
VSS
CK Q
RD
TRISB
ANSB<4,2,1>
RD
PORTB
D
WR
IOCB
CK Q
D
EN
RD
IOCB
Q3
To A/D Converter
To Cap Sensor
EN
Interrupt-onChange
RD PORTB
Preliminary
DS41341B-page 65
PIC16F72X/PIC16LF72X
FIGURE 6-9:
D
WR
WPUB
CK
Q
Q
Weak
CCP2OUT
Enable
VDD
RBPU
RD
WPUB
CCP2OUT
D
WR
PORTB
VDD
1
0
I/O Pin
CK Q
VSS
D
WR
TRISB
CK Q
RD
TRISB
ANSB<5,3>
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
To CCP2(1)
To A/D Converter
To Cap Sensor
Note 1:
DS41341B-page 66
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-10:
D
WR
WPUB
CK
Q
Q
Weak
CCP2OUT
Enable
VDD
RBPU
RD
WPUB
CCP2OUT
D
WR
PORTB
VDD
1
0
I/O Pin
CK Q
VSS
D
WR
TRISB
CK Q
RD
TRISB
ANSB<5,3>
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
To Timer1 Gate
To A/D Converter
To Cap Sensor
Preliminary
DS41341B-page 67
PIC16F72X/PIC16LF72X
FIGURE 6-11:
ICSP MODE
DEBUG
Data Bus
D
WR
WPUB
CK
VDD
Weak
VDD
RBPU
PORT_ICDCLK
RD
WPUB
1
D
WR
PORTB
Q
0
D
WR
TRISB
I/O Pin
CK Q
VSS
Q
0
CK Q
RD
TRISB
TRIS_ICDCLK
RD
PORTB
D
WR
IOCB
Q
Q
CK Q
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
ICSPCLK
DS41341B-page 68
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-12:
ICSP MODE
DEBUG
Data Bus
D
WR
WPUB
CK
VDD
Weak
VDD
RBPU
PORT_ICDDAT
RD
WPUB
1
D
WR
PORTB
Q
0
D
WR
TRISB
I/O Pin
CK Q
VSS
Q
0
CK Q
1
RD
TRISB
TRIS_ICDDAT
RD
PORTB
D
WR
IOCB
CK Q
D
EN
RD
IOCB
Q3
D
EN
Interrupt-onChange
RD PORTB
ICSPDAT_IN
Preliminary
DS41341B-page 69
PIC16F72X/PIC16LF72X
TABLE 6-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
SSSEL
CCP2SEL
---- --00
---- --00
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CPSCON0
CPSON
CPSOUT
T0XCS
0--- 0000
0--- 0000
CPSCON1
CPSCH1
CPSCH0
---- 0000
---- 0000
0000 000X
INTCON
CPSRNG1 CPSRNG0
CPSCH3
CPSCH2
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
0000 0000
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
PORTB
T1GCON
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
xxxx xxxx
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
uuuu uxuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
WPUB
WPUB7
WPUB6
WPUB5
WPUB4
WPUB3
WPUB2
WPUB1
WPUB0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by Port B.
DS41341B-page 70
Preliminary
PIC16F72X/PIC16LF72X
6.4
REGISTER 6-10:
EXAMPLE 6-3:
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTC
PORTC
PORTC
TRISC
B00001100
TRISC
;
;Init PORTC
;
;Set RC<3:2> as inputs
;and set RC<7:4,1:0>
;as outputs
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
REGISTER 6-11:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Preliminary
DS41341B-page 71
PIC16F72X/PIC16LF72X
6.4.1
RC0/T1OSO/T1CKI
6.4.8
RC7/RX/DT
Figure 6-13 shows the diagram for this pin. This pin is
configurable to function as one of the following:
Figure 6-20 shows the diagram for this pin. This pin is
configurable to function as one of the following:
6.4.2
RC1/T1OSI/CCP2
Figure 6-14 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a Timer1 oscillator input
a Capture 2 input, Compare 2 output, and PWM2
output
Note:
6.4.3
RC2/CCP1
Figure 6-15 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a Capture 1 input, Compare 1 output, and PWM1
output
6.4.4
RC3/SCK/SCL
Figure 6-16 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI clock
an I2C clock
6.4.5
RC4/SDI/SDA
Figure 6-17 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI data input
an I2C data I/O
6.4.6
RC5/SDO
Figure 6-18 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
a SPI data output
6.4.7
RC6/TX/CK
Figure 6-19 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an asynchronous serial output
a synchronous clock I/O
DS41341B-page 72
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-13:
Oscillator
Circuit
Data Bus
VDD
RC1/T1OSI
D
WR
PORTC
Q
I/O Pin
CK Q
D
WR
TRISC
VSS
CK Q
RD
TRISC
T1OSCEN
RD
PORTC
To Timer1 CLK Input
FIGURE 6-14:
Oscillator
Circuit
Data Bus
CCP2OUT
D
WR
PORTC
1
0
I/O Pin
CK Q
D
WR
TRISC
VDD
RC0/T1OSO
VSS
CK Q
RD
TRISC
T1OSCEN
RD
PORTC
To CCP2(1) Input
Note 1:
Preliminary
DS41341B-page 73
PIC16F72X/PIC16LF72X
FIGURE 6-15:
VDD
Data Bus
CCP1OUT
D
WR
PORTC
1
0
I/O Pin
CK Q
D
WR
TRISC
VSS
CK Q
RD
TRISC
RD
PORTC
To CCP1 Input
FIGURE 6-16:
Data Bus
VDD
SSPEN
0
1
D
WR
PORTC
(2)
I/O Pin
CK Q
VSS
SCL
D
WR
TRISC
CK Q
RD
TRISC
To SSP SPI
Clock Input
1
0
RD
PORTC
0
1
SSPEN
SSPM = I2C MODE
To SSP I2C
SCL Input
I2C(1)
Note 1:
2:
DS41341B-page 74
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 6-17:
SSPEN
SSPM = I2C MODE
VDD
Data Bus
1
D
WR
PORTC
(2)
I/O Pin
CK Q
VSS
D
WR
TRISC
CK Q
RD
TRISC
To SSP SPI
Data Input
1
0
RD
PORTC
0
1
To SSP I2C
SDA Input
I2C(1)
Note 1:
2:
FIGURE 6-18:
SSPEN
SSPM = SPI MODE
VDD
Data Bus
SDO
D
WR
PORTC
1
0
I/O Pin
CK Q
VSS
D
WR
TRISC
SDO
EN
CK Q
RD
TRISC
RD
PORTC
Preliminary
DS41341B-page 75
PIC16F72X/PIC16LF72X
FIGURE 6-19:
USART_CK
VDD
1
Data Bus
D
WR
PORTC
0
I/O Pin
CK Q
D
WR
TRISC
VSS
CK Q
RD
TRISC
RD
PORTC
SPEN
TXEN
CSRC
SYNC
To USART
Sync Clock Input
FIGURE 6-20:
VDD
Data Bus
USART_DT
D
WR
PORTC
1
0
I/O Pin
CK Q
D
WR
TRISC
VSS
CK Q
RD
TRISC
RD
PORTC
SPEN
SYNC
TXEN
SREN
CREN
To USART Data Input
DS41341B-page 76
Preliminary
PIC16F72X/PIC16LF72X
TABLE 6-3:
Name
Bit 6
APFCON
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP2CON
Bit 5
Bit 4
Bit 3
Bit 2
Value on
POR, BOR
Value on all
other
Resets
Bit 1
Bit 0
SSSEL
CCP2SEL
---- --00
---- --00
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
xxxx xxxx
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
0000 0000
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1SYNC
TMR1ON
0000 00-0
uuuu uu-u
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
T1CKPS0 T1OSCEN
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by Port B.
Preliminary
DS41341B-page 77
PIC16F72X/PIC16LF72X
6.5
EXAMPLE 6-4:
REGISTER 6-12:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
6.5.1
INITIALIZING PORTD
PORTD
PORTD
ANSELD
ANSELD
TRISD
B00001100
TRISD
;
;Init PORTD
;Make PORTD digital
;
;Set RD<3:2> as inputs
;and set RD<7:4,1:0>
;as outputs
ANSELD REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
Note 1:
x = Bit is unknown
DS41341B-page 78
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 6-13:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Note 1:
REGISTER 6-14:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
ANSD7
ANSD6
ANSD5
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
ANSD<7:0>: Analog Select between Analog or Digital Function on Pins RD<7:0>, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELD register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as 0.
Preliminary
DS41341B-page 79
PIC16F72X/PIC16LF72X
6.5.6
Note:
6.5.2
RD4/CPS12
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
RD0/CPS8
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.7
RD5/CPS13
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.3
RD1/CPS9
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.8
RD6/CPS14
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.4
RD2/CPS10
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.9
RD7/CPS15
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
6.5.5
RD3/CPS11
Figure 6-21 shows the diagram for these pins. They are
configurable to function as one of the following:
a general purpose I/O
a capacitive sensing input
FIGURE 6-21:
Data Bus
D
WR
PORTD
I/O Pin
CK Q
D
WR
TRISD
VSS
CK Q
RD
TRISD
ANSD<7:0>
RD
PORTD
To Cap Sensor
Note:
DS41341B-page 80
Preliminary
PIC16F72X/PIC16LF72X
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
TABLE 6-4:
Name
Bit 7
Bit 6
ANSELD
ANSD7
ANSD6
ANSD3
CPSCON0
CPSON
CPSRNG1
CPSCON1
CPSCH3
CPSCH2
CPSCH1
RD6
RD5
RD4
PORTD
RD7
TRISD
TRISD7
Bit 5
Bit 4
ANSD5 ANSD4
Bit 3
Bit 2
Value on
POR, BOR
Value on
all other
Resets
Bit 1
Bit 0
ANSD2
ANSD1
ANSD0
CPSRNG0
CPSOUT
T0XCS
RD3
RD2
RD1
RD0
TRISD3
TRISD2
TRISD1
TRISD0
Legend:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTD.
Note 1: These registers are not implemented on the PIC16F722/723/726/PIC16LF722/723/726 devices, read as 0.
Preliminary
DS41341B-page 81
PIC16F72X/PIC16LF72X
6.6
EXAMPLE 6-5:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTE
PORTE
PORTE
ANSELE
ANSELE
TRISE
B00001100
TRISE
DS41341B-page 82
;
;Init PORTE
;
;digital I/O
;
;Set RE<2> as an input
;and set RE<1:0>
;as outputs
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 6-15:
U-0
U-0
U-0
R-x
R/W-x
R/W-x
R/W-x
RE3
RE2(1)
RE1(1)
RE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
x = Bit is unknown
REGISTER 6-16:
U-0
U-0
U-0
U-0
R-1
R/W-1
R/W-1
R/W-1
TRISE3
TRISE2(1)
TRISE1(1)
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2-0
Note 1:
x = Bit is unknown
Preliminary
DS41341B-page 83
PIC16F72X/PIC16LF72X
REGISTER 6-17:
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
ANSE2(2)
ANSE1(2)
ANSE0(2)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-3
Unimplemented: Read as 0
bit 2-0
ANSE<2:0>: Analog Select between Analog or Digital Function on Pins RE<2:0>, respectively
0 = Digital I/O. Pin is assigned to port or Digital special function.
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
Note 1:
2:
When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
ANSELE register is not implemented on the PIC16F722/723/726/PIC16LF722/723/726. Read as 0
TABLE 6-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ANSELE
ANSE2
ANSE1
ANSE0
---- -111
---- -111
PORTE
RE3
RE2
RE1
RE0
---- xxxx
---- xxxx
TRISE
TRISE1(1)
TRISE0(1)
---- 1111
---- 1111
Legend:
Note 1:
2:
TRISE3(2) TRISE2(1)
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by PORTE
These registers are not implemented on the PIC16F722/723/726/PIC16LF722/723/726 devices, read as 0.
This bit is always 1 as RE3 is input only.
DS41341B-page 84
Preliminary
PIC16F72X/PIC16LF72X
6.6.1
RE0/AN5(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
Note 1: RE0/AN5
is
available
on
PIC16F724/LF724 and PIC16F727/LF727
only.
6.6.2
RE1/AN6(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
Note 1: RE1/AN6
is
available
on
PIC16F724/LF724 and PIC16F727/LF727
only.
6.6.3
RE2/AN7(1)
Figure 6-22 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose I/O
an analog input for the ADC
Note 1: RE2/AN7
is
available
on
PIC16F724/LF724 and PIC16F727/LF727
only.
6.6.4
RE3/MCLR/VPP
Figure 6-23 shows the diagram for this pin. This pin is
configurable to function as one of the following:
a general purpose input
as Master Clear Reset with weak pull-up
a programming voltage reference input
Preliminary
DS41341B-page 85
PIC16F72X/PIC16LF72X
FIGURE 6-22:
Data Bus
D
WR
PORTE
I/O Pin
CK Q
D
WR
TRISE
VSS
CK Q
RD
TRISE
ANSE<0:2>
RD
PORTE
To A/D Converter
Note:
FIGURE 6-23:
High-Voltage
Detect
I/O Pin
MCLR Circuit
MCLR
Pulse Filter
VSS
Data Bus
RD
TRISE
VSS
RD
PORTE
Power for Programming Flash
DS41341B-page 86
Preliminary
PIC16F72X/PIC16LF72X
7.0
OSCILLATOR MODULE
7.1
Overview
1.
2.
3.
4.
5.
6.
7.
8.
FIGURE 7-1:
FOSC<2:0>
(Configuration Word 1)
External Oscillator
OSC2
Sleep
OSC1
Internal Oscillator
IRCF<1:0>
(OSCCON Register)
500 kHz
INTOSC
16 MHz/500 kHz
1
Postscaler
8 MHz/250 kHz
4 MHz/125 kHz
2 MHz/62.5 kHz
11
10
MUX
MUX
32x
PLL
System Clock
(CPU and Peripherals)
01
00
PLLEN
(Configuration Word 1)
Preliminary
DS41341B-page 87
PIC16F72X/PIC16LF72X
7.2
7.3.2
7.3
7.3.1
16 MHz
8 MHz (Default after Reset)
4 MHz
2 MHz
500 kHz
250 kHz (Default after Reset)
125 kHz
62.5 kHz
Note:
DS41341B-page 88
Preliminary
PIC16F72X/PIC16LF72X
7.4
Oscillator Control
REGISTER 7-1:
U-0
U-0
R/W-1
R/W-0
R-q
R-q
U-0
U-0
IRCF1
IRCF0
ICSL
ICSS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
Unimplemented: Read as 0
bit 5-4
bit 3
bit 2
bit 1-0
Unimplemented: Read as 0
Preliminary
DS41341B-page 89
PIC16F72X/PIC16LF72X
7.5
Oscillator Tuning
REGISTER 7-2:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
00 0001 =
00 0000 = Oscillator module is running at the factory-calibrated frequency.
11 1111 =
DS41341B-page 90
Preliminary
PIC16F72X/PIC16LF72X
7.6
7.6.1
7.6.2
FIGURE 7-3:
EC MODE
PIC MCU
FIGURE 7-2:
Clock from
Ext. System
PIC MCU
I/O
Note 1:
7.6.3
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
OSC1/CLKIN
C1
Quartz
Crystal
C2
RS(1)
RF(2)
Sleep
OSC2/CLKOUT
Note 1:
2:
OSC2/CLKOUT(1)
To Internal
Logic
Preliminary
DS41341B-page 91
PIC16F72X/PIC16LF72X
FIGURE 7-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
FIGURE 7-5:
EXTERNAL RC MODES
VDD
PIC MCU
REXT
PIC MCU
OSC1/CLKIN
Internal
Clock
OSC1/CLKIN
CEXT
C1
To Internal
Logic
RP(3)
C2 Ceramic
RS(1)
Resonator
RF(2)
VSS
Sleep
FOSC/4 or
I/O(2)
OSC2/CLKOUT
Note 1:
2:
7.6.4
EXTERNAL RC MODES
TABLE 7-1:
OSC2/CLKOUT(1)
Value on
all other
Resets(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CONFIG1(1)
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
OSCCON
IRCF1
IRCF0
ICSL
ICSS
--10 qq--
--10 qq--
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
--uu uuuu
OSCTUNE
Legend:
Note 1:
x = unknown, u = unchanged, = unimplemented locations read as 0. Shaded cells are not used by oscillators.
See Configuration Word 1 (Register 8-1) for operation of all bits.
DS41341B-page 92
Preliminary
PIC16F72X/PIC16LF72X
8.0
DEVICE CONFIGURATION
8.1
REGISTER 8-1:
Configuration Words
R/P-1
R/P-1
U-1(4)
R/P-1
R/P-1
R/P-1
DEBUG
PLLEN
BORV
BOREN1
BOREN0
bit 15
bit 8
U-1(4)
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP
MCLRE
PWRTE
WDTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 13
bit 12
bit 11
Unimplemented: Read as 1
bit 10
bit 9-8
bit 7
Unimplemented: Read as 1
bit 6
bit 5
bit 4
bit 3
Note 1:
2:
3:
4:
Preliminary
DS41341B-page 93
PIC16F72X/PIC16LF72X
REGISTER 8-1:
bit 2-0
Note 1:
2:
3:
4:
REGISTER 8-2:
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
U-1(1)
bit 15
bit 8
U-1(1)
U-1(1)
R/P-1
R/P-1
U-1(1)
U-1(1)
U-1(1)
U-1(1)
VCAPEN1
VCAPEN0
bit 7
bit 0
Legend:
P = Programmable bit
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 13-6
Unimplemented: Read as 1
bit 5-4
bit 3-0
Unimplemented: Read as 1
Note 1:
x = Bit is unknown
DS41341B-page 94
Preliminary
PIC16F72X/PIC16LF72X
8.2
Code Protection
8.3
User ID
Preliminary
DS41341B-page 95
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 96
Preliminary
PIC16F72X/PIC16LF72X
9.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 9-1:
0000
AN1
0001
AN2
0010
AN3
0011
AN4
0100
AN5
0101
AN6
0110
AN7
0111
AN8
1000
AN9
1001
AN10
1010
AN11
1011
AN12
1100
AN13
1101
Reserved
1110
FVREF
1111
ADREF = 10
ADC
8
GO/DONE
ADRES
ADON
VSS
CHS<3:0>
Preliminary
DS41341B-page 97
PIC16F72X/PIC16LF72X
9.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Results formatting
9.1.1
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 23.0 Electrical Specifications for
more information. Table 9-1 gives examples of appropriate ADC clock selections.
Note:
PORT CONFIGURATION
9.1.2
CHANNEL SELECTION
9.1.3
9.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)
DS41341B-page 98
Preliminary
PIC16F72X/PIC16LF72X
TABLE 9-1:
ADC
Clock Source
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns(2)
125 ns(2)
250 ns(2)
500 ns(2)
2.0 s
100
200 ns
(2)
250 ns
(2)
(2)
1.0 s
4.0 s
400 ns
(2)
0.5 s
1.0 s
2.0 s
8.0 s(3)
Fosc/4
(2)
500 ns
Fosc/8
001
Fosc/16
101
800 ns
1.0 s
2.0 s
4.0 s
16.0 s(3)
Fosc/32
010
1.6 s
2.0 s
4.0 s
8.0 s(3)
32.0 s(3)
Fosc/64
110
3.2 s
4.0 s
16.0 s
64.0 s(3)
FRC
x11
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
Legend:
Note 1:
2:
3:
4:
8.0 s
(3)
(3)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
1.0-6.0 s(1,4)
FIGURE 9-2:
Tcy to TAD
TAD0
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
Preliminary
DS41341B-page 99
PIC16F72X/PIC16LF72X
9.1.5
INTERRUPTS
9.2.3
9.2
9.2.1
ADC Operation
STARTING A CONVERSION
Note:
9.2.2
9.2.4
COMPLETION OF A CONVERSION
9.2.5
TERMINATING A CONVERSION
DS41341B-page 100
Preliminary
PIC16F72X/PIC16LF72X
9.2.6
EXAMPLE 9-1:
2.
3.
4.
5.
6.
7.
8.
Configure Port:
Disable pin output driver (Refer to the TRIS
register)
Configure pin as analog (Refer to the ANSEL
register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
A/D CONVERSION
Preliminary
DS41341B-page 101
PIC16F72X/PIC16LF72X
9.2.7
REGISTER 9-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-2
bit 1
bit 0
DS41341B-page 102
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 9-2:
U-0
R/W-0
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
ADCS2
ADCS1
ADCS0
ADREF1
ADREF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
REGISTER 9-3:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
Preliminary
DS41341B-page 103
PIC16F72X/PIC16LF72X
9.3
EQUATION 9-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
(2
)1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n+1
(2
)1
T C = C HOLD ( R IC + R SS + R S ) ln(1/511)
= 10pF ( 1k + 7k + 10k ) ln(0.001957)
= 1.12 s
Therefore:
T ACQ = 2S + 1.12 S + [ ( 50C- 25C ) ( 0.05S /C ) ]
= 4.42 S
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41341B-page 104
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 9-3:
ANx
Rs
CPIN
5 pF
VA
VT 0.6V
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
CHOLD = 10 pF
VSS/VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
= Sampling Switch
VT
= Threshold Voltage
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
FIGURE 9-4:
Full-Scale Range
FFh
FEh
FDh
ADC Output Code
FCh
1 LSB ideal
FBh
Full-Scale
Transition
04h
03h
02h
01h
00h
VSS
Zero-Scale
Transition
Preliminary
VREF
DS41341B-page 105
PIC16F72X/PIC16LF72X
TABLE 9-2:
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
ADCON0
CHS3
CHS2
CHS1
CHS0
GO/DONE
ADON
--00 0000
--00 0000
ADCON1
ADCS2
ADCS1
ADCS0
ADREF1
ADREF0
-000 --00
-000 --00
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
ANSELE
ANSE2
ANSE1
ANSE0
---- -111
---- -111
ADRES
CCP2CON
FVRCON
FVRRDY
FVREN
INTCON
GIE
PEIE
T0IE
INTE
PIE1
TMR1GIE
ADIE
RCIE
TXIE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
TRISA
TRISA7
TRISA6
TRISA5
TRISB
TRISB7
TRISB6
TRISB5
TRISE
Legend:
DC2B1
DC2B0
CCP2M3
xxxx xxxx
uuuu uuuu
--00 0000
--00 0000
CCP2M2
CCP2M1
CCP2M0
ADFVR1
ADFVR0
q0-- --00
q0-- --00
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISE3
TRISE2
TRISE1
TRISE0
---- 1111
---- 1111
x = unknown, u = unchanged, = unimplemented read as 0, q = value depends on condition. Shaded cells are not used for ADC
module.
DS41341B-page 106
Preliminary
PIC16F72X/PIC16LF72X
10.0
REGISTER 10-1:
R-q
R/W-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
FVRRDY
FVREN
ADFVR1
ADFVR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 6
bit 5-2
Unimplemented: Read as 0
bit 1-0
Note 1:
2:
Preliminary
DS41341B-page 107
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 108
Preliminary
PIC16F72X/PIC16LF72X
11.0
TIMER0 MODULE
Note:
11.1.2
Timer0 Operation
11.1.1
FIGURE 11-1:
11.1
FOSC/4
Data Bus
T0XCS
T0CKI
1
0
Sync
2 TCY
1
0
Cap. Sensing
Oscillator
0
T0CS
T0SE
8-bit
Prescaler
PSA
Overflow to Timer1
T1GSS = 11
TMR0
TMR1GE
PSA
8
WDTE
Low-Power
WDT OSC
PS<2:0>
1
WDT
Time-out
Divide by
512
PSA
Preliminary
DS41341B-page 109
PIC16F72X/PIC16LF72X
11.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
11.1.4
TIMER0 INTERRUPT
11.1.5
DS41341B-page 110
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 11-1:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TMR0 RATE
WDT RATE
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
000
001
010
011
100
101
110
111
TABLE 11-1:
Name
CPSCON0
OPTION_REG
TMR0
TRISA
Legend:
INTCON
x = Bit is unknown
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CPSRNG1 CPSRNG0
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0--- 0000
CPSON
CPSOUT
T0XCS
0--- 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
xxxx xxxx
uuuu uuuu
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISA6
= Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
Preliminary
DS41341B-page 111
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 112
Preliminary
PIC16F72X/PIC16LF72X
12.0
FIGURE 12-1:
T1GSS<1:0>
T1G
00
From Timer0
Overflow
01
From Timer2
Match PR2
10
From WDT
Overflow
11
T1GSPM
0
T1G_IN
T1GVAL
0
Single Pulse
TMR1ON
T1GPOL
CK
R
Q1
Acq. Control
Data Bus
D
Q
RD
T1GCON
EN
Interrupt
T1GGO/DONE
Set
TMR1GIF
det
T1GTM
TMR1GE
TMR1ON
TMR1(2)
TMR1H
EN
TMR1L
T1CLK
Q
Synchronized
clock input
D
1
TMR1CS<1:0>
T1OSO/T1CKI
OUT
T1OSC
T1OSI
Cap. Sensing
Oscillator
T1SYNC
11
Synchronize(3)
Prescaler
1, 2, 4, 8
det
10
EN
0
T1OSCEN
(1)
FOSC
Internal
Clock
01
FOSC/4
Internal
Clock
00
2
T1CKPS<1:0>
FOSC/2
Internal
Clock
Sleep input
T1CKI
Preliminary
DS41341B-page 113
PIC16F72X/PIC16LF72X
12.1
Timer1 Operation
12.2
12.2.1
12.2.2
Timer1
Operation
TMR1GE
Off
Off
Always On
Count Enabled
TIMER1 ENABLE
SELECTIONS
TMR1ON
TABLE 12-1:
TABLE 12-2:
TMR1CS1
TMR1CS0
T1OSCEN
Clock Source
DS41341B-page 114
Preliminary
PIC16F72X/PIC16LF72X
12.3
12.5.1
Timer1 Prescaler
12.4
Timer1 Oscillator
12.5
Timer1 Operation in
Asynchronous Counter Mode
Preliminary
DS41341B-page 115
PIC16F72X/PIC16LF72X
12.6
12.6.2.1
Timer1 Gate
12.6.1
TABLE 12-3:
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
12.6.2
Timer1 Operation
12.6.2.2
12.6.2.3
12.6.2.4
Note:
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
DS41341B-page 116
00
T1GSS
TABLE 12-4:
Preliminary
PIC16F72X/PIC16LF72X
TABLE 12-5:
WDTE
TMR1GE = 1
and
T1GSS = 11
WDT Oscillator
Enable
WDT Reset
Wake-up
12.6.3
12.6.4
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 12-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
12.6.5
12.6.6
When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
Preliminary
DS41341B-page 117
PIC16F72X/PIC16LF72X
12.7
Timer1 Interrupt
12.9
12.8
FIGURE 12-2:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1:
2:
DS41341B-page 118
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 12-3:
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
TIMER1
FIGURE 12-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
TIMER1
N+4
Preliminary
N+8
DS41341B-page 119
PIC16F72X/PIC16LF72X
FIGURE 12-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
DS41341B-page 120
N+1
N+2
Set by hardware on
falling edge of T1GVAL
Cleared by software
Preliminary
Cleared by
software
PIC16F72X/PIC16LF72X
FIGURE 12-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
Cleared by hardware on
falling edge of T1GVAL
Set by software
DONE
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
TIMER1
TMR1GIF
Cleared by software
N+1
N+2
N+3
Set by hardware on
falling edge of T1GVAL
Preliminary
N+4
Cleared by
software
DS41341B-page 121
PIC16F72X/PIC16LF72X
12.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 12-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 12-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
bit 2
x = Bit is unknown
TMR1CS<1:0> = 0X
This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X.
bit 1
Unimplemented: Read as 0
bit 0
DS41341B-page 122
Preliminary
PIC16F72X/PIC16LF72X
12.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 12-2, is used to control Timer1 Gate.
REGISTER 12-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-x
R/W-0
R/W-0
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Preliminary
DS41341B-page 123
PIC16F72X/PIC16LF72X
TABLE 12-6:
Name
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
CCP2CON
INTCON
PORTB
xxxx xxxx
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
0000 00-0
uuuu uu-u
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
uuuu uxuu
T1CON
TMR1CS1 TMR1CS0
T1GCON
TMR1GE
Legend:
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Timer1 module.
DS41341B-page 124
T1GPOL
Preliminary
PIC16F72X/PIC16LF72X
13.0
TIMER2 MODULE
13.1
Timer2 Operation
FIGURE 13-1:
FOSC/4
Prescaler
1:1, 1:4, 1:16
2
TMR2
Sets Flag
bit TMR2IF
Reset
Comparator
EQ
Postscaler
1:1 to 1:16
T2CKPS<1:0>
PR2
4
TOUTPS<3:0>
Preliminary
DS41341B-page 125
PIC16F72X/PIC16LF72X
REGISTER 13-1:
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
TABLE 13-1:
x = Bit is unknown
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
0000 0000
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PR2
TMR2
T2CON
Legend:
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
0000 0000
0000 0000
1111 1111
1111 1111
0000 0000
0000 0000
-000 0000
-000 0000
x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used for Timer2 module.
DS41341B-page 126
Preliminary
PIC16F72X/PIC16LF72X
14.0
CAPACITIVE SENSING
MODULE
FIGURE 14-1:
T0CS
T0XCS
FOSC/4
T0CKI
0
TMR0
Overflow
1
1
CPSCH<3:0>(2)
CPSON(3)
CPS0
CPS1
CPS2
CPS3
Timer1 Module
CPS4
CPSON
T1CS<1:0>
CPS5
CPS6
CPS8(1)
CPS9
FOSC
Capacitive
Sensing
Oscillator
CPS7
(1)
CPSOSC
CPS10(1)
CPS11(1)
FOSC/4
CPSCLK
EN
T1OSC/
T1CKI
CPSOUT
TMR1H:TMR1L
T1GSEL<1:0>
CPSRNG<1:0>
CPS12(1)
T1G
CPS13(1)
Timer1 Gate
Control Logic
CPS14(1)
CPS15(1)
Timer2 Module
WDT
Event
TMR2
Overflow
WDT Overflow
Scaler
LP WDT
OSC
Postscaler
Set
TMR2IF
PS<2:0>
Preliminary
41341B-page 127
PIC16F72X/PIC16LF72X
14.1
14.4.1
Analog MUX
TIMER0
14.2
14.3
14.4.2
TABLE 14-1:
TMR1ON
TMR1GE
Timer1 Operation
Off
Off
On
Timer resources
14.4
TIMER1
41341B-page 128
Preliminary
PIC16F72X/PIC16LF72X
14.5
14.5.3
Software Control
14.5.1
FREQUENCY THRESHOLD
NOMINAL FREQUENCY
(NO CAPACITIVE LOAD)
14.5.2
REDUCED FREQUENCY
(ADDITIONAL CAPACITIVE LOAD)
Preliminary
41341B-page 129
PIC16F72X/PIC16LF72X
14.6
9.
41341B-page 130
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 14-1:
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
R-0
R/W-0
CPSON
CPSRNG1
CPSRNG0
CPSOUT
T0XCS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
Unimplemented: Read as 0
bit 3-2
bit 1
bit 0
Preliminary
41341B-page 131
PIC16F72X/PIC16LF72X
REGISTER 14-2:
U-0
U-0
U-0
U-0
R/W-0(2)
R/W-0
R/W-0
R/W-0
CPSCH3
CPSCH2
CPSCH1
CPSCH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3-0
Note 1:
2:
TABLE 14-2:
Name
Bit 6
Bit 5
ANSELA
ANSA5
ANSELB
ANSB5
ANSELD
ANSD7
ANSD6
ANSD5
OPTION_REG
RBPU
INTEDG
T0CS
TMR1GIE
ADIE
RCIE
PIE1
x = Bit is unknown
Bit 4
Value on
POR, BOR
Value on
all other
Resets
Bit 3
Bit 2
Bit 1
Bit 0
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
--11 1111
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
ANSD4
ANSD3
ANSD2
ANSD1
ANSD0
1111 1111
1111 1111
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
0000 00-0
0000 00-0
T2CON
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
1111 1111
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
1111 1111
1111 1111
Legend:
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.
41341B-page 132
Preliminary
PIC16F72X/PIC16LF72X
15.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
TABLE 15-1:
CCP Mode
Timer Resource
Capture
Timer1
Compare
Timer1
PWM
Timer2
TABLE 15-2:
CCP1 Mode
Interaction
Capture
Capture
Capture
Compare
Compare
Compare
PWM
PWM
The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges will be aligned.
PWM
Capture
None
PWM
Compare
None
Note 1:
2:
Note:
If CCP2 is configured as a Special Event Trigger, CCP1 will clear Timer1, affecting the value captured on
the CCP2 pin.
If CCP1 is in Capture mode and CCP2 is configured as a Special Event Trigger, CCP2 will clear Timer1,
affecting the value captured on the CCP1 pin.
Preliminary
DS41341B-page 133
PIC16F72X/PIC16LF72X
REGISTER 15-1:
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DCxB1
DCxB0
CCPxM3
CCPxM2
CCPxM1
CCPxM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3-0
DS41341B-page 134
Preliminary
PIC16F72X/PIC16LF72X
15.1
15.1.3
Capture Mode
15.1.1
FIGURE 15-1:
Prescaler
1, 4, 16
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPx
CCPRxH
Capture
Enable
EXAMPLE 15-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
MOVWF
15.1.5
TMR1L
CCPxCON<3:0>
System Clock (FOSC)
15.1.2
CCP PRESCALER
CLRF
MOVLW
CCPRxL
TMR1H
15.1.4
BANKSEL CCP1CON
and
Edge Detect
SOFTWARE INTERRUPT
Preliminary
DS41341B-page 135
PIC16F72X/PIC16LF72X
TABLE 15-3:
Name
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
SSSEL
CCP2SEL
---- --00
---- --00
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CCPRxL
xxxx xxxx
uuuu uuuu
CCPRxH
xxxx xxxx
uuuu uuuu
INTCON
PIE1
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
CCP2IF
---- ---0
---- ---0
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
0000 00-0
uuuu uu-u
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
0000 0x00
uuuu uuuu
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISC
Legend:
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Capture.
DS41341B-page 136
Preliminary
PIC16F72X/PIC16LF72X
15.2
15.2.2
Compare Mode
15.2.3
FIGURE 15-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxCON<3:0>
Mode Select
Set CCPxIF Interrupt Flag
(PIRx)
4
CCPRxH CCPRxL
CCPx
Q
S
R
Output
Logic
Match
TRIS
Output Enable
Comparator
TMR1H
TMR1L
15.2.1
15.2.4
15.2.5
Preliminary
DS41341B-page 137
PIC16F72X/PIC16LF72X
TABLE 15-4:
Name
Bit 6
Bit 5
Bit 4
ADCON0
CHS3
CHS2
ANSELB
ANSB5
ANSB4
APFCON
CCP1CON
DC1B1
CCP2CON
DC2B1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GO/DONE
ADON
--00 0000
--00 0000
ANSB1
ANSB0
--11 1111
--11 1111
SSSEL
CCP2SEL
---- --00
---- --00
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
Bit 3
Bit 2
Bit 1
CHS1
CHS0
ANSB3
ANSB2
DC1B0
DC2B0
CCPRxL
xxxx xxxx
uuuu uuuu
CCPRxH
xxxx xxxx
uuuu uuuu
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
---- ---0
CCP2IF
---- ---0
T1CON
TMR1CS1
TMR1CS0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1ON
0000 00-0
uuuu uu-u
T1GCON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS1
T1GSS0
0000 0x00
0000 0x00
uuuu uuuu
PIR2
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx
uuuu uuuu
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the Compare.
DS41341B-page 138
Preliminary
PIC16F72X/PIC16LF72X
15.3
PWM Mode
FIGURE 15-4:
PR2
T2CON
CCPRxL
CCPxCON
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON<5:4>
TMR2 = 0
15.3.1
FIGURE 15-3:
CCPxCON<5:4>
Duty Cycle Registers
CCPRxL
CCPRxH(2) (Slave)
CCPx
R
Comparator
TMR2
(1)
S
TRIS
Comparator
PR2
Note 1:
2:
Clear Timer2,
toggle CCPx pin and
latch duty cycle
Preliminary
DS41341B-page 139
PIC16F72X/PIC16LF72X
15.3.2
PWM PERIOD
EQUATION 15-2:
PULSE WIDTH
EQUATION 15-1:
PWM PERIOD
EQUATION 15-3:
TMR2 is cleared
The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPRxL into
CCPRxH.
15.3.3
( CCPRxL:CCPxCON<5:4> )
Duty Cycle Ratio = ----------------------------------------------------------------------4 ( PR2 + 1 )
TOSC = 1/FOSC
Note:
The
Timer2
postscaler
(refer
to
Section 13.1 Timer2 Operation) is not
used in the determination of the PWM
frequency.
DS41341B-page 140
Preliminary
PIC16F72X/PIC16LF72X
15.3.4
PWM RESOLUTION
EQUATION 15-4:
log [ 4 ( PR2 + 1 ) ]
Resolution = ------------------------------------------ bits
log ( 2 )
TABLE 15-5:
1.22 kHz
4.88 kHz
19.53 kHz
156.3 kHz
208.3 kHz
16
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
6.6
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
0x65
0x65
0x19
0x0C
0x09
15.3.8
1.
2.
3.
4.
5.
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
6.
Note:
15.3.7
78.12 kHz
PWM Frequency
15.3.6
0xFF
15.3.5
Note:
PWM Frequency
TABLE 15-6:
PWM RESOLUTION
Preliminary
DS41341B-page 141
PIC16F72X/PIC16LF72X
TABLE 15-7:
Name
Value on
POR, BOR
Value on
all other
Resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ANSELB
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
--11 1111
--11 1111
APFCON
SSSEL
CCP2SEL
---- --00
---- --00
CCP1CON
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000
--00 0000
CCP2CON
DC2B1
DC2B0
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000
--00 0000
CCPRxL
xxxx xxxx
uuuu uuuu
CCPRxH
xxxx xxxx
uuuu uuuu
PR2
1111 1111
1111 1111
-000 0000
T2CON
TMR2
TRISB
TRISC
Legend:
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
0000 0000
0000 0000
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
- = Unimplemented locations, read as 0, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
DS41341B-page 142
Preliminary
PIC16F72X/PIC16LF72X
16.0
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (AUSART)
The
Addressable
Universal
Synchronous
Asynchronous Receiver Transmitter (AUSART)
module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and
data buffers necessary to perform an input or output
serial data transfer independent of device program
execution. The AUSART, also known as a Serial
Communications Interface (SCI), can be configured as
a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
FIGURE 16-1:
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK
MSb
LSb
(8)
Pin Buffer
and Control
TRMT
SPEN
Transmit Shift Register (TSR)
TXEN
Baud Rate Generator
FOSC
n
TX9
n
+1
SPBRG
Multiplier
x4
SYNC
BRGH
x16 x64
TX9D
Preliminary
DS41341B-page 143
PIC16F72X/PIC16LF72X
FIGURE 16-2:
CREN
RX/DT
+1
SPBRG
RSR Register
MSb
Pin Buffer
and Control
Data
Recovery
FOSC
Multiplier
x4
x16 x64
SYNC
BRGH
Stop
OERR
(8)
LSb
0 START
RX9
FERR
RX9D
RCREG Register
FIFO
8
Data Bus
RCIF
RCIE
Interrupt
DS41341B-page 144
Preliminary
PIC16F72X/PIC16LF72X
16.1
16.1.1
AUSART ASYNCHRONOUS
TRANSMITTER
16.1.1.2
Transmitting Data
16.1.1.3
16.1.1.1
Note 1: When the SPEN bit is set the RX/DT I/O pin
is automatically configured as an input,
regardless of the state of the corresponding
TRIS bit and whether or not the AUSART
receiver is enabled. The RX/DT pin data
can be read via a normal PORT read but
PORT latch data output is precluded.
Preliminary
DS41341B-page 145
PIC16F72X/PIC16LF72X
16.1.1.4
TSR Status
16.1.1.6
16.1.1.5
1.
2.
3.
5.
6.
7.
FIGURE 16-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK pin
Start bit
FIGURE 16-4:
bit 1
bit 7/8
Stop bit
Word 1
TXIF bit
(Transmit Buffer
Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
bit 0
1 TCY
Word 1
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
Word 1
TX/CK pin
TXIF bit
(Transmit Buffer
Empty Flag)
Word 2
Start bit
bit 0
1 TCY
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
1 TCY
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note:
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
DS41341B-page 146
Preliminary
PIC16F72X/PIC16LF72X
TABLE 16-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
INTCON
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
0000 -010
0000 -010
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Asynchronous Transmission.
Preliminary
DS41341B-page 147
PIC16F72X/PIC16LF72X
16.1.2
AUSART ASYNCHRONOUS
RECEIVER
16.1.2.2
16.1.2.1
Note:
Receiving Data
16.1.2.3
Receive Interrupts
DS41341B-page 148
Preliminary
PIC16F72X/PIC16LF72X
16.1.2.4
16.1.2.7
16.1.2.5
Address Detection
16.1.2.6
Preliminary
DS41341B-page 149
PIC16F72X/PIC16LF72X
16.1.2.8
1.
2.
3.
4.
5.
6.
7.
8.
9.
16.1.2.9
FIGURE 16-5:
Rcv Shift
Reg
Rcv Buffer Reg
ASYNCHRONOUS RECEPTION
Start
bit
bit 0
RX/DT pin
bit 1
Start
bit
bit 0
Word 1
RCREG
Start
bit
Word 2
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41341B-page 150
Preliminary
PIC16F72X/PIC16LF72X
TABLE 16-2:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCREG
INTCON
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
TXSTA
Legend:
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Asynchronous Reception.
Preliminary
DS41341B-page 151
PIC16F72X/PIC16LF72X
REGISTER 16-1:
R/W-0
CSRC
R/W-0
R/W-0
U-0
R/W-0
R-1
R/W-0
TX9
TXEN(1)
SYNC
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Note 1:
x = Bit is unknown
DS41341B-page 152
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 16-2:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R-0
R-0
R-x
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: The AUSART module automatically changes the pin from tri-state to drive as needed. Configure
TRISx = 1.
Preliminary
DS41341B-page 153
PIC16F72X/PIC16LF72X
16.2
EXAMPLE 16-1:
CALCULATING BAUD
RATE ERROR
F OS C
Desired Baud Rate = --------------------------------------64 ( SPBRG + 1 )
16000000
= ------------------------ 1
64 ( 9600 )
= [ 25.042 ] = 25
16000000
Actual Baud Rate = --------------------------64 ( 25 + 1 )
= 9615
TABLE 16-3:
Configuration Bits
AUSART Mode
Asynchronous
FOSC/[64 (n+1)]
Asynchronous
FOSC/[16 (n+1)]
Synchronous
FOSC/[4 (n+1)]
SYNC
BRGH
0
0
1
Legend:
TABLE 16-4:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0000 000x
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
Legend:
x = unknown, - = unimplemented read as 0. Shaded cells are not used for the Baud Rate Generator.
DS41341B-page 154
Preliminary
PIC16F72X/PIC16LF72X
TABLE 16-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1201
0.08
207
1200
0.00
143
2400
2404
0.16
129
2400
0.00
119
2403
0.16
103
2400
0.00
71
9600
9470
-1.36
32
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
29
10286
-1.26
27
10416
-0.01
23
10165
-2.42
16
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
57.6k
57.60k
0.00
57.60k
0.00
115.2k
SYNC = 0, BRGH = 0
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
SYNC = 0, BRGH = 1
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
300
1200
2400
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.82k
-1.36
21
57.60k
0.00
19
58.8k
2.12
16
57.60k
0.00
11
115.2k
113.64k
-1.36
10
115.2k
0.00
115.2k
0.00
Preliminary
DS41341B-page 155
PIC16F72X/PIC16LF72X
TABLE 16-5:
BAUD
RATE
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
%
Error
SPBRG
value
(decimal)
Actual
Rate
%
Error
SPBRG
value
(decimal)
300
1200
1202
0.16
207
1200
0.00
191
300
1202
0.16
0.16
207
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS41341B-page 156
Preliminary
PIC16F72X/PIC16LF72X
16.3
16.3.1.2
16.3.1
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
16.3.1.1
Note:
16.3.1.3
1.
2.
3.
Master Clock
4.
5.
6.
7.
8.
Preliminary
DS41341B-page 157
PIC16F72X/PIC16LF72X
FIGURE 16-6:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
Word 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
TX/CK pin
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
1
Synchronous Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
FIGURE 16-7:
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 16-6:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000x
0000 000x
SPBRG
BRG7
BRG6
BRG5
BRG4
BRG3
BRG2
BRG1
BRG0
0000 0000
0000 0000
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TRISC
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 0000
0000 0000
0000 -010
0000 -010
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Master Transmission.
DS41341B-page 158
Preliminary
PIC16F72X/PIC16LF72X
16.3.1.4
16.3.1.7
16.3.1.5
Slave Clock
16.3.1.6
16.3.1.8
1.
Preliminary
DS41341B-page 159
PIC16F72X/PIC16LF72X
FIGURE 16-8:
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RXREG
Note:
Timing diagram demonstrates Synchronous Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 16-7:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RCREG
0000 0000
0000 0000
RCSTA
TRISC
TXSTA
Legend:
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Master Reception.
DS41341B-page 160
Preliminary
PIC16F72X/PIC16LF72X
16.3.2
1.
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
2.
3.
4.
16.3.2.1
5.
16.3.2.2
1.
2.
3.
4.
5.
6.
7.
8.
TABLE 16-8:
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
0000 0000
0000 0000
0000 -010
0000 -010
RCSTA
TRISC
TXREG
TXSTA
Legend:
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Slave Transmission.
Preliminary
DS41341B-page 161
PIC16F72X/PIC16LF72X
16.3.2.3
16.3.2.4
1.
2.
Sleep
CREN bit is always set, therefore the receiver is
never Idle
SREN bit, which is a don't care in Slave mode
3.
4.
5.
6.
7.
8.
9.
TABLE 16-9:
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
all other
Resets
Value on
POR, BOR
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
RCREG
PIE1
0000 0000
0000 0000
0000 0000
0000 0000
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
0000 000X
0000 000X
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
TXSTA
CSRC
TX9
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010
0000 -010
Legend:
x = unknown, - = unimplemented read as 0. Shaded cells are not used for Synchronous Slave Reception.
DS41341B-page 162
Preliminary
PIC16F72X/PIC16LF72X
16.4
16.4.1
16.4.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
Preliminary
DS41341B-page 163
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 164
Preliminary
PIC16F72X/PIC16LF72X
17.0
17.1
SPI Mode
Master mode
Slave mode
SPI is a full-duplex protocol, with all communication
being bidirectional and initiated by a master device. All
clocking is provided by the master device and all bits
are transmitted, MSb first. Care must be taken to
ensure that all devices on the SPI bus are setup to
allow all controllers to send and receive data at the
same time.
FIGURE 17-1:
SDI
SDI
Shift Register
(SSPSR)
MSb
LSb
General I/O
Shift Register
(SSPSR)
MSb
SCK
Processor 1
SDO
Serial Clock
Slave Select
(optional)
Preliminary
LSb
SCK
SS
Processor 2
DS41341B-page 165
PIC16F72X/PIC16LF72X
FIGURE 17-2:
Write
SSPBUF Reg
SSPSR Reg
SDI
bit 0
Shift
Clock
bit 7
SDO
SS
Control
Enable
RA5/SS
RA0/SS
SSSEL
2
Clock Select
Edge
Select
2
Edge
Select
Prescaler
4, 16, 64
SCK
TRISx
TMR2
Output
FOSC
4
SSPM<3:0>
DS41341B-page 166
Preliminary
PIC16F72X/PIC16LF72X
17.1.1
MASTER MODE
17.1.1.3
17.1.1.1
17.1.1.2
17.1.1.4
Preliminary
DS41341B-page 167
PIC16F72X/PIC16LF72X
FIGURE 17-3:
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
SDO
(CKE = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDO
(CKE = 1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
EXAMPLE 17-1:
LOOP
BANKSEL
BTFSS
GOTO
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
DS41341B-page 168
;
;Has data been received(transmit complete)?
;No
;
;WREG reg = contents of SSPBUF
;Save in user RAM, if data is meaningful
;W reg = contents of TXDATA
;New data to xmit
Preliminary
PIC16F72X/PIC16LF72X
17.1.2
SLAVE MODE
17.1.2.2
17.1.2.1
17.1.2.3
Preliminary
DS41341B-page 169
PIC16F72X/PIC16LF72X
FIGURE 17-4:
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
bit 7
SDI
(SMP = 0)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
FIGURE 17-5:
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 6
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
DS41341B-page 170
Preliminary
PIC16F72X/PIC16LF72X
17.1.2.4
Note:
17.1.2.5
FIGURE 17-6:
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
bit 7
bit 6
bit 7
bit 0
bit 0
bit 7
bit 7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Preliminary
DS41341B-page 171
PIC16F72X/PIC16LF72X
REGISTER 17-1:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
DS41341B-page 172
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 17-2:
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
P: Stop bit
Used in I2C mode only.
bit 3
S: Start bit
Used in I2C mode only.
bit 2
bit 1
bit 0
Preliminary
x = Bit is unknown
DS41341B-page 173
PIC16F72X/PIC16LF72X
TABLE 17-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
--11 1111
ANSELA
ANSA5
ANSA4
ANSA3
ANSA2
ANSA1
ANSA0
--11 1111
APFCON
SSSEL
CCP2SEL
---- --00
---- --00
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
PIE1
PIR1
TMR1GIF
0000 0000
0000 0000
PR2
1111 1111
1111 1111
SSPBUF
xxxx xxxx
uuuu uuuu
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
0000 0000
0000 0000
SSPSTAT
SMP
CKE
D/A
R/W
UA
BF
0000 0000
0000 0000
1111 1111
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
1111 1111
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
T2CON
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
-000 0000
-000 0000
Legend:
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the SSP in SPI mode.
DS41341B-page 174
Preliminary
PIC16F72X/PIC16LF72X
I2C Mode
17.2
FIGURE 17-8:
VDD
Internal
Data Bus
Read
Write
SSPBUF Reg
SCL
Shift
Clock
SDA
SCL
SCL
SDA
SCL
(optional)
17.2.1
HARDWARE SETUP
SSPSR Reg
SDA
Slave 1
SDA
Slave 2
Two pins are used for data transfer; the SCL pin (clock
line) and the SDA pin (data line). The user must
configure the two pin's data direction bits as inputs in
the appropriate TRIS register. Upon enabling I2C
mode, the I2C slew rate limiters in the I/O pads are
controlled by the SMP bit of SSPSTAT register. The
SSP module functions are enabled by setting the
SSPEN bit of SSPCON register.
VDD
Master
FIGURE 17-7:
TYPICAL I2C
CONNECTIONS
LSb
MSb
SSPMSK Reg
Match Detect
Addr Match
SSPADD Reg
Start and
Stop bit Detect
Preliminary
DS41341B-page 175
PIC16F72X/PIC16LF72X
17.2.2
FIGURE 17-9:
SDA
SCL
S
Start
P
Change of
Change of
Data Allowed
Data Allowed
Condition
17.2.3
Stop
Condition
ACKNOWLEDGE
TABLE 17-2:
SSPSR SSPBUF
Generate ACK
Pulse
SSPOV
0
Yes
Yes
Yes
0
No
No
Yes
1
No
No
Yes
1
No
No
Yes
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
DS41341B-page 176
Preliminary
PIC16F72X/PIC16LF72X
17.2.4
ADDRESSING
17.2.4.1
7-bit Addressing
17.2.4.2
10-bit Addressing
6.
7.
8.
9.
17.2.4.3
Address Masking
Preliminary
DS41341B-page 177
PIC16F72X/PIC16LF72X
17.2.5
RECEPTION
FIGURE 17-10:
R/W = 0
Receiving Address
SCL
SSPIF
BF
Receiving Data
ACK
A7 A6 A5 A4 A3 A2 A1
SDA
ACK
D7 D6 D5 D4 D3 D2 D1 D0
8
Receiving Data
ACK
D7 D6 D5 D4 D3 D2 D1 D0
1
Cleared in software
Bus Master
sends Stop
condition
SSPOV
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS41341B-page 178
Preliminary
Preliminary
CKP
UA
SSPOV
BF
SSPIF
SCL
SDA
UA is set indicating
that the SSPADD needs to
be updated
SSPBUF is written
with contents of SSPSR
Cleared in software
2
4
Cleared in software
UA is set indicating
that SSPADD needs to
be updated
Cleared by hardware
when SSPADD is updated
with low byte of address
A6 A5 A4 A3 A2 A1 A0
A7
ACK
5
6
Cleared in software
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Cleared in software
D7 D6 D5 D4 D3 D2 D1 D0
P
Bus master
sends Stop
condition
SSPOV is set
because SSPBUF is
still full. ACK is not sent.
ACK
FIGURE 17-11:
R/W ACK
A9 A8 0
PIC16F72X/PIC16LF72X
DS41341B-page 179
PIC16F72X/PIC16LF72X
17.2.6
TRANSMISSION
FIGURE 17-12:
SDA
SCL
A7
A6
1
2
Data in
sampled
R/W
A5
A4
A3
A2
A1
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
Cleared in software
SSPIF
BF
Dummy read of SSPBUF
to clear BF flag
CKP
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
DS41341B-page 180
Preliminary
Preliminary
CKP
UA
BF
SSPIF
SCL
A9 A8
ACK
R/W = 0
Cleared in software
A6 A5 A4 A3 A2 A1
A0
A7
ACK
Cleared in software
A9 A8
Sr
Bus Master
sends Restarts
condition
ACK
R/W = 1
Cleared in software
Write of SSPBUF
Completion of
data transmission
clears BF flag
ACK
D4 D3 D2 D1 D0
D7 D6 D5
Bus Master
sends Stop
condition
FIGURE 17-13:
SDA
PIC16F72X/PIC16LF72X
DS41341B-page 181
PIC16F72X/PIC16LF72X
17.2.7
CLOCK STRETCHING
2
17.2.8
17.2.9
MULTI-MASTER MODE
DS41341B-page 182
Preliminary
PIC16F72X/PIC16LF72X
17.2.10
CLOCK SYNCHRONIZATION
17.2.11
When the CKP bit is cleared, the SCL output is held low
once it is sampled low. therefore, the CKP bit will not
stretch the SCL line until an external I2C master device
has already asserted the SCL line low. The SCL output
will remain low until the CKP bit is set and all other
devices on the I2C bus have released SCL. This
ensures that a write to the CKP bit will not violate the
minimum
high
time
requirement
for
SCL
(Figure 17-14).
FIGURE 17-14:
SLEEP OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
DX
DX-1
SCL
CKP
Master device
asserts clock
Master device
deasserts clock
WR
SSPCON
Preliminary
DS41341B-page 183
PIC16F72X/PIC16LF72X
REGISTER 17-3:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1: When this mode is selected, any reads or writes to the SSPADD SFR address accesses the SSPMSK register.
2: When enabled, these pins must be properly configured as input or output using the associated TRIS bit.
DS41341B-page 184
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 17-4:
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
R/W
UA
BF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
P: Stop bit
This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.
1 = Indicates that a Stop bit has been detected last (this bit is 0 on Reset)
0 = Stop bit was not detected last
bit 3
S: Start bit
This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.
1 = Indicates that a Start bit has been detected last (this bit is 0 on Reset)
0 = Start bit was not detected last
bit 2
bit 1
bit 0
Preliminary
DS41341B-page 185
PIC16F72X/PIC16LF72X
REGISTER 17-5:
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
MSK7
MSK6
MSK5
MSK4
MSK3
MSK2
MSK1
MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-1
bit 0
REGISTER 17-6:
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 17-7:
Name
INTCON
x = Bit is unknown
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
SSPBUF
xxxx xxxx
uuuu uuuu
SSPADD
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
SSPCON
SSPMSK(2)
WCOL
SSPOV
SSPEN
SSPSTAT
SMP(1)
CKE(1)
D/A
TRISC
TRISC7
TRISC6
TRISC5
Legend:
Note 1:
2:
CKP
SSPM3
SSPM2
SSPM1
SSPM0
TRISC4 TRISC3
R/W
UA
BF
0000 0000
0000 0000
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as 0. Shaded cells are not used by SSP module in I2C
mode.
Maintain these bits clear in I2C mode.
Accessible only when SSPM<3:0> = 1001.
DS41341B-page 186
Preliminary
PIC16F72X/PIC16LF72X
18.0
PMCON1
PMDATL
PMDATH
PMADRL
PMADRH
Note:
Required
Sequence
EXAMPLE 18-1:
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BANKSEL
BSF
NOP
NOP
PMADRL
;
MS_PROG_ADDR, W ;
PMADRH
;MS Byte of Program Address to read
LS_PROG_ADDR, W ;
PMADRL
;LS Byte of Program Address to read
PMCON1
;
PMCON1, RD
;Initiate Read
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
PMDATL
PMDATL, W
LOWPMBYTE
PMDATH, W
HIGHPMBYTE
Preliminary
DS41341B-page 187
PIC16F72X/PIC16LF72X
REGISTER 18-1:
R-1
U-0
U-0
U-0
U-0
U-0
U-0
R/S-0
Reserved
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7
bit 6-1
Unimplemented: Read as 0
bit 0
REGISTER 18-2:
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMD13
PMD12
PMD11
PMD10
PMD9
PMD8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
x = Bit is unknown
bit 7-6
Unimplemented: Read as 0
bit 5-0
PMD<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
REGISTER 18-3:
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMD7
PMD6
PMD5
PMD4
PMD3
PMD2
PMD1
PMD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
x = Bit is unknown
PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
DS41341B-page 188
Preliminary
PIC16F72X/PIC16LF72X
REGISTER 18-4:
U-0
U-0
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMA12
PMA11
PMA10
PMA9
PMA8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
REGISTER 18-5:
x = Bit is unknown
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
PMA7
PMA6
PMA5
PMA4
PMA3
PMA2
PMA1
PMA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
-n = Value at POR
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 18-1:
Name
PMCON1
PMADRH
PMADRL
PMDATH
PMDATL
Legend:
x = Bit is unknown
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
Reserved
RD
1--- ---0
1--- ---0
---x xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
--xx xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used by the Program Memory
Read.
Preliminary
DS41341B-page 189
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 190
Preliminary
PIC16F72X/PIC16LF72X
19.0
1.
2.
3.
4.
5.
6.
7.
19.1
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
Preliminary
DS41341B-page 191
PIC16F72X/PIC16LF72X
19.2
FIGURE 19-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON reg.)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC + 1
Inst(PC) = Sleep
Inst(PC - 1)
PC + 2
PC + 2
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
TABLE 19-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other Resets
IOCB
IOCB7
IOCB6
IOCB5
IOCB4
IOCB3
IOCB2
IOCB1
IOCB0
0000 0000
0000 0000
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 0000
0000 0000
PIE1
TMR1GIE
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
PIE2
CCP2IE
---- ---0
---- ---0
PIR1
TMR1GIF
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
PIR2
CCP2IF
---- ---0
---- ---0
INTCON
Legend:
x = unknown, u = unchanged, = unimplemented, read as 0. Shaded cells are not used in Power-down mode.
DS41341B-page 192
Preliminary
PIC16F72X/PIC16LF72X
20.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
FIGURE 20-1:
Note:
Device to be
Programmed
VDD
VDD
VDD
10k
VPP
MCLR/VPP
GND
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
Preliminary
DS41341B-page 193
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 194
Preliminary
PIC16F72X/PIC16LF72X
21.0
TABLE 21-1:
Field
Description
Register file address (0x00 to 0x7F)
Byte-oriented operations
Bit-oriented operations
Literal and control operations
OPCODE FIELD
DESCRIPTIONS
PC
Program Counter
TO
Time-out bit
Carry bit
C
DC
Z
PD
Power-down bit
FIGURE 21-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
21.1
13
Read-Modify-Write Operations
OPCODE
Preliminary
0
k (literal)
11
OPCODE
10
0
k (literal)
DS41341B-page 195
PIC16F72X/PIC16LF72X
TABLE 21-2:
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
C, DC, Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
Z
1, 2
1, 2
2
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
01
01
01
01
1, 2
1, 2
3
3
2:
3:
k
k
k
k
k
k
k
k
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C, DC, Z
Z
TO, PD
Z
TO, PD
C, DC, Z
Z
When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external
device, the data will be written back with a 0.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41341B-page 196
Preliminary
PIC16F72X/PIC16LF72X
21.2
Instruction Descriptions
ADDLW
Syntax:
[ label ] ADDLW
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
0 f 127
0b7
Operation:
0 (f<b>)
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
f,b
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
0b7
Operation:
Operation:
1 (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Description:
ANDLW
BTFSC
Syntax:
[ label ] ANDLW
Syntax:
Operands:
0 k 255
Operands:
Operation:
0 f 127
0b7
Status Affected:
Operation:
skip if (f<b>) = 0
Description:
Status Affected:
None
Description:
ANDWF
f,d
AND W with f
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d [0,1]
Operation:
f,d
Status Affected:
Description:
f,b
Preliminary
DS41341B-page 197
PIC16F72X/PIC16LF72X
BTFSS
CLRWDT
Syntax:
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
0b<7
Operands:
None
Operation:
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Description:
Operation:
skip if (f<b>) = 1
Status Affected:
None
Description:
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
Syntax:
[ label ] COMF
Operands:
0 k 2047
Operands:
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
0 f 127
d [0,1]
f,d
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Syntax:
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
0 f 127
d [0,1]
Operation:
(f) - 1 (destination)
Status Affected:
Status Affected:
Description:
Description:
Decrement register f. If d is 0,
the result is stored in the W
register. If d is 1, the result is
stored back in register f.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Description:
DS41341B-page 198
Preliminary
PIC16F72X/PIC16LF72X
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
GOTO k
INCF f,d
Preliminary
INCFSZ f,d
IORWF
f,d
DS41341B-page 199
PIC16F72X/PIC16LF72X
MOVF
Move f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
MOVF f,d
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
Operation:
(f) (dest)
Status Affected:
None
Status Affected:
Description:
Description:
Words:
Cycles:
Words:
Cycles:
Example:
MOVF
Example:
MOVW
F
OPTION
Before Instruction
OPTION =
W
=
After Instruction
OPTION =
W
=
FSR, 0
0xFF
0x4F
0x4F
0x4F
After Instruction
W =
value in FSR
register
Z = 1
MOVLW
Move literal to W
NOP
No Operation
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 k 255
Operands:
None
Operation:
k (W)
Operation:
No operation
Status Affected:
None
Status Affected:
None
Description:
Description:
No operation.
Words:
Cycles:
Words:
Cycles:
Example:
MOVLW k
Example:
MOVLW
NOP
0x5A
After Instruction
W =
DS41341B-page 200
NOP
0x5A
Preliminary
PIC16F72X/PIC16LF72X
RETFIE
RETLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
0 k 255
Operation:
TOS PC,
1 GIE
Operation:
k (W);
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
Words:
Cycles:
Example:
RETFIE
After Interrupt
PC =
GIE =
TABLE
TOS
1
RETLW k
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Syntax:
[ label ]
Operands:
None
Operation:
TOS PC
Status Affected:
None
Description:
Preliminary
RETURN
DS41341B-page 201
PIC16F72X/PIC16LF72X
RLF
SLEEP
Syntax:
[ label ]
Syntax:
[ label ] SLEEP
Operands:
0 f 127
d [0,1]
Operands:
None
Operation:
Operation:
Status Affected:
Description:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
RLF
f,d
Words:
Cycles:
Example:
Status Affected:
TO, PD
Description:
Register f
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
RRF
SUBLW
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) (W)
Operation:
Status Affected:
Description:
Description:
RRF f,d
DS41341B-page 202
Register f
Preliminary
W>k
C=1
Wk
DC = 0
DC = 1
W<3:0> k<3:0>
PIC16F72X/PIC16LF72X
SUBWF
Subtract W from f
XORLW
Syntax:
Syntax:
[ label ] XORLW k
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
Operation:
SWAPF
Status Affected:
Description:
W>f
C=1
Wf
DC = 0
DC = 1
W<3:0> f<3:0>
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
Syntax:
[ label ] XORWF
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
Preliminary
f,d
DS41341B-page 203
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 204
Preliminary
PIC16F72X/PIC16LF72X
22.0
DEVELOPMENT SUPPORT
22.1
Preliminary
DS41341B-page 205
PIC16F72X/PIC16LF72X
22.2
MPASM Assembler
22.5
22.6
22.3
22.4
DS41341B-page 206
Preliminary
PIC16F72X/PIC16LF72X
22.7
22.9
22.8
Preliminary
DS41341B-page 207
PIC16F72X/PIC16LF72X
22.11 PICSTART Plus Development
Programmer
DS41341B-page 208
Preliminary
PIC16F72X/PIC16LF72X
23.0
ELECTRICAL SPECIFICATIONS
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
Preliminary
DS41341B-page 209
PIC16F72X/PIC16LF72X
23.1
PIC16LF72X
PIC16F72X
Param.
No.
D001
Sym.
VDD
Characteristic
VDR
Max.
Units
PIC16LF72X
1.8
1.8
2.3
3.6
3.6
3.6
V
V
V
PIC16F72X
1.8
1.8
2.3
5.5
5.5
5.5
V
V
V
PIC16LF72X
1.5
PIC16F72X
1.7
1.6
PIC16LF72X
0.8
PIC16F72X
1.7
0.984
0.974
1.968
1.938
3.966
3.936
1.024
1.064
1.064
2.158
2.158
4.226
4.226
VDD 2V
VDD 2V; -40 TA 125C
VDD 2.5V
VDD 2.5V; -40 TA 125C
VDD 4.75V
VDD 4.75V; -40 TA 125C
0.05
V/ms
VPOR*
VPORR*
VFVR
SVDD
Conditions
D002*
D004*
Typ
Supply Voltage
D001
D002*
Min.
2.048
4.096
DS41341B-page 210
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 23-1:
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
TPOR(3)
Preliminary
DS41341B-page 211
PIC16F72X/PIC16LF72X
23.2
PIC16LF72X
PIC16F72X
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
LDO Regulator
D010
D010
D011*
D011*
D011*
D011*
D012
D012
350
50
30
7.0
11
1.8
9.0
13
3.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40C TA +85C
9.5
20
1.8
12.5
22
3.0
13.5
24
5.0
7.0
12
1.8
9.0
18
3.0
9.5
21
1.8
12.5
25
3.0
13.5
27
5.0
110
150
1.8
150
200
3.0
120
175
1.8
160
250
3.0
180
300
5.0
250
300
1.8
380
600
3.0
275
350
1.8
400
700
3.0
450
750
5.0
D013*
150
180
1.8
230
270
3.0
D013*
150
205
1.8
225
320
3.0
250
350
5.0
FOSC = 32 kHz
LP Oscillator mode (Note 4),
-40C TA +85C
FOSC = 32 kHz
LP Oscillator mode
FOSC = 32 kHz
LP Oscillator mode (Note 4)
FOSC = 1 MHz
XT Oscillator mode
FOSC = 1 MHz
XT Oscillator mode (Note 5)
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode (Note 5)
FOSC = 1 MHz
EC Oscillator mode
FOSC = 1 MHz
EC Oscillator mode (Note 5)
DS41341B-page 212
Preliminary
PIC16F72X/PIC16LF72X
23.2
PIC16LF72X
PIC16F72X
Param
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
VDD
Note
D015
D015
D016*
D016*
290
330
1.8
460
500
3.0
300
430
1.8
450
655
3.0
500
730
5.0
110
130
1.8
130
150
3.0
100
195
1.8
125
200
3.0
150
220
5.0
690
800
1.8
1000
1200
3.0
625
980
mA
1.8
1000
1425
mA
3.0
1000
1470
mA
5.0
D017
1.0
1.2
mA
1.8
1.5
1.7
mA
3.0
D017
1.4
mA
1.8
1.5
1.9
mA
3.0
1.6
2.4
mA
5.0
230
240
1.8
340
360
3.0
225
320
1.8
350
445
3.0
D018
D018
D019
D019
*
Note 1:
2:
3:
4:
5:
400
800
5.0
1.6
1.8
mA
3.0
1.9
2.1
mA
3.6
1.6
mA
3.0
1.9
3.2
mA
5.0
FOSC = 4 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode (Note 5)
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode (Note 5)
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 4 MHz
EXTRC mode (Note 3, Note 5)
FOSC = 20 MHz
HS Oscillator mode
FOSC = 20 MHz
HS Oscillator mode (Note 5)
Preliminary
DS41341B-page 213
PIC16F72X/PIC16LF72X
23.3
PIC16LF72X
PIC16F72X
Param
No.
Device Characteristics
Power-down Base Current
Min.
Typ
Conditions
Max.
+85C
Max.
+125C
Units
0.7
3.9
VDD
D020
0.06
0.08
1.0
4.3
3.0
D020
4.5
10.2
14.2
1.8
10.5
16.8
3.0
5.5
11.8
18.7
5.0
0.5
1.7
4.1
1.8
0.8
4.8
3.0
13.5
16.4
1.8
6.5
14.5
16.8
3.0
D021
D021
D021A
D021A
1.8
7.5
16
18.7
5.0
8.5
14
18
1.8
8.5
14
18
3.0
39
44
48
1.8
39
45
49
3.0
40
60
70
mA
5.0
D022
1.8
7.5
12
18
3.0
D022
1.8
38
42
49
3.0
40
46
50
5.0
0.6
1.8
1.8
3.5
3.0
4.5
11.1
1.8
12.5
3.0
13.5
5.0
D026
D026
Note 1:
2:
3:
4:
5:
Note
(IPD)(2)
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
DS41341B-page 214
Preliminary
PIC16F72X/PIC16LF72X
23.3
PIC16LF72X
PIC16F72X
Param
No.
Device Characteristics
Min.
Typ
Conditions
Max.
+85C
Max.
+125C
Units
VDD
Note
(2)
0.1
0.7
4.3
1.8
0.1
1.0
4.7
3.0
3.5
10.7
14.3
1.8
10.6
16.9
3.0
18.8
5.0
1.8
4.5
11.9
D027A
250
400
250
400
3.0
D027A
280
430
1.8
280
430
3.0
280
430
5.0
3.5
1.8
3.0
3.5
1.8
3.0
32
5.0
D028
D028
Note 1:
2:
3:
4:
5:
Cap Sense
Cap Sense
Preliminary
DS41341B-page 215
PIC16F72X/PIC16LF72X
23.4
DC Characteristics: PIC16F72X/PIC16LF72X-I/E
DC CHARACTERISTICS
Param
No.
Sym.
VIL
Characteristic
Typ
Max.
Units
Conditions
0.8
0.15 VDD
0.2 VDD
0.3 VDD
D030
D030A
D031
D032
0.2 VDD
D033A
0.3 VDD
2.0
0.25 VDD +
0.8
0.8 VDD
0.7 VDD
VIH
D040
D040A
D041
D042
MCLR
0.8 VDD
D043A
0.7 VDD
D043B
0.9 VDD
(Note 1)
VSS VPIN VDD, Pin at highimpedance
125C
IIL
D060
I/O ports
100
nA
1000
nA
D061
MCLR(3)
50
200
nA
D063
OSC1
50
100
nA
25
25
100
140
200
300
0.6
VDD - 0.7
IPUR
D070*
VOL
D080
VOH
D090
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
DS41341B-page 216
Preliminary
PIC16F72X/PIC16LF72X
23.4
Param
No.
Sym.
Characteristic
Typ
Max.
Units
Conditions
15
pF
50
pF
Cell Endurance
100
1k
E/W
VMIN
8.0
9.0
2.7
VPEW
2.7
IPPPGM
5.0
mA
5.0
mA
2.8
ms
Year
D101A* CIO
EP
D131
D132
D133
TPEW
D134
TRETD
Characteristic Retention
40
Charging current
200
D135A
0.0
mA
Legend:
Note 1:
2:
3:
4:
TBD = To Be Determined
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
Negative current is defined as current sourced by the pin.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
Including OSC2 in CLKOUT mode.
Preliminary
DS41341B-page 217
PIC16F72X/PIC16LF72X
23.5
Thermal Considerations
TH02
TH03
TH04
TH05
Sym.
Characteristic
JA
JC
TJMAX
PD
Typ.
Units
Conditions
60
C/W
80
C/W
90
C/W
27.5
C/W
47.2
C/W
46
C/W
24.4
C/W
31.4
C/W
24
C/W
24
C/W
24
C/W
24.7
C/W
14.5
C/W
20
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS41341B-page 218
Preliminary
PIC16F72X/PIC16LF72X
23.6
FIGURE 23-2:
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
Preliminary
DS41341B-page 219
PIC16F72X/PIC16LF72X
23.7
AC Characteristics: PIC16F72X-I/E
FIGURE 23-3:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
FIGURE 23-4:
VDD (V)
5.5
3.6
2.5
HS Oscillator
Limit
2.3
2.0
1.8
0
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 23-1 for each Oscillator modes supported frequencies.
DS41341B-page 220
Preliminary
PIC16F72X/PIC16LF72X
PIC16LF72X VOLTAGE FREQUENCY GRAPH, -40C TA +125C
VDD (V)
FIGURE 23-5:
3.6
2.5
HS Oscillator
Limit
2.3
2.0
1.8
0
16
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 23-1 for each Oscillator modes supported frequencies.
FIGURE 23-6:
125
+ 5%
Temperature (C)
85
60
2%
25
0
-20
+ 5%
-40
1.8
2.0
2.5
4.0
4.5
5.0
5.5
VDD (V)
Note 1: This chart covers both regulator enabled and regulator disabled states.
2: Regulator Nominal voltage
Preliminary
DS41341B-page 221
PIC16F72X/PIC16LF72X
TABLE 23-1:
Sym.
FOSC
Characteristic
External CLKIN Frequency(1)
Oscillator Frequency(1)
OS02
TOSC
Oscillator Period(1)
OS03
TCY
OS04*
TosH,
TosL
TosR,
TosF
OS05*
Min.
Typ
Max.
Units
Conditions
DC
37
kHz
DC
MHz
XT Oscillator mode
DC
20
MHz
HS Oscillator mode
DC
20
MHz
EC Oscillator mode
32.768
kHz
LP Oscillator mode
0.1
MHz
XT Oscillator mode
20
MHz
HS Oscillator mode
DC
MHz
RC Oscillator mode
27
LP Oscillator mode
250
ns
XT Oscillator mode
50
ns
HS Oscillator mode
50
ns
EC Oscillator mode
30.5
LP Oscillator mode
250
10,000
ns
XT Oscillator mode
LP Oscillator mode
50
1,000
ns
HS Oscillator mode
250
ns
RC Oscillator mode
200
TCY
DC
ns
TCY = 4/FOSC
LP oscillator
100
ns
XT oscillator
20
ns
HS oscillator
ns
LP oscillator
ns
XT oscillator
ns
HS oscillator
DS41341B-page 222
Preliminary
PIC16F72X/PIC16LF72X
TABLE 23-2:
OSCILLATOR PARAMETERS
Sym.
HFOSC
OS08A MFOSC
OS10*
Freq.
Tolerance
Characteristic
Min.
Typ
Max.
Units
Conditions
2%
16.0
MHz
0C TA +85C
5%
16.0
MHz
-40C TA +125C
2%
500
kHz
0C TA +85C
5%
500
kHz
-40C TA +125C
FIGURE 23-7:
Cycle
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS16
OS13
OS18
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
Preliminary
DS41341B-page 223
PIC16F72X/PIC16LF72X
TABLE 23-3:
Sym.
TosH2ckL
OS12
Characteristic
Typ
Max.
Units
Conditions
70
ns
VDD = 3.3-5.0V
72
ns
VDD = 3.3-5.0V
(1)
(1)
OS13
TckL2ioV
OS14
TioV2ckH
OS15
OS16
TosH2ioV
TosH2ioI
OS17
TioV2osH
OS18
TioR
OS19
TioF
20
ns
TOSC + 200
ns
50
ns
50
70*
ns
ns
20
ns
25
TCY
40
15
28
15
72
32
55
30
ns
OS20* Tinp
OS21* Trbp
*
Min.
ns
VDD = 3.3-5.0V
VDD = 3.3-5.0V
VDD = 2.0V
VDD = 3.3-5.0V
VDD = 2.0V
VDD = 3.3-5.0V
ns
ns
FIGURE 23-8:
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O pins
Note 1: Asserted low.
DS41341B-page 224
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 23-9:
VDD
VBOR and VHYST
VBOR
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to 0. 2 ms
delay if PWRTE = 0 and VREGEN = 1.
Preliminary
DS41341B-page 225
PIC16F72X/PIC16LF72X
TABLE 23-4:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
30
TMCL
2
5
s
s
31
10
10
18
18
27
33
ms
ms
32
TOST
1024
Tosc (Note 3)
(2)
33*
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.40
1.80
2.5
1.9
2.60
2.00
36*
VHYST
25
50
75
100
mV
-40C to +85C
-40C to 125C
37*
5
10
Note 1:
2:
3:
4:
BORV=2.5V
BORV=1.9V
DS41341B-page 226
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 23-10:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 23-5:
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
No Prescaler
With Prescaler
TT0L
41*
No Prescaler
With Prescaler
Typ
Max.
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
42*
TT0P
T0CKI Period
45*
TT1H
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
TT1L
46*
T1CKI Low
Time
47*
TT1P
48
FT1
49*
Asynchronous
60
ns
32.4
32.768
33.1
kHz
2 TOSC
7 TOSC
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
Preliminary
DS41341B-page 227
PIC16F72X/PIC16LF72X
FIGURE 23-11:
CCPx
(Capture mode)
CC01
CC02
CC03
Note:
TABLE 23-6:
Characteristic
CC01* TccL
CC02* TccH
CC03* TccP
*
Min.
Typ
Max.
Units
0.5TCY + 20
ns
With Prescaler
20
ns
No Prescaler
0.5TCY + 20
ns
With Prescaler
20
ns
3TCY + 40
N
ns
No Prescaler
Conditions
TABLE 23-7:
Characteristic
Min.
Typ
Max.
Units
Conditions
AD01
NR
Resolution
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
2.2
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
AD09* IREF
Note 1:
2:
3:
4:
Gain Error
bit
LSb VREF = 3.0V
LSb No missing codes
VREF = 3.0V
1.5
1.8
VDD
VSS
VREF
Recommended Impedance of
Analog Voltage Source
50
10
1000
10
V
V
DS41341B-page 228
Preliminary
PIC16F72X/PIC16LF72X
TABLE 23-8:
Sym.
Characteristic
AD130* TAD
AD131
TCNV
AD132* TACQ
Min.
Typ
Max.
Units
Conditions
1.0
9.0
TOSC-based
1.0
1.6
6.0
10.5
TAD
Acquisition Time
9.5
FIGURE 23-12:
BSF ADCON0, GO
AD134
1 TCY
(TOSC/2(1))
AD131
Q4
AD130
A/D CLK
7
A/D Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
Preliminary
DS41341B-page 229
PIC16F72X/PIC16LF72X
FIGURE 23-13:
BSF ADCON0, GO
(TOSC/2 + TCY(1))
AD134
1 TCY
AD131
Q4
AD130
A/D CLK
7
A/D Data
0
NEW_DATA
OLD_DATA
ADRES
ADIF
1 TCY
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
FIGURE 23-14:
CK
US121
US121
DT
US122
US120
Note:
TABLE 23-9:
Symbol
Characteristic
Min.
Max.
Units
3.0-5.5V
80
ns
1.8-5.5V
100
ns
US121 TCKRF
3.0-5.5V
45
ns
1.8-5.5V
50
ns
3.0-5.5V
45
ns
1.8-5.5V
50
ns
US122 TDTRF
DS41341B-page 230
Preliminary
Conditions
PIC16F72X/PIC16LF72X
FIGURE 23-15:
Symbol
Characteristic
Preliminary
Min.
Max.
Units
10
ns
15
ns
Conditions
DS41341B-page 231
PIC16F72X/PIC16LF72X
FIGURE 23-16:
SS
SP70
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
bit 6 - - - - - -1
MSb
SDO
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 23-2 for load conditions.
FIGURE 23-17:
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SDO
MSb
bit 6 - - - - - -1
LSb
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 23-2 for load conditions.
DS41341B-page 232
Preliminary
PIC16F72X/PIC16LF72X
FIGURE 23-18:
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SP78
SCK
(CKP = 1)
SP80
MSb
SDO
LSb
bit 6 - - - - - -1
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
SP73
Note: Refer to Figure 23-2 for load conditions.
FIGURE 23-19:
SS
SCK
(CKP = 0)
SP71
SP72
SCK
(CKP = 1)
SP80
MSb
SDO
bit 6 - - - - - -1
LSb
SP77
SP75, SP76
SDI
MSb In
bit 6 - - - -1
LSb In
SP74
Note: Refer to Figure 23-2 for load conditions.
Preliminary
DS41341B-page 233
PIC16F72X/PIC16LF72X
TABLE 23-11: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ
TCY
ns
SP71* TSCH
TCY + 20
ns
SP72* TSCL
TCY + 20
ns
100
ns
SP74* TSCH2DIL,
TSCL2DIL
100
ns
SP75* TDOR
10
25
ns
SP76* TDOF
3.0-5.5V
1.8-5.5V
25
50
ns
10
25
ns
SP77* TSSH2DOZ
10
50
ns
SP78* TSCR
3.0-5.5V
10
25
ns
1.8-5.5V
25
50
ns
SP79* TSCF
10
25
ns
3.0-5.5V
50
ns
1.8-5.5V
145
ns
Tcy
ns
SP82* TSSL2DOV
50
ns
1.5TCY + 40
ns
FIGURE 23-20:
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note: Refer to Figure 23-2 for load conditions.
DS41341B-page 234
Preliminary
PIC16F72X/PIC16LF72X
TABLE 23-12: I2C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol
Characteristic
SP90*
TSU:STA
SP91*
THD:STA
SP92*
TSU:STO
SP93
Start condition
Typ
4700
Max. Units
Setup time
600
Start condition
4000
Hold time
600
Stop condition
4700
Setup time
Hold time
*
Min.
600
4000
600
Conditions
ns
ns
ns
ns
FIGURE 23-21:
SP100
SP102
SP101
SCL
SP90
SP106
SP107
SP92
SP91
SDA
In
SP110
SP109
SP109
SDA
Out
Note: Refer to Figure 23-2 for load conditions.
Preliminary
DS41341B-page 235
PIC16F72X/PIC16LF72X
TABLE 23-13: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
SP100* THIGH
Characteristic
Clock high time
Min.
Max.
Units
4.0
0.6
1.5TCY
4.7
1.3
SSP Module
SP101* TLOW
SSP Module
SP102* TR
SP103* TF
SP90*
SP91*
TSU:STA
THD:STA
SP106* THD:DAT
SP107* TSU:DAT
SP92*
TSU:STO
SP109* TAA
SP110*
SP111
*
Note 1:
2:
TBUF
CB
Conditions
1.5TCY
1000
ns
0.1CB
300
ns
250
ns
20 + 0.1CB
250
ns
CB is specified to be from
10-400 pF
Only relevant for
Repeated Start condition
20 +
4.7
0.6
4.0
0.6
ns
0.9
250
ns
100
ns
Start condition
setup time
4.7
0.6
3500
ns
ns
4.7
1.3
400
pF
CB is specified to be from
10-400 pF
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
DS41341B-page 236
Preliminary
PIC16F72X/PIC16LF72X
TABLE 23-14: CAP SENSE OSCILLATOR SPECIFICATIONS
Param.
No.
CS01
CS02
Symbol
ISRC
ISNK
Characteristic
Current Source
Current Sink
High
Min.
Typ
Max.
Units
Conditions
-5.8
Medium
-1.1
Low
-0.2
High
6.6
Medium
1.3
Low
0.24
CS03
VCTH
Cap Threshold
High
0.8
CS04
VCTL
Cap Threshold
Low
0.4
FIGURE 23-22:
VCTH
VCTL
ISRC
Enabled
ISNK
Enabled
Preliminary
DS41341B-page 237
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 238
Preliminary
PIC16F72X/PIC16LF72X
24.0
DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Preliminary
DS41341B-page 239
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 240
Preliminary
PIC16F72X/PIC16LF72X
25.0
PACKAGING INFORMATION
25.1
28-Lead SPDIP
Example
PIC16F722
-I/SP e3
0810017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F724
-I/P e3
0810017
Example
28-Lead QFN
16F722
-I/ML e3
0810017
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
Preliminary
DS41341B-page 241
PIC16F72X/PIC16LF72X
Package Marking Information (Continued)
Example
44-Lead QFN
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F724
-I/ML e3
0810017
28-Lead SOIC
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F722
-I/SO e3
0810017
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16F722
-I/SS e3
0810017
44-Lead TQFP
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
DS41341B-page 242
PIC16F727
-I/PT e3
0810017
Preliminary
PIC16F72X/PIC16LF72X
25.2
Package Details
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DS41341B-page 243
PIC16F72X/PIC16LF72X
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Preliminary
PIC16F72X/PIC16LF72X
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Preliminary
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DS41341B-page 247
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Preliminary
PIC16F72X/PIC16LF72X
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PIC16F72X/PIC16LF72X
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DS41341B-page 250
Preliminary
PIC16F72X/PIC16LF72X
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DS41341B-page 251
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DS41341B-page 252
Preliminary
PIC16F72X/PIC16LF72X
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
APPENDIX B:
MIGRATING FROM
OTHER PIC
DEVICES
Original release.
Revision B
Electrical Specification updates; Package Drawings;
miscellaneous updates.
B.1
PIC16F77 to PIC16F72X
TABLE B-1:
FEATURE COMPARISON
Feature
PIC16F77
PIC16F727
20 MHz
20 MHz
8K
8K
Max. Program
Memory (Words)
Max. SRAM (Bytes)
368
368
A/D Resolution
8-bit
8-bit
Timers (8/16-bit)
2/1
2/1
Oscillator Modes
Brown-out Reset
Internal Pull-ups
RB<7:0>
RB<7:0>
Interrupt-on-change
RB<7:4>
RB<7:0>
Comparator
USART
Extended WDT
Software Control
Option of WDT/BOR
INTOSC Frequencies
None
Clock Switching
Preliminary
DS41341B-page 253
PIC16F72X/PIC16LF72X
NOTES:
DS41341B-page 254
Preliminary
PIC16F72X/PIC16LF72X
INDEX
A
A/D
Specifications.................................................... 228, 229
Absolute Maximum Ratings .............................................. 209
AC Characteristics
Industrial and Extended ............................................ 220
Load Conditions ........................................................ 219
ADC .................................................................................... 97
Acquisition Requirements ......................................... 104
Associated registers.................................................. 106
Block Diagram............................................................. 97
Calculating Acquisition Time..................................... 104
Channel Selection....................................................... 98
Configuration............................................................... 98
Configuring Interrupt ................................................. 101
Conversion Clock........................................................ 98
Conversion Procedure .............................................. 101
Internal Sampling Switch (RSS) Impedance.............. 104
Interrupts................................................................... 100
Operation .................................................................. 100
Operation During Sleep ............................................ 100
Port Configuration ....................................................... 98
Reference Voltage (VREF)........................................... 98
Source Impedance.................................................... 104
Special Event Trigger................................................ 100
ADCON0 Register....................................................... 22, 102
ADCON1 Register....................................................... 23, 103
Addressable Universal Synchronous Asynchronous
Receiver Transmitter (AUSART).............................. 143
ADRES Register ......................................................... 22, 103
Alternate Pin Function......................................................... 51
Analog-to-Digital Converter. See ADC
ANSELA Register ............................................................... 53
ANSELB Register ............................................................... 62
ANSELD Register ............................................................... 79
ANSELE Register ............................................................... 84
APFCON Register......................................................... 23, 51
Assembler
MPASM Assembler................................................... 206
AUSART ........................................................................... 143
Associated Registers
Baud Rate Generator........................................ 154
Asynchronous Mode ................................................. 145
Associated Registers
Receive..................................................... 151
Transmit.................................................... 147
Baud Rate Generator (BRG) ............................ 154
Receiver............................................................ 148
Setting up 9-bit Mode with Address Detect....... 150
Transmitter........................................................ 145
Baud Rate Generator (BRG)
Baud Rate Error, Calculating ............................ 154
Baud Rates, Asynchronous Modes .................. 155
Formulas ........................................................... 154
High Baud Rate Select (BRGH Bit) .................. 154
Synchronous Master Mode ............................... 157, 161
Associated Registers
Receive..................................................... 160
Transmit.................................................... 158
Reception.......................................................... 159
Transmission .................................................... 157
B
BF bit ........................................................................ 173, 185
Block Diagram
Capacitive Sensing................................................... 127
Block Diagrams
(CCP) Capture Mode Operation ............................... 135
ADC ............................................................................ 97
ADC Transfer Function............................................. 105
Analog Input Model................................................... 105
AUSART Receive ..................................................... 144
AUSART Transmit .................................................... 143
CCP PWM ................................................................ 139
Clock Source .............................................................. 87
Compare................................................................... 137
Crystal Operation........................................................ 91
External RC Mode ...................................................... 92
Interrupt Logic............................................................. 41
MCLR Circuit .............................................................. 33
On-Chip Reset Circuit................................................. 31
PIC16F722/723/726/PIC16LF722/723/726 ................ 12
PIC16F724/727/PIC16LF724/727 .............................. 13
RA0 Pins..................................................................... 55
RA4 Pin ...................................................................... 56
RA5 Pin ...................................................................... 57
RA6 Pin ...................................................................... 58
RA7 Pin ...................................................................... 58
RB0 Pin ...................................................................... 64
RB3 Pin ...................................................................... 66
RB4, RB2, RB1 Pins................................................... 65
RB5 Pin ...................................................................... 67
RB6 Pin ...................................................................... 68
RB7 Pin ...................................................................... 69
RC0 Pin ...................................................................... 73
RC1 Pin ...................................................................... 73
RC2 Pin ...................................................................... 74
RC3 Pin ...................................................................... 74
RC4 Pin ...................................................................... 75
RC5 Pin ...................................................................... 75
RC6 Pin ...................................................................... 76
RC7 Pin ...................................................................... 76
RD Pins ...................................................................... 80
RE Pins....................................................................... 86
RE3 Pin ...................................................................... 86
Resonator Operation .................................................. 92
SPI Mode.................................................................. 166
SSP (I2C Mode)........................................................ 175
Timer1 .............................................. 113, 119, 120, 121
Timer2 ...................................................................... 125
TMR0/WDT Prescaler .............................................. 109
Brown-out Reset (BOR)...................................................... 35
Specifications ........................................................... 226
Timing and Characteristics ....................................... 225
Preliminary
DS41341B-page 255
PIC16F72X/PIC16LF72X
C
C Compilers
MPLAB C18 .............................................................. 206
MPLAB C30 .............................................................. 206
Capacitive Sensing ........................................................... 127
Associated registers w/ Capacitive Sensing ............. 132
Capture Module. See Capture/Compare/PWM (CCP)
Capture/Compare/PWM (CCP)......................................... 133
Associated registers w/ Capture ............................... 136
Associated registers w/ Compare ............................. 138
Associated registers w/ PWM ................................... 142
Capture Mode ........................................................... 135
CCPx Pin Configuration ............................................ 135
Compare Mode ......................................................... 137
CCPx Pin Configuration .................................... 137
Software Interrupt Mode ........................... 135, 137
Special Event Trigger........................................ 137
Timer1 Mode Selection ............................. 135, 137
Interaction of Two CCP Modules (table) ................... 133
Prescaler ................................................................... 135
PWM Mode ............................................................... 139
Duty Cycle......................................................... 140
Effects of Reset................................................. 141
Example PWM Frequencies and
Resolutions, 20 MHZ ................................ 141
Example PWM Frequencies and
Resolutions, 8 MHz................................... 141
Operation in Sleep Mode .................................. 141
Setup for Operation........................................... 141
System Clock Frequency Changes................... 141
PWM Period .............................................................. 140
Setup for PWM Operation ......................................... 141
Timer Resources....................................................... 133
CCP. See Capture/Compare/PWM (CCP)
CCP1CON Register ............................................................ 22
CCP2CON Register ............................................................ 22
CCPR1H Register ............................................................... 22
CCPR1L Register................................................................ 22
CCPR2H Register ............................................................... 22
CCPR2L Register................................................................ 22
CCPxCON Register .......................................................... 134
CKE bit ...................................................................... 173, 185
CKP bit ...................................................................... 172, 184
Clock Sources
External Modes ........................................................... 91
EC ....................................................................... 91
HS ....................................................................... 91
LP........................................................................ 91
OST..................................................................... 91
RC....................................................................... 92
XT ....................................................................... 91
Code Examples
A/D Conversion ......................................................... 101
Call of a Subroutine in Page 1 from Page 0................ 28
Changing Between Capture Prescalers .................... 135
Indirect Addressing ..................................................... 29
Initializing PORTA ....................................................... 52
Initializing PORTB ....................................................... 60
Initializing PORTC....................................................... 71
Initializing PORTD....................................................... 78
Initializing PORTE ....................................................... 82
Loading the SSPBUF (SSPSR) Register .................. 168
Saving W, STATUS and PCLATH Registers
in RAM ............................................................... 43
DS41341B-page 256
Comparators
C2OUT as T1 Gate................................................... 116
Compare Module. See Capture/Compare/PWM (CCP)
CONFIG1 Register ....................................................... 93, 94
CPSCON0 Register .......................................................... 131
CPSCON1 Register .......................................................... 132
Customer Change Notification Service............................. 261
Customer Notification Service .......................................... 261
Customer Support............................................................. 261
D
D/A bit ............................................................................... 185
Data Memory ...................................................................... 18
Data/Address bit (D/A)...................................................... 185
DC and AC Characteristics............................................... 239
DC Characteristics
Extended and Industrial ............................................ 216
Industrial and Extended ............................................ 210
Development Support ....................................................... 205
Device Configuration .......................................................... 93
Code Protection .......................................................... 95
Configuration Word..................................................... 93
User ID ....................................................................... 95
Device Overview................................................................. 11
E
Effects of Reset
PWM mode ............................................................... 141
Electrical Specifications .................................................... 209
Enhanced Capture/Compare/PWM (ECCP)
Specifications ........................................................... 228
Errata .................................................................................. 10
F
Firmware Instructions ....................................................... 195
Fixed Voltage Reference. See FVR
FSR Register ................................................................ 22, 23
Fuses. See Configuration Bits
FVR................................................................................... 107
FVRCON Register ...................................................... 23, 107
G
General Purpose Register File ........................................... 18
I
I2C Mode
Associated Registers ................................................ 186
INDF Register ............................................................... 22, 23
Indirect Addressing, INDF and FSR Registers ................... 29
Instruction Format............................................................. 195
Instruction Set................................................................... 195
ADDLW..................................................................... 197
ADDWF..................................................................... 197
ANDLW..................................................................... 197
ANDWF..................................................................... 197
MOVF ....................................................................... 200
BCF .......................................................................... 197
BSF........................................................................... 197
BTFSC ...................................................................... 197
BTFSS ...................................................................... 198
CALL......................................................................... 198
CLRF ........................................................................ 198
CLRW ....................................................................... 198
CLRWDT .................................................................. 198
COMF ....................................................................... 198
DECF ........................................................................ 198
Preliminary
PIC16F72X/PIC16LF72X
DECFSZ.................................................................... 199
GOTO ....................................................................... 199
INCF.......................................................................... 199
INCFSZ ..................................................................... 199
IORLW ...................................................................... 199
IORWF ...................................................................... 199
MOVLW .................................................................... 200
MOVWF .................................................................... 200
NOP .......................................................................... 200
RETFIE ..................................................................... 201
RETLW ..................................................................... 201
RETURN ................................................................... 201
RLF ........................................................................... 202
RRF........................................................................... 202
SLEEP ...................................................................... 202
SUBLW ..................................................................... 202
SUBWF ..................................................................... 203
SWAPF ..................................................................... 203
XORLW..................................................................... 203
XORWF..................................................................... 203
Summary Table......................................................... 196
INTCON Register ................................................................ 44
Internal Oscillator Block
INTOSC
Specifications.................................................... 223
Internal Sampling Switch (RSS) Impedance ...................... 104
Internet Address................................................................ 261
Interrupts ............................................................................. 41
ADC .......................................................................... 101
Associated registers w/ Interrupts............................... 48
Interrupt-on-Change.................................................... 60
TMR1 ........................................................................ 118
INTOSC Specifications ..................................................... 223
IOCB Register ..................................................................... 62
L
Load Conditions ................................................................ 219
M
MCLR .................................................................................. 33
Internal ........................................................................ 33
............................................................................................ 17
Data ............................................................................ 18
Program ...................................................................... 17
.......................................... 261, 253, 206, 207, 205, 207, 206
O
OPCODE Field Descriptions ............................................. 195
OPTION Register ................................................................ 26
OPTION_REG Register .................................................... 111
OSCCON Register .............................................................. 89
Oscillator
Associated registers............................................ 92, 124
Oscillator Module
EC ............................................................................... 87
HS ............................................................................... 87
INTOSC ...................................................................... 87
INTOSCIO................................................................... 87
LP................................................................................ 87
Oscillator Tuning ......................................................... 90
RC............................................................................... 87
RCIO ........................................................................... 87
XT ............................................................................... 87
Oscillator Parameters ....................................................... 223
Oscillator Specifications .................................................... 222
Oscillator Start-up Timer (OST)
P
P (Stop) bit........................................................................ 185
Packaging ......................................................................... 241
Marking............................................................. 241, 242
PDIP Details ............................................................. 243
Paging, Program Memory................................................... 28
PCL and PCLATH............................................................... 28
Computed GOTO ....................................................... 28
Stack........................................................................... 28
PCL Register ................................................................ 22, 23
PCLATH Register ......................................................... 22, 23
PCON Register ....................................................... 23, 27, 36
PICSTART Plus Development Programmer..................... 208
PIE1 Register ............................................................... 23, 45
PIE2 Register ............................................................... 23, 46
Pin Diagram
PIC16F722/723/726, 28-pin PDIP/SOIC/SSOP/QFN... 3
PIC16F724/727, 40-pin PDIP ....................................... 5
PIC16F724/727, 44-pin QFN........................................ 7
PIC16F724/727, 44-pin TQFP...................................... 6
Pinout Descriptions
PIC16F72X/PIC16LF72X ........................................... 14
PIR1 Register ............................................................... 22, 47
PIR2 Register ............................................................... 22, 48
PMADRH Register............................................................ 189
PMADRL Register ............................................................ 189
PMCON1 Register .............................................. 24, 188, 189
PMDATH Register ............................................................ 188
PMDATL Register............................................................. 188
PORTA ............................................................................... 52
ANSELA Register ....................................................... 53
Associated Registers.................................................. 59
Pin Descriptions and Diagrams .................................. 54
PORTA Register......................................................... 22
RA0............................................................................. 54
RA1............................................................................. 54
RA2............................................................................. 54
RA3............................................................................. 54
RA4............................................................................. 54
RA5............................................................................. 54
RA6............................................................................. 54
RA7............................................................................. 54
Specifications ........................................................... 224
PORTA Register ................................................................. 52
PORTB ............................................................................... 60
Additional Pin Functions
ANSELB Register ............................................... 60
Weak Pull-up ...................................................... 60
Associated Registers.................................................. 70
Interrupt-on-Change ................................................... 60
P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM+ (ECCP+) ................................................. 60
Pin Descriptions and Diagrams .................................. 63
PORTB Register......................................................... 22
RB0............................................................................. 63
RB1............................................................................. 63
RB2............................................................................. 63
RB3............................................................................. 63
RB4............................................................................. 63
RB5............................................................................. 63
RB6............................................................................. 63
RB7............................................................................. 63
PORTB Register ................................................................. 61
Preliminary
DS41341B-page 257
PIC16F72X/PIC16LF72X
PORTC................................................................................ 71
Associated Registers .................................................. 77
P1A.See Enhanced Capture/Compare/PWM+
(ECCP+) ............................................................. 71
PORTC Register ......................................................... 22
RC0 ............................................................................. 72
RC2 ............................................................................. 72
RC3 ............................................................................. 72
RC4 ............................................................................. 72
RC5 ............................................................................. 72
RC6 ............................................................................. 72
RC7 ............................................................................. 72
Specifications ............................................................ 224
PORTC Register ................................................................. 71
PORTD................................................................................ 78
Additional Pin Functions
ANSELD Register ............................................... 78
Associated Registers .................................................. 81
P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM+ (ECCP+).................................................. 78
PORTD Register ......................................................... 22
RD6 ............................................................................. 80
PORTD Register ................................................................. 78
PORTE................................................................................ 82
Associated Registers .................................................. 84
PORTE Register ......................................................... 22
RE0 ............................................................................. 85
RE1 ............................................................................. 85
RE2 ............................................................................. 85
RE3 ............................................................................. 85
PORTE Register ................................................................. 83
Power-Down Mode (Sleep) ............................................... 191
Associated Registers ................................................ 192
Power-on Reset .................................................................. 33
Power-up Timer (PWRT)..................................................... 33
Specifications ............................................................ 226
PR2 Register............................................................... 23, 174
Precision Internal Oscillator Parameters........................... 223
Prescaler
Shared WDT/Timer0 ................................................. 110
Product Identification System............................................ 263
Program Memory ................................................................ 17
Map and Stack (PIC16F722/LF722) ........................... 17
Map and Stack (PIC16F723/LF723 and
PIC16F724/LF724) ............................................. 17
Map and Stack (PIC16F726/LF726 and
PIC16F727/LF727) ............................................. 18
Paging ......................................................................... 28
Program Memory Read (PMR) ......................................... 187
Associated Registers ................................................ 189
Programming, Device Instructions .................................... 195
R
R/W bit .............................................................................. 185
RCREG ............................................................................. 150
RCREG Register................................................................. 22
RCSTA Register.......................................................... 22, 153
Reader Response ............................................................. 262
Read-Modify-Write Operations.......................................... 195
Receive Overflow Indicator bit (SSPOV)................... 172, 184
Registers
ADCON0 (ADC Control 0) ........................................ 102
ADCON1 (ADC Control 1) ........................................ 103
ADRES (ADC Result) ............................................... 103
ANSELA (PORTA Analog Select) ............................... 53
ANSELB (PORTB Analog Select) ............................... 62
DS41341B-page 258
S
S (Start) bit........................................................................ 185
SMP bit ..................................................................... 173, 185
Software Simulator (MPLAB SIM) .................................... 206
SPBRG ............................................................................. 154
SPBRG Register................................................................. 23
Special Event Trigger ....................................................... 100
Special Function Registers ................................................. 18
Special Function Registers (SFRs)..................................... 22
SPI Mode .......................................................................... 171
Preliminary
PIC16F72X/PIC16LF72X
Associated Registers ................................................ 174
Typical Master/Slave Connection ............................. 165
SSP ................................................................................... 165
I2C Mode................................................................... 175
Acknowledge .................................................... 176
Addressing ........................................................ 177
Clock Stretching................................................ 182
Clock Synchronization ...................................... 183
Firmware Master Mode ..................................... 182
Hardware Setup ................................................ 175
Multi-Master Mode ............................................ 182
Reception.......................................................... 178
Sleep Operation ................................................ 183
Start/Stop Conditions ........................................ 176
Transmission .................................................... 180
Master Mode ............................................................. 167
SPI Mode .................................................................. 165
Slave Mode ....................................................... 169
Typical SPI Master/Slave Connection....................... 165
SSPADD Register ............................................................... 23
SSPBUF Register ............................................................... 22
SSPCON Register .............................................. 22, 172, 184
SSPEN bit ................................................................. 172, 184
SSPM bits ................................................................. 172, 184
SSPMSK Register............................................................... 23
SSPOV bit ................................................................. 172, 184
SSPSTAT Register ............................................. 23, 173, 185
STATUS Register ............................................................... 25
Synchronous Serial Port Enable bit (SSPEN)........... 172, 184
Synchronous Serial Port Mode Select bits (SSPM) .. 172, 184
T
T1CON Register ......................................................... 22, 122
TMR1ON Bit.............................................................. 123
T1GCON Register............................................................. 123
T2CON Register ................................................. 22, 126, 174
Thermal Considerations .................................................... 218
Time-out Sequence............................................................. 36
Timer0 ............................................................................... 109
Associated Registers ................................................ 111
Interrupt..................................................................... 111
Operation .......................................................... 109, 114
Specifications............................................................ 227
Timer1 ............................................................................... 113
Associated registers.................................................. 124
Asynchronous Counter Mode ................................... 115
Reading and Writing ......................................... 115
Interrupt..................................................................... 118
Modes of Operation .................................................. 114
Module On/Off (TMR1ON Bit)................................... 123
Operation During Sleep ............................................ 118
Oscillator ................................................................... 115
Prescaler................................................................... 115
Specifications............................................................ 227
Timer1 Gate
Selecting Source............................................... 116
TMR1H Register ....................................................... 113
TMR1L Register........................................................ 113
Timer2
Associated registers.................................................. 126
Timers
Timer1
T1CON.............................................................. 122
T1GCON ........................................................... 123
Timer2
T2CON.............................................................. 126
Timing Diagrams
A/D Conversion ........................................................ 229
A/D Conversion (Sleep Mode).................................. 230
Asynchronous Reception.......................................... 150
Asynchronous Transmission .................................... 146
Asynchronous Transmission (Back-to-Back)............ 146
Brown-out Reset (BOR)............................................ 225
Brown-out Reset Situations ........................................ 35
CLKOUT and I/O ...................................................... 223
Clock Synchronization .............................................. 183
Clock Timing............................................................. 220
Enhanced Capture/Compare/PWM (ECCP)............. 228
I2C Bus Data............................................................. 235
I2C Bus Start/Stop Bits ............................................. 234
I2C Reception (7-bit Address)................................... 178
I2C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................. 179
I2C Transmission (7-bit Address) ............................. 180
INT Pin Interrupt ......................................................... 42
Reset, WDT, OST and Power-up Timer ................... 224
Slave Select Synchronization ................................... 171
SPI Master Mode...................................................... 168
SPI Master Mode (CKE = 1, SMP = 1) ..................... 232
SPI Mode (Slave Mode with CKE = 0)...................... 170
SPI Mode (Slave Mode with CKE = 1)...................... 170
SPI Slave Mode (CKE = 0) ....................................... 233
SPI Slave Mode (CKE = 1) ....................................... 233
Synchronous Reception (Master Mode, SREN) ....... 160
Synchronous Transmission ...................................... 158
Synchronous Transmission (Through TXEN) ........... 158
Time-out Sequence
Case 1 ................................................................ 37
Case 2 ................................................................ 37
Case 3 ................................................................ 37
Timer0 and Timer1 External Clock ........................... 227
Timer1 Incrementing Edge ....................................... 118
USART Synchronous Receive (Master/Slave) ......... 231
USART Synchronous Transmission
(Master/Slave) .................................................. 230
Wake-up from Interrupt............................................. 192
Timing Parameter Symbology .......................................... 219
Timing Requirements
I2C Bus Data..................................................... 236, 235
SPI Mode.................................................................. 234
TMR0 Register.................................................................... 22
TMR1H Register ................................................................. 22
TMR1L Register.................................................................. 22
TMR2 Register.................................................................... 22
TMRO Register................................................................... 24
TRISA ................................................................................. 52
TRISA Register............................................................. 23, 52
TRISB ................................................................................. 60
TRISB Register............................................................. 23, 61
TRISC ................................................................................. 71
TRISC Register............................................................. 23, 71
TRISD ................................................................................. 78
TRISD Register............................................................. 23, 79
TRISE ................................................................................. 82
TRISE Register............................................................. 23, 83
TXREG ............................................................................. 145
TXREG Register ................................................................. 22
TXSTA Register.......................................................... 23, 152
BRGH Bit .................................................................. 154
Preliminary
DS41341B-page 259
PIC16F72X/PIC16LF72X
U
UA ..................................................................................... 185
Update Address bit, UA..................................................... 185
USART
Synchronous Master Mode
Requirements, Synchronous Receive............... 231
Requirements, Synchronous Transmission ...... 230
Timing Diagram, Synchronous Receive............ 231
Timing Diagram, Synchronous Transmission ... 230
V
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts ................................................. 192
Watchdog Timer (WDT) ...................................................... 33
Clock Source............................................................... 33
Modes ......................................................................... 34
Period.......................................................................... 33
Specifications ............................................................ 226
WCOL bit................................................................... 172, 184
WPUB Register ................................................................... 62
Write Collision Detect bit (WCOL)............................. 172, 184
WWW Address.................................................................. 261
WWW, On-Line Support...................................................... 10
DS41341B-page 260
Preliminary
PIC16F72X/PIC16LF72X
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://support.microchip.com
Preliminary
DS41341B-page 261
PIC16F72X/PIC16LF72X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Device: PIC16F72X/PIC16LF72X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
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4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
DS41341B-page 262
Preliminary
PIC16F72X/PIC16LF72X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
/XX
XXX
Device
Temperature
Range
Package
Pattern
Examples:
a)
b)
Device:
Temperature
Range:
I
E
=
=
-40C to +85C
-40C to +125C
Package:
ML
P
PT
SO
SP
SS
=
=
=
=
=
=
Pattern:
Note 1:
Preliminary
DS41341B-page 263
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
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Tel: 480-792-7200
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Tel: 91-80-4182-8400
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Fax: 43-7242-2244-393
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Tel: 33-1-69-53-63-20
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China - Hong Kong SAR
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
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Tel: 886-7-536-4818
Fax: 886-7-536-4803
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Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
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Fax: 86-29-8833-7256
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Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS41341B-page 264
Preliminary