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Sequential Circuits

The output depends not only on the current inputs, but


also on the past values of the inputs. This is how a digital
circuit remembers data. Let us see ho a single bit is
stored.

An SR Latch
S

Q
R = Reset, S= Set

Comment

1/0

Old state continues

0/1

Set state

Reset state

Illegal inputs

A clocked D-latch

Clock C
Q

Q (not Q)

Clock is the enabler. If C=0, Q remains unchanged.


When C=1, then Q acquires the value of D. We will use it
as a building block of sequential circuits.
D

D-latch
C

There are some shortcomings of this simple circuit. An


edge-triggered circuit (or a master-slave circuit) solves
this problem

Master-Slave D flip-flop
D

Clock

D-latch

D-latch

Internal details shown above

Clock
Clock pulse

Abstract view

The output Q acquires the value of the input D, only when


one complete clock pulse is applied to the clock input.

Register
A 8-bit register is an array of 8 D-flip-flops.
Data input

D- F/F

D-F/F

D-F/F
Q

D-F/F
Q

write

Data out

Abstract view of a register

Binary counter
Counts 0, 1, 2, 3,
D

D-F/F
C

write

A toggle flip-flop (T) is


Q

a modulo-2 counter

D3

D2

D1

D0

Q3

Q2

Q1

Q0

A 4-bit counter
(mod-16 counter)

4-bit adder

Observe how Q3 Q2 Q1 Q0 change when pulses are


applied to the clock input

State diagram of a 4-bit counter


Here state = Q3Q2Q1Q0
0
15

14

13

Recall that the program counter is a 32-bit counter

A shift register
D

D- F/F

D-F/F

Shift (right)

With each pulse

D-F/F
Q

D-F/F
Q

Hardware Multiplication
Multiplicand

Multiplier

Product

The basic operations are ADD and SHIFT. Now let


us see how it is implemented by hardware.

By now, you know all the building blocks.

The Building Blocks


A shift register
Review how a D flip-flop works

D- F/F

D-F/F

D-F/F
Q

D-F/F
Q

Shift (right)

With each clock pulse on the shift line, data moves one
place to the right.

Executing r1:= r2
How to implement a simple register transfer r1:= r2?

R2
32-bit reg
32

Write

R1

Clock

32-bit reg

It requires only one clock pulse to complete the


operation.

Executing r1:= r1 + r2

R2
32-bit reg
32

32-bit
Adder
SUM
32

32
CLOCK

R1
32-bit reg

Write

It requires only one clock pulse to complete the


operation.

A Hardware Multiplier
Occupies the
right half
Shift left

Multiplicand

0
64-bit reg

64

64-bit
ALU

Add

Right shift

Multiplier
LSB

Initially 0
64

64

Product
64-bit reg

Control
Write

If LSB of Multiplier = 1 then add else skip;


Shift left multiplicand & shift right multiplier

How to implement the control unit?

Division
The restoring division algorithm follows the simple
idea from the elementary school days. It involves
subtraction and shift. Here is an implementation by
hardware
Shift right

Divisor

0s

64-bit
64

64-bit
ALU

64

Subtract/Add

Quotient

Left
Shift

64

Dividend / Remainder
64-bit

Test if negative or not

Control
Write