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Asia Pacific Equity Research

11 June 2013

Semiconductors Simplified
An investor guide to the Semi supply chain
“Semiconductors Simplified” is a primer for investors new to the semiconductor
supply chain.
The first part of this guide explains the basics of semiconductors, typical process
flow in semiconductor wafer fabrication and packaging, and important primary
concepts such as Moore’s Law. It also discusses some of the new buzzwords in
the semiconductor industry, such as 3D IC stacking and FinFETs.

Technology - Semiconductors
Gokul Hariharan

AC

(852) 2800-8564
gokul.hariharan@jpmorgan.com
J.P. Morgan Securities (Asia Pacific) Limited

Rahul Chadha
(886-2) 2725 9898
rahul.z.chadha@jpmorgan.com
J.P. Morgan Securities (Taiwan) Limited

The second part illustrates in detail how value flows through various parts of the
semiconductor manufacturing supply chain (fabless, foundries, back-end
packaging and testing, etc.). It also touches upon how different vendors of the
supply chain are starting to move into each other's turf.

JJ Park
(822) 758-5717
jj.park@jpmorgan.com
J.P. Morgan Securities (Far East) Ltd, Seoul
Branch

Technology supply chain – where do semiconductors sit?
Semiconductor Food chain – “Upstream”

Raw material
suppliers

Foundries

SPE vendors

OSAT/component

Chip inventory
draw-down

Hardware part –“ Downstream”

System makers

Channel
distributors

Component
inventory
draw-down

Channel inventory
draw-down

End demand

Source: J.P. Morgan.

Semiconductor supply chain – block diagram

Source: AMD.

See page 16 for analyst certification and important disclosures, including non-US analyst disclosures.
J.P. Morgan does and seeks to do business with companies covered in its research reports. As a result, investors should be aware that the
firm may have a conflict of interest that could affect the objectivity of this report. Investors should consider this report as only a single factor in
making their investment decision.
www.jpmorganmarkets.com

2 . Why are semiconductors so important? Engineers try to design an apt blend of conductors. Typical examples of conductors are metals such as gold.html. this can be used to represent binary code of 1s and 0s .com Asia Pacific Equity Research 11 June 2013 Semiconductors simplified The following sections are a step by us to simplify the world of semiconductors for global investors. In a digital design. and derive possible analogies to real world processes. transistors are the building blocks of any semiconductor circuit. copper and platinum. with an aim to illustrate various jargon and processes used in the semiconductor industry. which lets the current to flow through it when it is in "on" state. Put it simply. Hence. Transistors – the building block of the IC (Integrated Circuit) As DNA is the basic building block of genes in a human body. and insulators to precisely control the flow of current through the circuit.Gokul Hariharan (852) 2800-8564 gokul. Let’s try to look at transistor as a “power switch”.the basics of any digital design. http://www. offering minimum resistance to the flow of current. the "semi-conductive" nature of semiconductors makes them apt for any circuit design. Examples here include materials like plastics and rubber. Conductors are highly conductive material.hariharan@jpmorgan. have their conductivity in between that of conductors and insulators. Semiconductors. insulators and semiconductors. if the passage of current can be controlled through it. semiconductors. the required functionality can be derived from an electronic circuit. offer very high resistance levels thus making it nearly impossible for current to pass through them.com/content/www/us/en/motherboards/desktopmotherboards/motherboards. on the other hand. as the name suggests. Insulators. a material is classified into three categories – conductors. Source: Intel Corp. What is a semiconductor? In the field of electricity. while no current can pass through it when it's in "off" state – illustrating their ability to switch roles between conductors and insulators. based on the resistance they provide for the passage of current through them.intel. Figure 1: A Packaged Integrated Circuit Figure 2: A PC Motherboard Source: Microchip.

generally known as dies. is packaged in a wear-resistant material. Once the circuit design is firmed up. the whole die. Chip designers are generally classified as fabless or IDM (integrated device manufacturers). transistors are typically printed on a silicon wafer in the desired pattern. Advanced ICs would need to move from “wires” to smaller “balls" or new techniques like Flipchip. tops it up with the desired topping. To do this.com Asia Pacific Equity Research 11 June 2013 When engineers integrate many of these transistors into any design circuit.hariharan@jpmorgan.Gokul Hariharan (852) 2800-8564 gokul. This process is known as wire bonding. the chef usually starts with a circular pizza base. These silicon wafers are then sliced into small rectangular pieces. located at the apex of this chain. Dies are then mounted on a plastic or ceramic base. Once the dies are mounted. dependent on how many transistors should be present on every die. Figure 3: Semiconductor supply chain – block diagram Source: AMD. IC fabrication – the pizza analogy If we were to look at the pizza making process. raw wafers (pizza dough) are taken through a step of processes called photolithography and deposition which results is materials being deposited and circuits being built on the raw wafer (pizza being baked). electrical connections are made between the transistors and are extended outside the die – to enable plug-in to an outer circuit board. bakes it and finally cuts it into required number of slices. 3 . Semiconductor manufacturing Figure 4 below illustrates the various steps in a semiconductor chip manufacture. are engaged in designing and qualifying their chips by various system makers (PC/Handset/TV) for their adoption in respective end-products. which will protect the bare die and wire-bonded interconnects through the lifecycle of the IC. We are not going into the details of these wafer fabrication steps – the lead time for which is usually 2+ months. This process is widely termed as securing a “design win” in the semiconductor industry. it is known as “integrated circuit or integration of many transistors on a circuit”. Finally. The chip designers. We can draw a close analogy of this process to semiconductor manufacturing. with the interconnections etc.

Based on customer’s IC design. IDMs typically design and manufacture chips in-house. given in-house manufacturing by IDMs. and shipped to various channel distributors across the globe. they proceed with the manufacturing of the chip. the past decade has seen dynamic market-share gains by fabless majors against IDMs. Moreover. which impacted their profitability due to significant fixed costs. Second. prudent timing of capex allocation by IDMs became difficult. 4 . foundries fabricate chips by first etching transistors on a silicon wafer followed by slicing them into rectangular shaped “dies”.com Asia Pacific Equity Research 11 June 2013 Figure 4: Technology supply chain Semiconductor Food chain – “Upstream” Raw material suppliers Foundries SPE vendors Hardware part –“ Downstream” OSAT/component Chip inventory draw-down System makers Channel distributors Component inventory draw-down Channel inventory draw-down End demand Source: J. We attribute this industry development to two major factors. however. prudent capex allocations were possible based on proactive capacity allocation & tech advancement discussions in accordance with customer needs.P. due to a diversified customer mix.hariharan@jpmorgan. In addition to this. growth of fabless model worked in favor of foundries. Given outsourced manufacturing model by fabless majors. given the capital intensive nature of the semiconductor industry and dynamic product cycle. While the IDM model worked well in 1990s. where as fabless companies only “design in-house”. Once ready. either in-house (IDM model) or via foundries. maintaining decent utilization rates during a demand down-cycle was difficult. these IC chips are assembled into handsets/PC/consumer electronics devices at various EMS vendors (electronics manufacturing services vendors like Hon-Hai) into final products. they were shielded from both the above mentioned factors.Gokul Hariharan (852) 2800-8564 gokul. even during downturns. as they were able to maintain decent utilization rates. Morgan. What happens post a design win? Once the chip-designer secures a design win. outsource the manufacturing process to contract manufacturers. These dies then undergo backend packaging and test procedures and are finally converted to “integrated circuits” chips (IC chips). First. known as pure-play foundries.

Once designs are finalized.hariharan@jpmorgan. In this stage.Gokul Hariharan (852) 2800-8564 gokul. middle and back end of the line operations (note that this back end is still at Foundry level and is different from traditional terminology on back-end applied to assembly and test operations). foundries specialize in etching layers of transistors on a silicon wafer. Example for ASIC include application processor manufactured by SEC for Apple's iPhone. The Back-end of the Line (BEOL) process consists primarily of forming interconnects among existing circuit layers formed during the FEOL stage and involves a lot of deposition processes since metal (like aluminum or copper) needs to be deposited to form the interconnects between different circuit elements. ASIC are typically developed and customized for an exclusive customers. lithography steps for forming the transistors and etching away excess material. while commodity DRAM (for PC) falls in the category of ASSPs. and then exposing it to an optical lithography tool. but can be adopted by various customers given standard specifications. foundry and OSAT vendors ? Chip-design Typically ICs are classified into two major sub-categories – ASIC (Application specific integrated circuits). the Front End of the Line (FEOL) process consists primarily of transistor formation. The etching process is a combination of first coating the wafer with photoresist layer. 5 . growing different regions of the transistor. and ASSP (application specific standard products). which requires multiple steps of preparing the wafer for transistor fabrication. while ASSP are customized for a specific product. implanting new material on the silicon oxide. Very simply. these are send to Foundries for wafer fabrication. various transistors are connected together thru metal interconnects and undergo a series of chemical processes.com Asia Pacific Equity Research 11 June 2013 What happens at fabless. dielectric material is also used to create insulation layers between different metal interconnects. In the following chart. these processes are roughly divided into 3 sections: Front end. Once etched. Foundry wafer fabrication As mentioned earlier.

which are then packaged and tested – all these combined being termed as the backend steps of the fabrication process. followed by slicing it into rectangular dies. 6 .hariharan@jpmorgan. Once the wafer processing part is finished.com Asia Pacific Equity Research 11 June 2013 Figure 5: Semiconductor Manufacturing – Frontend wafer processing explained Source: AMD. Figure 6: Semiconductor Manufacturing – Backend explained Source: AMD. the wafer is probed for any defects.Gokul Hariharan (852) 2800-8564 gokul.

com Asia Pacific Equity Research 11 June 2013 Figure 7: Semiconductor process flow – Front end and back end process BT resin Substratebased Silicon wafer Wafer probing (sorting) Oxidation layering Dicing Packaging Final test Backendprocess Coating (photo-resisit) Exposure (lithography) Developing & baking Etching Ion implanting Leadframebased Chemical vapor deposition (CVD) Ashing (CMP) CMP slurry DUV Front-endprocess Source: J. 7 . 2. as discussed below: 1. Ingot – The near-100% purity silicon is first melted and perfect silicon ‘seed’ crystal is lowered into it. Morgan.P.Gokul Hariharan (852) 2800-8564 gokul.” 4. 3. A step-by-step look at semiconductor manufacturing process There are usually eight steps of front-end processing. Saw and polish wafer – The ingot is accurately sawed into bare wafers (substrates). Photolithography – This step involves creating repeating circuit patterns onto the wafer by shining light through a stencil-like “mask. Ion implantation – This step beams ions or impurities (dopants) onto the wafer to add conductive properties to individual transistors. The raw wafer is then polished and cleaned to remove impurities and then a photo-resist coating is applied on it.hariharan@jpmorgan. The result is a long rod (ingot) of single-crystal silicon with a diameter of usually 300 mm. Ingot formation could take a few days depending on the pull rate (1-10mm/hour) and ingot length (could be up to 2-3m).

hariharan@jpmorgan. 8. ‘Bonding’ connects the circuit to the electrical contacts of the package. the lead frame) of the package. Source: NXP Corp. 7. Source: Intel Corp. Etching – This step etches away unwanted silicon from the wafer to prepare for gate formation. We talked lithography – why is it so important? Let's think of a conventional lithography process where in an image is printed on a flat metal surface. This is followed by back-end processing. 8 . test. In the back-end operation. Metal layers – This step creates the metal layers to interconnect the transistors within the chip – sometimes over 30 layers! This process also makes the bonding pads that connect the chip itself to the package leads. which essentially refers to the assembly.Gokul Hariharan (852) 2800-8564 gokul. and forms metal gates over the wafer. copper ions create metal connections with transistors. 2. 3. and so to the outside world.com Asia Pacific Equity Research 11 June 2013 5. followed by selective treatment to retain ink. ‘Encapsulation’ (usually by plastic molding) gives the physical and chemical protection to the circuit. ‘Die attach’ attaches the die to the support structure (e. The back-end processing involves various steps which may take from a few days to a few weeks to complete depending on the complexity of the circuit and the logistics involved. while surrounding areas are treated to repel the ink. Metal deposition – This step deposits the wafer in copper sulphate solution. ‘Die preparation’ cuts the wafer into individual integrated circuits or dice. Similarly. 4. adds dielectric layers. semiconductor lithography is used to print transistors on a silicon wafer – termed as etching in semiconductor industry. 6. and packaging of the final integrated circuit so that it can be connected to a printed circuit board (PCB). Gate formation – This step deposits silicon dioxide layers.g.. devices are then assembled using four steps: 1.

000 Ivy Bridge Core i7 1. 9 .000 4004 8080 8008 1.000.hariharan@jpmorgan.000.Asia Pacific Equity Research 11 June 2013 Gokul Hariharan (852) 2800-8564 gokul. there are two possible methods to do this . put forward an interesting observation that the number of transistors on a chip usually doubles every two years. OR 2) technology advancements be made to reduce the size of transistor to fit in more transistors on same wafer area. This process is repeated over and over in a Fabrication process and is the most important part of building integrated circuits on a wafer.000 8086 10.com/content/www/us/en/history/history-intel-chips-timeline-poster.000 Intel Xeon Pentium M Pentrium II 10.000. hence etching the required circuitry on the wafer. What does process migration (moving from 28nm to 20nm) actually mean? Let’s think on how to increase die output per wafer? The answer is to print more transistors per wafer. but this is not very viable as fabs & lithography tools are designed for a particular wafer size.000 Pentrium IV Pentrium 486 Pentrium III 386 286 100.000 1. founder of Intel.html.com Typically.000. 1971-2012 & Moore's Law 10.intel.000. The second option is usually adopted in the semiconductor industry and essentially brings Moore's law into discussion. a foundry coats the wafer with a photo-resist material and exposes it to an optical light beam. Wafer size migrations typically happen once in 12-15 years. Now. thus providing more area for printing. What is Moore’s law? Gordon Moore. http://www. Figure 8: Moore’s Law Microprocessor Transistor Count.000 1970 1975 1980 1985 1990 1995 2000 2005 2010 Source: Intel Corp.000.000.000 Sandy Bridge Core 2 Duo Core 2 Duo 100.1) foundries increase the wafer size.

hence "cramming" more transistors per square inch area on the wafer. there is less leakage of current. hence power consumption profile is improved. hence the area occupied by transistor shrinks by almost half (since area is proportional to square of feature size). This essentially translates in more die output per wafer. More importantly. it speeds up the movement of electrons through them – hence speed is enhanced. If the size of transistors is reduced. in the move from 28nm to 20nm.Gokul Hariharan (852) 2800-8564 gokul. This process migration. This observation made by Gordon Moore seems to have held true over past many decades. at 20nm. The transistor scaling achieved by Moore’s law is also important to drive the virtuous cycle of semiconductor growth: Better scaling gives better performance (more transistors) or cost (cheaper transistors) . leading foundries (such as TMSC) have 28nm under mass production and are working on development of 20nm. Hence. and is popularly known as "Moore's Law". But. thus lowering the overall cost per IC. the semiconductor industry is looking for alternatives on how to extend Moore's law into future years . which drives market growth. Sizes of transistors are generally measured in nanometers since the miniaturization has reached such an extent that smallest feature sizes in modern day transistors are at below 100nm size.which has coined terms like "3D IC and FinFET" as new buzz words. and secondly. larger number of dies can be produced from the same wafer given smaller transistor size. 2007 At present. enabling more transistors for the same area of wafer is the essence of Moore's law.com Asia Pacific Equity Research 11 June 2013 Why is it so popular? Let’s try to evaluate the performance and cost implications of this observation. Figure 9: The Moore’s Law Virtuous Cycle in semiconductors Transistor scaling Better Performance/ Cost Investment Market Growth Source: ITRS More than Moore Paper. size reduction curve for transistors are expected to hit near-limit using current lithography tools. they are essentially shrinking the transistor size to smaller dimensions. the feature size shrinks by 30% or more. For example. When TSMC claims that they are moving from 28nm to 20nm. helping to drive new investment which can push transistor scaling and Moore’s law even further.hariharan@jpmorgan. 10 .

with increasing complexities in transistor fabrication. new construction can be carried out on the available land. As illustrated in the following figures from Amkor and TSMC respectively. thus overcoming the inefficiencies suffered by conventional packaging techniques as transistors goes 3D.5D or 3D arrangement. This mode of manufacturing has been termed as "3D IC manufacturing" by Intel. What’s 3D IC packaging? 3D IC packaging is an extension of scaling that semiconductor vendors have been pushing as process migration leads to denser chips and smaller process geometries. Compared to the planar structure in the diagram on the left. In order to provide housing to this growing population. Silicon in Package. since a 3D structure result in two dies being stacked on top of each other thus reducing the length of interconnection. while TSMC calls it "FinFET". a TSV arrangement can convert 3 separate packages into a single package under a 2. These days. its related packaging techniques has also underwent degree of sophistication over generations of semiconductor devices.Gokul Hariharan (852) 2800-8564 gokul. a term synonymous with 3D IC/FinFET fabrication has been 3D IC packaging. Packaging to go 3D as well As on the front end.hariharan@jpmorgan. As process geometries become smaller and smaller. IC stacking with a silicon interposer and finally true 3D stacking or TSV (thru silicon Via) as shown in the figure below. But what if we exhaust all the available land though the population keeps growing? A possible and viable solution to this problem could be building skyscrapers instead of single storied houses. 11 . Synopsys. It has evolved through different stages . starting from Package on Package. Planar Transistor Structure 3D structure or the Fin. Given limiting size reductions in transistors beyond 20nm. developing enough bonding space through conventional packaging techniques like wire bonding and even solder bumping across the 2D planar structure becomes inefficient. Figure 10: FinFET Transistor vs.com Asia Pacific Equity Research 11 June 2013 3D IC & FinFET – new buzz words Let’s take an example of a city with a constantly growing population base. Similar analogy can be applied to transistors on a silicon wafer. Source: Intel. foundries and IDM are going for the skyscraper mode of transistor fabrication – fabricating in 3D architecture compared to planer 2D manufacturing previously.

Post our discussion on the technological aspects of the semiconductor industry. Amkor.5D & 3D TSV packaging Source: Company reports.Gokul Hariharan (852) 2800-8564 gokul. we try to illustrate 12  How value flows across various steps of semiconductor contract manufacturing (Fabless/Foundry / OSAT) food chain?  Vertical integration that starts to happen within this space. . Figure 12: TSV (COWOS) packaging vs.com Asia Pacific Equity Research 11 June 2013 Figure 11: Migration to 2. conventional Source: TSMC.hariharan@jpmorgan.

US$/chip Testing Margins Testing costs Packaging Margins Revenues for OSAT players = value added during packaging and testing “Value added” pricing model for OSAT Packaging Materials + Substrate Costs Foundry Margins Depreciation + Labor Costs Silicon Wafer + Other Material costs Foundry ASP US$/Wafer Fabless places order to foundry Source: J. 13 .com Asia Pacific Equity Research 11 June 2013 Value pyramid for semiconductor manufacturing chain Figure 13: Semiconductor manufacturing – Value Pyramid Fabless ASP = Cost to ODM/ OEM/EMS (US$/chip) Fabless Margins IP Royality Material COGS for fabless . Morgan.Gokul Hariharan (852) 2800-8564 gokul.hariharan@jpmorgan.P.

Foundry vendors sit at the first stage. doing wafer fabrication.  Pure play PCB players are trying to integrate into substrate to maintain ASP amid shrinking PCB content given rising sophistication in packaging 14 . we conceptualize Wafer Fabrication.Gokul Hariharan (852) 2800-8564 gokul. and then moving it on to the packaging vendors. Packaging/Test. ODM EMS vendors use PCBs to assemble various integrated circuits to make a device.hariharan@jpmorgan. the lines are blurring among these 4 players. As we illustrate below. Packaging vendors source substrates from standalone substrate makers and send it back to Fabless vendors. In the past few years.com Asia Pacific Equity Research 11 June 2013 The four layers from device to Silicon – lines are blurring As shown in the Figure 14.  Substrate vendors have always been engaged in PCBs as well (like Ibiden in Japan) but more substrate vendors are also trying to get into PCB (Kinsus buying Boardtek).  OSAT players trying to integrate material business to achieve leverage of inhouse component sourcing. They are also trying to develop System-In-package solutions to capture more value from PCB vendors (moving board level assembly into the package itself). Substrate and PCB as the 4 degrees of separation between raw silicon and the device. through TSV and COWOS for advanced packaging.  Foundries trying to forward integrate into packaging to capture some value from OSAT players.

15 . Morgan.Gokul Hariharan (852) 2800-8564 gokul.com Asia Pacific Equity Research 11 June 2013 Figure 14: Semiconductor manufacturing chain Semiconductor manufacturing chain Foundry OSAT – Packaging & Testing ODM/EMS /Brands IC Design Substrate Move to System in Package Printed Circuit Board (PCB) Source: J.hariharan@jpmorgan.P.

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