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amplificadores controlados por tenecion

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In this circuit, you will need an n-channel JFET which is to be operated as a voltage variable resistor. The lab has a supply of 2N5457 JFETs which can be used for the experiment.

In general, the JFET drain current is given by

iD = (vGS VT O )2

where is the transconductance parameter and VT O is the threshold voltage (which is negative). It will be necessary to know numerical values for and VT O for your JFET. This

information can be obtained from the curve tracer. Dr. Brewer can assist with this.

The object of this experiment is to assemble and test a voltage controlled amplifier (VCA)

that might be used as a variable gain stage in a compressor, a limiter, or a guitar eects box.

The variable gain element in the VCA is a JFET operated in its linear or triode region. The

basic circuit is shown in Figure 1. The drain-to-source voltage of the JFET is labeled vA in

the figure. It is given by

R2

vA = vI

R1 + R2

For op-amp circuits powered by 15 V power supplies, a practical upper limit on the

peak input voltage might be taken to be 10 V. For the JFET to be operated in its linear

region, its drain-to-source voltage should not exceed VT O , where VT O is its threshold voltage

(which is negative for the n-channel JFET). To be on the safe side, the limit might be taken

to be VT O /2. Thus, a design specification for the circuit is

|vA |max = 10

R2

|VT O |

R1 + R2

2

or

R1

20

1

R2

|VT O |

When the JFET is pinched o, i.e. when it is an infinite resistance, the circuit is to be

designed so that it has a voltage gain that is 5% to 10% greater than unity (in the range of

1.05 to 1.10). This requires

1.05

R3

1.10

R1 + R2

or

R3

R3

R1 + R2

1.1

1.05

When the JFET is operated in its linear region, it exhibits a resistance from its drain to

source. Let this be denoted by rds . The gain of the circuit is given by

vO

R3 rds kR2

=

vI

R2 R1 + rds kR2

Let the minimum value of rds be denoted by rds(min) . It is given by

rds(min) =

1

2 |VT O |

At this value, the circuit is to exhibit an attenuation that is 26 dB (a linear factor of 1/20)

lower than the gain when the JFET is pinched o. This condition requires

1

R3 rds(min) kR2

1 R3 R2

1

1

=

or

R1 =

R2 R1 + rds(min) kR2

20 R2 R1 + R2

19rds(min) R2

1

To solve for R1 and R2 , assume a standard 5% value for R3 . Calculate the two values of

R2 for which

1

1

1

R3

1

R3

1

1

+ R2 =

+ R2 =

and

19rds(min) R2

1.1

19rds(min) R2

1.05

Calculate the corresponding values of R1 . Repeat for several 5% standard values of R3 until

values for both R1 and R2 that are closest to standard 5% values are obtained.

Assemble the circuit using a TL071, TL081, or LF351 op amp. Use RA = RB = 10 k.

Apply a sine wave to the input and a negative dc voltage to vC . Verify that that gain of the

circuit can be varied between unity and 1/20 by varying vC over the range VT O vC 0.

Do not apply a dc voltage outside this range for the JFET could be damaged, and remember

that VT O is negative. If you have oscillation problems, put a small value capacitor (hopefully

no larger than 10 pF to 20 pF) in parallel with R3 .

Once the circuit is operational, apply a triangle wave having a peak voltage of 10 V to

vI . Connect the x input to the oscilloscope to vI and the y input to vO . You should observe

a straight line having some curvature on the oscilloscope whose slope at vI = 0 can be varied

approximately between 1 and 1/20 by varying vC . Note and record the curvature in this

line. This curvature adds undesired distortion to the signal which is to be eliminated in the

next step.

The next step is to linearize the circuit to remove the curvature by feeding the voltage

vA /2 back into the JFET gate. A suitable circuit is shown in Figure 2. The output voltage

of A2 must be negative to prevent the flow of gate current in the JFET. When this is the

case, the gate-to-source voltage of the JFET is given by

vGS = vA

R3 R6

R6

vC

R2 R5

R4

vGS =

vA

vC

2

2

With R5 chosen to be some convenient value (e.g. R5 = 10 k), calculate values for R4 and

R6 . Use R7 = 10 k. Note that there is no current through R7 when vGS < 0 so that this

resistor has no eect on vGS .

Figure 2: Circuit with the linearization voltage added to the JFET gate voltage.

Assemble the circuit in Figure 2 using the values calculated above. Note that vC must

be positive in this circuit because A2 inverts the control voltage. Perform the same tests as

for the circuit in Figure 2 and record the waveforms. In the following weeks, the VCA will

be used as the control element in a compressor circuit. You should neaten up the circuit

so that it occupies no more room on the electronic breadboard than is necessary. This is

because the circuits to be added will occupy more area than this part of the experiment.

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