You are on page 1of 139

CHAPTER I INTRODUCTION TO INDUCTANCE

The impact of inductance has been a critical issue in the printed circuit board (PCB) design for quite some time. Since a PCB has both nearly perfect dielectric and ground plane, resistive losses in conductors as well as dielectrics are reasonably ignored. The inductance and capacitance are the major concerns in terms of the on-board signal transmission. In addition, the dimension of a PCB is relatively large compared with the signal wavelength, especially in the radio-frequency (RF) and microwave regime. For example, a 1 GHz signal has a wavelength of 30 cm in free space while a typical PCB can easily have one of its dimensions larger than several inches. This means the board has to be treated as a distributed system where the transmission line theory instead of KCL and KVL applies. The significance of inductance includes increased transmission delay, signal reflection and ringing, inductive coupling, and digital switching noise due to AC voltage drop.

However, inductance has been largely ignored in an on-chip environment, where resistive together with capacitive effects are bigger concerns. In addition, the chip size is no larger than several millimeters, which is tiny enough compared with signal wavelengths. With the operating frequencies looming into the gigahertz range, inductance is quickly coming into play. On one hand, the parasitic inductance of on-chip interconnects

1

gives rise to signal delay and crosstalk between different signal paths. On the other hand, spiral inductors have been specifically designed and integrated onto a chip to achieve enhanced system integrity. Therefore there is a dramatically increased demand of IC designers for an accurate inductance model, both analytical and computational.

MAXWELL EQUATIONS Maxwell’s Equations are the complete set of laws for time-varying electromagnetic phenomena. The four physical terms that describe electromagnetic fields are the electric field

E

V / m, electric displacement D

C / m

2

, magnetic field B

T / m

2

, and magnetic

intensity H

A / m.

E

and B

are analogous in nature in that they both give the force

on a moving charge q given by,

F

qE v B

(1)

where v is the velocity of the charge. D and H are analogous because they are independent of material properties and correspond to the space free charge and current respectively. E and B are related to D and H through the electric and magnetic polarization of the media material,

D E 
D
E 

(2)

2

B H

(3)

where

F / mis the electric permittivity and

H / mis the magnetic permeability.

The first one of Maxwell Equations is derived from Faraday’s Law, which states that a time-varying magnetic field induces electric fields. The integral form of Faraday’s Law is

 E  d l
E
d l

l

 

  B  t S

B
 t
S

d s

(4)

where S

is an arbitrary surface and l is the edge of S

on which the magnetic field is

integrated. Although the integral of electric field along a closed loop has the unit of voltage, it is different from the voltage defined for static fields, which is equal to the potential difference between two points and is independent of the path connecting the two points. The loop integral of the electric field induced by the time-varying magnetic field is defined as the electromotive force (emf) of that loop,

emf

 E  d l (5) l
E 
d l (5)
l

Applying Stoke’s Theorem, the large-scale form of Faraday’s Law can be transferred to the differential form

 

E

 

B

 

t

(6)

The second one of Maxwell’s Equations is based on Ampere’s Law, which describes that both conducting currents and time-varying electric fields generate magnetic fields. The integral form of Ampere’s Law is

3

 H  d l
H
d l

l



S

  D J   t   
 D
J 
 t
  

d s

(7)

where S

is an arbitrary surface and l is the edge of S . Applying Stoke’s Theorem, the

differential form of Ampere’s Law is

 D   H  J 
 D
 
H
J

t

(8)

The time derivative of the electric displacement has the same unit as current density that is so-called displacement current. The third one of Maxwell’s Equations is based on Gauss’s Law, which states that

the total flux of electric displacement D

from an arbitrary volume V

is equal to the net

charge enclosed in that volume. The integral form of Gauss’s Law is



D

S

d s



dv

V

(9)

where S

is the enclosed surface of volume V

and is the charge density. Applying

the divergence theorem, the differential form of Gauss’s Law is

  D

(10)

The fourth one of Maxwell’s Equations is validated from the fact that there is no magnetic charge existing in nature. Thus the magnetic field lines are always closed and the net flux of magnetic fields through any closed surface is always zero,

4



B

S

d s

0

(11)

  B 0

(12)

Writing the four equations together, the Maxwell’s Equations are

 B   E    t  D   H  J
 B
 
E
 
 t
 D
 
H
J
 t
 
D
 
B
 0

(13)

In order to solve Maxwell’s Equations as a set of differential equations, proper boundary conditions need to be applied to get unique solutions. At the surface of two different media, the tangential electrical field and normal magnetic field are continuous

E

t1

E

t 2

(14)

B

n1

B

n 2

(15)

The difference between the normal electrical displacements is equal to the surface charge density

D

n

1

D

n

2

s

C / m

2

(16)

The difference between the tangential magnetic intensity is equal to the surface current density

5

H

t

1

H

t

2

J

s

A/ m

2

(17)

For perfect dielectrics, there are no surface charges or currents, thus

D

n1

D

n 2

(18)

H

t1

H

t 2

(19)

For perfect conductors under DC conditions, there are no electric field inside the conductor because the internal electric field built up by the surface charges cancels the external electric fields and therefore the net electric field is zero

E t
E
t

0

(20)

If the magnetic field is static without varying with time, it will penetrate the perfect conductor. For most conductors, the relative permeability is close to one. For perfect conductors under AC conditions, both the electric and the magnetic fields inside the conductor are zero

E

t

0

(21)

B

n

0

(22)

INDUCTANCE DEFINITION Inductance can be defined in several ways that are inherently consistent.

6

From the energy point of view, the inductance of a device describes the magnetic energy storage capability of the device. The time-average energy stored in the magnetic field is given by

W

m

Re

1

4



V

H

B

dv

  • 1 LII

*

  • 4 (23)

where I

is the current flowing through the device. Thus the energy definition of

inductance is given by

L

Re



V

H

B

dv

  • II

(24)

Although the energy definition is the most fundamental definition of inductance, a more popular definition of inductance is through the magnetic flux leakage that is given by

L

I

(25)

where is the magnetic flux expressed as

 



H

S

d s

(26)

It is seen that the energy and flux definition are linked by the magnetic field.

Therefore the inductance of a device can be calculated from computing the H pattern associated with the device. From Faraday’s Law, voltage is linked to the magnetic flux by

field

7

V



 

t

(27)

By substituting Equation (27) into Equation (25), the AC voltage drop across a device is proportional to the time derivative of the current

  • V L

    • dI (28)

dt

This is commonly used in the circuit theory and the directions of V in Figure 1

and I

are defined

+

V

-

+ V - I
+ V - I
 

I

Figure 1 – Voltage and Current Direction in Inductance Definition

The inductance definition gives insight of the impact of inductance on an electric network:

  • 1. Current flowing through a conductor creates a magnetic field;

  • 2. A time-varying current generates a time-varying magnetic field, which induces electric fields;

  • 3. The induced electric field exerts forces on the electrons in the conductor carrying the current and causes emf.

8

The induced electric field from a conductor can affect not only the electron movement of the conductor itself, but also another conductor nearby. This leads to the separation of inductance definition into self-inductance and mutual inductance. The self-inductance of a conductor describes the effects of the electromagnetic field generated by the conductor on itself. For a real conductor instead of an ideally filamentary one, it is convenient to further separate the definition of self-inductance into internal self-inductance and external self-inductance. The external one is due to the magnetic flux leakage from the inductor to the external surrounding. The internal one arises from the magnetic energy stored inside the conductor. The overall classification of inductance is summarized in Figure 2.

Inductance Self Mutual Internal External
Inductance
Self
Mutual
Internal
External

Figure 2 – Inductance Classification

9

INTERNAL SELF-INDUCTANCE When applying the flux leakage definition to the internal of the conductor, the inconvenience arises from the difficulty of distinguishing the flux area, especially. To gain better understanding of internal inductance, the magnetic energy definition of inductance is used. When a conductor carries a current, magnetic field is generated both inside and outside the conductor. Thus some of the magnetic energy is stored inside the conductor, which gives rise to the internal inductance. For those conductors that are not filamentary, the internal inductance exists. For example, the internal inductance of an infinitely long straight thick wire exists while the external one does not. Although one can try to solve the field pattern inside a given conductor to calculate the energy and thus internal inductance, a more efficient way to solve the problem is by using the definition of internal impedance per unit length, which is given by [2]

Z

i

/

m

E

z 0

(29)
I

where

E

z 0

is the electric field on the conductor surface and I

is the total current

flowing through the conductor.

The question is what

E

z 0

is for a given

I

?

10

From Ohm’s Law, electric field is directly related to the conducting current and material conductivity

J E

(30)

Thus the internal impedance of a conductor per unit length is

Z

  • i

J

z 0



J da

z

a

(31)

where the current I

is replaced by the integration of the current density over the

conductor cross-section. Since the conductivity of a practical conductor cannot be infinite, the internal impedance of a conductor includes not only internal inductance, but also internal

resistance. In another word, the real part of

Z

  • i represents internal resistance and the

imaginary part of

Z

corresponds to internal inductance as shown in Figure 3. i R L i i Z 
corresponds to internal inductance as shown in Figure 3.
i
R
L
i
i
Z
 R  jL
i
i
i

Figure 3 – Internal Impedance including Resistance and Inductance

The current distribution on the conductor cross-section is not uniform as long as the current varies with time. This non-uniform distribution is due to the skin effect,

11

which is a frequency dependent phenomenon. As illustrated in Figure 4, the skin effect can be explained physically combining Faraday’s Law and Ampere’s Law.

J  E  B  E    t  D  H 
J  E
 B

E
 
 t
 D

H
J

t

Figure 4 – Physical Explanation of Skin Effect

The conducting current J

generates magnetic field that is given by Ampere’s

Law

  H

J

(32)

A time varying J Faraday’s Law

results in a time varying H

that induces an electric field given by

12

 

E

 

B

 

t

(33)

The induced electric field causes a displacement current that in turn adds to the magnetic fields

 D   H  J 
 D
 
H
J

t

(34)

It is evident from Figure 4 that the induced electric field points to the direction that tends to cancel the conducting electric fields at the center of the conductor and reinforce it at the surface. From Ohm’s Law, therefore, the current will crowd at the conductor surface and void at the center. The skin effect becomes more significant at increased frequencies. From the carrier transportation point of view, the current density can be written as

J

qn v

(35)

where q is the electron charge magnitude, n is the carrier density, and v

is the carrier

velocity. For good conductors like metals, the non-uniform distribution of current density as a result of skin effect is mainly due to the non-uniform distribution of the carrier

velocity rather than the carrier density. This is because the conductivity of metals is so large that it is a good approximation that the electron density is uniform throughout the conductor. Thus skin effect in good conductors can also be viewed as the non-uniform distribution of the electron velocity, which is higher at the conductor surface than the center.

13

The extreme case will be a superconductive conductor, whose conductivity is infinity. All the current will flow at the surface of the conductor. There will be only surface current and no body current. Since the carrier density is assumed to be uniform, there will be no normal electric fields perpendicular to the conductor surface, but only tangential ones along the current path. Choosing the tangential direction to be zˆ , the electric field can be expressed as

E

zE ˆ x

z

,

y

(36)

The non-uniform distribution of the electric field can be solved through Maxwell’s Equations. The first and second equations are rewritten below

 B   E   (6)  t  D   H 
 B
 
E
(6)
 t
 D
 
H
J
(8)
 t
By taking curl on both sides, Equation (6) becomes
B 
 
 
E
 
 
 t

(37)

Substitute Equation (8) into Equation (37),

  

E

 

2

E

 

t

 



E



E

t

 

From Gauss’s Law,

(38)

14

   E 
  E 

(39)

The first term in Equation (38) can be expressed as

  

E



 

   
 

xˆ

y

y ˆ

y

ˆ

z

z

     

(40)

For most of the practical conductors, it is a good assumption that there is no gradient of

both the charge density and the material permittivity . be simplified as

Therefore Equation (38) can

2

  E E   E    t  t   
 E
E

E 

 t
 t
   
   

(41)

The phasor form of this equation becomes a complex Helmholtz equation

2

E

j

  E

2

(42)

This is a partial differential equation and its solution depends on the boundary conditions. A useful parameter called skin depth is defined to describe quantitatively the skin effect, which is defined as

2 
2


(43)

where is the angular frequency of the fields and is the conductor conductivity. The skin depth is derived as the depth at which the magnetic field can penetrate a conductor. It is also consistent with the depth beneath the surface of a conductor at which the current mainly flows.

15

EXTERNAL SELF-INDUCTANCE A current flowing through a conductor generates magnetic field in its surroundings, which gives rise to the external inductance of the conductor. In order to calculate the external inductance using the flux definition, a finite flux area has to be properly defined. Since a current always flows through a closed path, the surface area can then be chosen as enclosed by the current loop that is illustrated in Figure 5.

I 
I

Figure 5 – Surface Area Enclosed by Current Loop

Therefore the rigorous definition of external inductance is referred to the inductance of a conductor loop. The physical explanation gives further insight of the loop inductance concept. Consider a current loop as shown in Figure 6.

16

 H  J I  B  E  
 H  J
I
 B

E
 

t Figure 6 – Physical Explanation of Loop Inductance

The loop can be differentiated into many infinitesimal current elements. Each

current segment generates circular H

lines surround itself given by

 

  H

J

(32)

Under the time-varying condition, the induced E

field is given by

 

E

 

B

(33)

 

t

The induced electric field tends to point to the direction of opposing the change of the

conducting current. As shown in Figure 6, if the current I electric field points to the opposite direction of I .

increases, the induced

It is seen that the

E

lines are closed, corresponding to the electromotive force

(emf).

For most of the cases in integrated circuits, the circuit operating frequency is so

17

low that the displacement current is much smaller than the conducting current and therefore can be ignored. The loop concept of the external inductance can be further illustrated by considering a straight wire with infinite length. Since the wire by itself does not construct a complete loop, there is no external inductance associated with the infinitely long wire. The inductance of a filamentary conductor is given by

L



B

S

d s

I

(44)

where S

is the flux area bounded by the conductor. In reality, however, a conductor will

have an arbitrary cross-section. The concept of average flux [12] is used to account for the conductor cross-section. The average flux is defined as

1    a a
1

a
a

da

(45)

where a is the area of the conductor cross-section as illustrated in Figure 7.

18

a
a

Figure 7 – Area of Conductor Cross-Section

As shown in Figure 8, the average flux can be understood by replacing the thick conductor loop with a filamentary loop that is located somewhere in between the inner and outer edges of the thick conductor. The average flux area of the thick conductor equals the area bounded by the filamentary loop.



Figure 8 – Illustration of Average Flux

After properly defining the loop, it is necessary to solve the H

fields. Ampere’s

Law states that the static magnetic field generated by a small current element in an

unbounded, homogeneous, and isotropic media is

19

d H r

  I r ' d l  R 3 4  R
I
r '
d l
R
3
4
R

(46)

where the vectors are illustrated in Figure 9.

z d H r r R  Ir' dl r' y 0
z
d H r
r
R
Ir' dl
r'
y
0

Figure 9 – Coordinates for Calculating the Magnetic Field from a Current Element

By summing all the magnetic field generated by all the current elements, the total magnetic field generated by a complete filamentary current loop is

H

r

  I r '  d l  R 3 4  R l
I
r '
d l
R
3
4
R
l

(47)

where l is the current path. The average flux of the current loop with arbitrary conductor cross-section is



a



H

S

d s

da

(48)

And the external self-inductance of a current loop is give by

20

  • L e

  • (49)

I

I

For low frequencies, the current distribution on the conductor cross-section can be

approximated to be uniform. Therefore Equation (49) can be simplified to

  1     L        d
1
L
 
d l
R
d s
da
(50)
e
3
I
a
4
R
a
 
S
l
 

MUTUAL INDUCTANCE

Mutual inductance describes the magnetic coupling between two conductors. It

refers to the interference between either two current loops or two segments on the same

current loop. Similar to the external self-inductance definition, mutual inductance can

also be explained by Faraday’s and Ampere’s Law. Figure 10 shows two coupled current

loops that are labeled as i and

j .

Loop

j carries a conducting current and generates

magnetic fields in the space. Some of the H

lines generated by

j

may cut loop i

and

generate electromotive forces (emf) on i . The emf either enhances or impedes the

current flow on loop i .

21

  H  J ij j  B I ij   E  
  H
 J
ij
j
 B
I
ij
 
E
 
j
I
ij
 t
i

Figure 10 – Physical Explanation of Mutual Inductance between Current Loops

Mutual inductance defined by the magnetic flux leakage is given by

L

ij

ij

I

j

(51)

The mutual flux

ij

between i and

j

is

ij



H

ij

S

i

d s

(52)

where S

is the surface bounded by loop i . This expression is derived from two loops.

It, however, does not seem to apply to the mutual inductance between conductor

segments for the difficulty of defining the flux area. To solve this problem, the vector

magnetic potential is used instead of the magnetic flux to calculate the mutual inductance,

which avoids the use of flux area.

The magnetic vector potential is defined as

22

B

   A

(53)

From Ampere’s Law, the magnetic field generated by a conducting current is

H

r

  • (47)

Combining Equation (53) and (47), vector magnetic potential generated by a current loop

is

A r

l

I

r

'

d l

4

R

(54)

By replacing the current with current density, A can be expressed as

 

'

A r



V

J

4

r

R

dv

(55)

where V

is the volume of the conductor.

The magnetic flux can be expressed by A , applying Stoke’s theorem

 

 A  d l
A
d l

(56)
l

Thus the average mutual flux between two conductor loops is

or

ij

1

a

i



a

i

i

A j
A
j

d l da

i

i

(57)

23

ij

1

4

a

i

   

a

i

i

a

j

j

J

j

d l

i

d l

j

R

ij

da da

i

j

(58)

where

a

i

and

a

j

are the cross section area of loop i and

j respectively as illustrated

in Figure 11,

dl

i

and

d l

j

are the infinitesimal segments of loop i and

j respectively,

and

R

ij

is the distance vector from

d l

i

to

d l

j

as shown in Figure 12.

i a i
i
a
i
j a j
j
a
j

Figure 11 – Illustration of Conductor Cross-Sections

24

dl i i R ij dl j j
dl
i
i
R
ij
dl
j
j

Figure 12 – Coordinate Illustration to Calculate Mutual Inductance between Conductor

Loops

The mutual inductance between two conductor loops is

L

m ij

,

1

J

j

d l

i

d l

j

    

4

a

i

a

i

i

a

j

j

R

ij

da da

i

j

J

j

da

j

a

j

(59)

This equation is the general form of mutual inductance computation by taking into

account the non-uniform distribution of the current density in the conductor. The dot

product in this equation implies that the mutual inductance between two orthogonal loops

is zero. The mutual inductance is positive when the currents in the two loops flow in the

same direction, and vice versa.

25

Although this equation is derived from conductor loops, it can be easily modified

for conductor segments by applying the virtual loop concept [12]. Consider two straight

conductor segments, not necessarily coplanar, as shown in Figure 13.

c j j c i i' b j i b i'' i
c
j
j
c
i
i'
b
j
i
b
i''
i

Infinity

Figure 13 – Virtual Loops of Conductor Segments

The virtual loop is defined for segment i by adding two straight edges i ' and i' ' that

are perpendicular to segment

j and extend to infinity. The virtual loop is closed at

infinity. Thus the mutual inductance between segment

j and the virtual loop is the

summation of the mutual inductance between segment

j and the four segments of the

virtual loop

L

m vl

,

i

_

j

L

m ij

,

L

m i

,

'

j

L

m i

,

''

j

L

m

,

j

(60)

L

m

,

i

'

j

and

L

m

,

i

''

j

are both zeros

because i '

and i' ' are orthogonal to

j .

L

m

j

,

is

also zero because of the infinite distance from

j to infinity. Therefore

26

L

m

,

vl

_

j

L

m ij

,

(61)

In this way, Equation (59) can be modified to calculate the mutual inductance between

two conductor segments

L

m

,

ij

1

4

a

i

a

i

 

c

i

b

i

a

j

c

j

b

j

J

j

d l

i

d l

j

R

ij

da da

i

j

J da

j

j

a

j

where

b i
b
i

and

b j
b
j

donate the starting points of segment i and

j respectively,

c

i

and

c

j

represent the ending points on segment i and

j .

THESIS OVERVIEW

In this chapter, the concept of inductance has been explained in detail. Three

inherently consistent definitions of inductance are given in different aspects: magnetic

energy storage, magnetic flux leakage, and voltage-current relationship. The

classification of inductance provides a more insightful understanding of the inductive

mechanism, including internal self-inductance, external self-inductance, and mutual

inductance.

Starting with Maxwell’s Equations, analytical expressions are derived for the

three kinds of inductance, which serve as the guidelines for inductance calculation of

specific cases.

27

The internal self-inductance is caused by the skin effect, which is calculated by

solving the complex Helmholtz equation. The external self-impedance can be computed

by using the flux leakage definition. The mutual inductance is modeled by introducing

the magnetic vector potential to revise the flux definition. It changes the surface integral

of the magnetic field into the loop integral of the magnetic vector potential to calculate

flux. In this way, one can develop the partial mutual inductance idea to compute the

mutual inductance between two conductor segments instead of conductor loops.

In the next chapters, the inductance classification and analytical model are applied

to an on-chip environment to characterize interconnects and integrated inductors. The

analytical model is revised to include the semiconductor substrate losses and the skin

effect. And the computer simulation gives numerical solutions of the analytical model

applied to on-chip interconnects and inductors.

28

CHAPTER II CHARACTERIZATIONS OF ON-CHIP INTERCONNECTS

As the integrated circuit evolves towards faster operating speed and higher level

of system integration, the on-chip interconnection network becomes more complicated.

On-chip interconnects are carrying signals with higher frequencies and extending into

larger dimensions. There is a growing demand of high-frequency circuit designers to

accurately characterize on-chip interconnects. A distributed equivalent circuit model has

been used to model on-chip interconnects in terms of distributed impedance and

admittance of the interconnect. The line inductance and resistance are closely related to

the signal delay and attenuation. An on-chip interconnect defers from an ideal microstrip

line because of the presence of the lossy semiconductor substrate. High frequency effects

such as the skin effect should also be considered to model the interconnect.

INTERNAL SELF-IMPEDANCE OF ON-CHIP INTERCONNECTS

From the discussion of the internal self-inductance in Chapter I, the internal

impedance of an on-chip interconnect per unit length is given by

29

Z

i

J

z 0



J da

z

a

(31)

where

J

z

is the current density on the interconnect cross-section,

J

z 0

is the current

density at the interconnect surface, and is the interconnect conductivity.

The current distribution on the interconnect cross-section is given by solving the

complex Helmholtz equation

2

E

j

  E

2

(42)

The shape of the interconnect cross-section can be approximated to be

rectangular. Applying the rectangular coordinates as shown in Figure 14 where zˆ is the

direction of the current path,

y x 0 W W  2 2 z
y
x
0
W
W
2
2
z

Figure 14 – Coordinates Illustration to Calculate Skin Effect of On-Chip Interconnects

Equation (42) can be separated as

30

2

E

x

j

  E

x

2

(62)

2

E

y

j

  E

y

2

(63)

2

E

z

j

  E

z

2

(64)

For good conductors, the normal electric fields

E

x

and

E y
E
y

are negligible compared

with

E

z

. The propagation form of

E

z

can be written as

E

z

E

'

z

x

,

y e

jk z

z

t

(65)

'

where E

z

x

,

y

gives the current distribution on the conductor cross-section.

Substituting Equation (65) into (64) gives

'

E

z

x

2

'

E

z

y

2

j



2

 

2

k

z

'

E

z

(66)

This a two dimensional problem.

For on-chip interconnects, the thickness of different metal layers is listed in Appendix II

in terms of various CMOS processes [37]. It is seen that the thickness of the metal

interconnects ranges roughly from 0.5 m to 1 m .

Taking the 0.25 m Aluminum process as an example, the skin depths of different

metal layers versus frequency are compared in Figure 15. It is seen that in the typical

radio-frequency range from 1GHz to 10GHz, the skin depth varies around several

microns. Since higher metal layers have better conductivity, they have smaller skin depth

than lower layers.

31

3.5 Metal 1, 2 Metal 3, 4 Metal 5 3 2.5 2 1.5 1 0.5 1
3.5
Metal 1, 2
Metal 3, 4
Metal 5
3
2.5
2
1.5
1
0.5
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
Skin Depth,  m

Figure 15 – Skin Depth of Different Metal Layers in TSMC 0.25 m Process

The nonuniform of current distribution on a conductor cross-section has to be

considered when the dimension of the conductor cross-section is comparable to twice the

skin depth at specified frequencies [13].

It is evidence from Appendix II and Figure 15 that when the operating frequency

is below 10GHz, twice the skin depth is larger than the thickness of the corresponding

metal layers. Thus the skin effect can be neglected on the thickness dimension of on-chip

interconnects by assuming there is no current density variation. And the skin effect is

only considered on the width dimension. This leads to the one dimensional

approximation of Equation (66), which for on-chip interconnects can be written as

32

where

E

z

x

x

2

k

2

E

z

x

0

(67)

k

2

  j



2

 

The homogeneous solution of Equation (67) can be written as

E z
E
z

x

A

cos

kx

B

sin

kx

(68)

By choosing the coordinates to have the origin located at the center of the conductor as

illustrated in Figure 14, E

z

x

becomes an even function in terms of x

E x

z

A

cos

kx

(69)

where A is a constant.

If the current density at the interconnect edge is assumed to be unity, the

normalized current density is given by

J

x

cos kx

J

z 0

cos   

k

W  

2

where W

is the width of the interconnect.

(70)

Since k

is a complex number, both the electric field and the current density

inside the interconnect are also complex. This means the current flow on the interconnect

cross-section will have a spatial dependent phase. As an example, the current density on

the cross-section of a 4 m wide interconnect is plotted in Figure 16. The interconnect is

on the Metal 5 layer in a 0.25 m CMOS process.

33

f=1GHz 1.2 f=5GHz f=10GHz 1 0.8 0.6 0.4 0.2 0 -0.2 -2 -1.5 -1 -0.5 0
f=1GHz
1.2
f=5GHz
f=10GHz
1
0.8
0.6
0.4
0.2
0
-0.2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x, m
Re(J z /J z0 )

(a) Real Part of the Current Density

0.6 f=1GHz f=5GHz f=10GHz 0.5 0.4 0.3 0.2 0.1 0 -0.1 -2 -1.5 -1 -0.5 0
0.6
f=1GHz
f=5GHz
f=10GHz
0.5
0.4
0.3
0.2
0.1
0
-0.1
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
x, m
Im(J z /J z0 )

(b) Imaginary Part of the Current Density

34

f=1GHz f=5GHz 1.2 f=10GHz 1 0.8 0.6 0.4 0.2 -2 -1.5 -1 -0.5 0 0.5 1
f=1GHz
f=5GHz
1.2
f=10GHz
1
0.8
0.6
0.4
0.2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
|J z /J z0 |

x, m

(c) Magnitude of the Current Density

Figure 16 – Current Density on the Interconnect Cross-Section at Different Frequencies

It is evidence from Figure 16 that the skin effect becomes more significant at

increased frequencies. At 1GHz, the magnitude of the current density in the middle of

the interconnect is about 90% of that at the edge. However, when the frequency goes up

to 10GHz, nearly all the current crowds to the edge of the interconnect.

As seen from Figure 16 (a), the real part of the current density remains positive

below 5GHz. However, as the frequency increases, the real part of the current density

becomes negative in the middle of the interconnect. Since the plotted current density is

normalized to the surface one, it means the current in the middle begins to flow in the

35

opposite direction as to the surface current at increased frequencies. Such phase

difference is due to the increased displacement current at high frequencies.

The internal impedance of an on-chip interconnect per unit length can be

calculated by taking Equation (70) into (31), which gives

or

Z

i

cos   

W

k

W  

2

J

z 0



J da

z

a

2

W

cos kx dx

2

(71)

Z i

k

2

tan   kW  

2

(72)

Again, taking as an example the interconnect on the Metal 5 layer in a 0.25 m

CMOS process, the internal inductance and resistance per unit length versus frequency

with different line widths are plotted in Figure 17.

36

-13 x 10 4.5 W=1 W=2 W=4 4 3.5 3 2.5 2 1.5 1 1 2
-13
x 10
4.5
W=1
W=2
W=4
4
3.5
3
2.5
2
1.5
1
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
9
x
10
Internal Resistance, H/m

(a) Internal Inductance of the Interconnect

0.03 0.025 0.02 0.015 0.01 W=1 W=2 W=4 0.005 1 2 3 4 5 6 7
0.03
0.025
0.02
0.015
0.01
W=1
W=2
W=4
0.005
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
9
x
10
Internal Resistance,  /m

(b) Internal Resistance of the Interconnect

Figure 17 – Interconnect Internal Impedance per unit length versus Frequency

37

It is evident from Figure 17 (b) that the interconnect internal resistance increases

with the frequency. This is because at higher frequencies more current crowds at the

interconnect edges and thus less area of the interconnect cross-section contributes to the

current conduction, which leads to the increase of the internal resistance. At low

frequencies, the current distribution on the interconnect cross-section is close to uniform

and thus wider interconnects have smaller internal resistance. However, at high

frequencies, the current distribution is dominated by the skin effects and the interconnect

width tends to have less effects on the internal resistance.

It is seen from Figure 17 (a) that the interconnect internal inductance decreases

with the frequency. This is mainly because at higher frequencies, the total current carried

by the interconnect decreases for an increased internal resistance. This results in less

magnetic energy stored inside the interconnect and thus less internal inductance.

Wider interconnects have more internal inductance and less internal resistance

than narrower interconnects. This is because wider interconnects have bigger area of

cross­section and thus more internal volume to store magnetic energy and conduct

current. However, at higher frequencies, the interconnect width shows less effects on the

internal impedance. This is mainly due to the skin effect that at high frequencies all

current flow on the interconnect edges and the width do not really matter.

The internal impedance of interconnects with less width shows less frequency­

dependence in that the skin effect is less important than in the wider interconnects.

38

ON-CHIP MICROSTRIP SYSTEM

As shown in Figure 18, an on-chip interconnect is a planar metal or poly trace on

a silicon substrate with a silicon dioxide layer in between as the dielectric insulator.

Sometimes, there is also a metal plate beneath the silicon substrate, which is either the

back metallization of the silicon wafer or the IC package that contains the silicon die.

Insulator Semiconductor Substrate Metal Plate Metal
Insulator
Semiconductor Substrate
Metal Plate
Metal

Figure 18 – On-Chip Interconnects

The characterizations of an on-chip interconnect are determined by not only the

properties of metal (or poly) traces, but the whole metal-insulator-substrate-metal system.

Such system can be classified as a microstrip system. The metal (or poly) trace is the

signal path and the silicon substrate together with the metal plate behaves like the signal

return path.

39

When there is a current flow in the metal trace, the same amount of current will

flows in the return path but in the opposite direction. Only in this way can a signal

transmit (or propagate). If the silicon substrate is a perfect dielectric without a

conductive plane beneath it, there will be no return path for the current and the signal will

not transmit or propagate along the metal trace.

The distribution of the return current is strongly dependent on the frequency. At

low frequencies as shown in Figure 19, the skin depth of the substrate is much larger than

the substrate thickness. The magnetic field generated by the signal current will penetrate

both the insulator and the substrate. It will be terminated at the surface of the metal plate.

By assuming that the metal plate has perfect conductivity, there is no magnetic field

inside the metal plate. The return current mainly flows on the surface of the metal plate

given by

J

s

H

t

(73)

At high frequencies as shown in Figure 20, the magnetic field generated by the

signal induces eddy current in the substrate, which shields the magnetic field penetration.

Therefore some of the magnetic fields will not penetrate the substrate and will be

terminated in the bulk of the substrate.

40

I  I I
I
 I
I

Figure 19 – Return Current Distribution of On-Chip Interconnects at Low Frequencies

 I
 I

Figure 20 – Return Current Distribution of On-Chip Interconnects at High Frequencies

41

The depth at which the magnetic field can penetrate the substrate depends on the

substrate properties and the frequency, which is given by the skin depth

2 
2


(43)

It is seen from Equation (43) that the higher frequency and the higher substrate

conductivity, the less the skin depth. This implies that more magnetic fields will be

terminated in the substrate and therefore more return current flows in the substrate. If the

frequency and the substrate conductivity are so high that the skin depth of the substrate is

smaller than the substrate thickness, the majority of the return current will flow in the

substrate instead of the metal plate. In this condition, the signal propagation on the

interconnect will not be in quasi-TEM model any more, but in a so-called slow mode

[14].

EXTERNAL SELF-IMPEDANCE OF ON-CHIP INTERCONNECTS

For an ideal microstrip system with perfect dielectrics and ground planes, the line

will be lossless. However, for an on-chip interconnect with a semi-conductive

semiconductor substrate, there will be both external self-inductance and self-resistance.

The external self-inductance arises from the magnetic flux leakage from microstrip line.

The external self-resistance is a result of the low conductivity of the substrate.

42

In order to calculate the external self-impedance of an on-chip chip interconnect,

one needs to solve the field pattern associated with the system, which requires the

solution of the current distribution. However, the distribution of the return current in the

substrate and the metal plate is complicated that requires solving Maxwell’s Equations. A

more time-efficient way of solving the problem is the magnetic image approach.

First, consider an ideal microstrip system consists of a perfectly conductive

microstrip line and an infinite large ground plane with perfect conductivity as shown in

Figure 21.

I    Perfect Ground Plane
I
  
Perfect
Ground Plane

I

Figure 21 – Image Theory in Ideal Microstrip System

The magnetic field generated by the signal current is terminated at the surface of the

perfect ground plane and extends to infinity above the ground plane. The boundary

conditions on the surface of the ground plane are given by

E t
E
t

0

(21)

43

D

n

s

B

n

0

H

t

J

s

(74)

(22)

(75)

The total magnetic field generated by this microstrip system above the ideal ground plane

is contributed by both the signal current I

and the surface current on the ground plane.

The boundary conditions can be satisfied by replacing the whole ground plane

with an image current, which mirrors the signal current on the other side of the ground

plane. The image carries the same amount of current as the signal but points in the

opposite direction, as shown in Figure 21. In this way, the contribution of the return

current to the total magnetic field equals that of the image current. By taking the

magnetic image approach, one can solve the field pattern associated with an ideal

microstrip system by simply summing the magnetic fields generated by the signal current

and its image.

There are closed-form expressions available to calculate the external self-

inductance of an ideal microstrip system [1]. For an ideal microstrip line as shown in

Figure 22, its external self-inductance is given by [17]

44

w    h Perfect Ground Plane
w
  
h
Perfect
Ground Plane

L es

Figure 22 – Ideal Microstrip Line  2  2      h
Figure 22 – Ideal Microstrip Line
2
2
 
h 
w 
ln
1
32
1
1
 
4
w
8
h
 

(76)

where w is the width of the microstrip line and h is the vertical distance between the

microstrip line and the ground plane.

However, Equations (76) cannot accurately model an on-chip interconnect mainly

because of the lossy semiconductor substrate. In order to account for the lossy

semiconductor substrate, the complex image method [16] is used.

The complex image method is similar to the magnetic image approach for the

ideal microstrip system. The difference is that for the complex image method, the

vertical distance between the signal current and its image is complex. This is due to the

lossy nature of the substrate.

The discussion of the complex image method can be divided into two conditions

[15]:

45

  • 1. The skin depth of the substrate is much smaller than the substrate thickness and the signal propagates in the skin mode;

  • 2. The skin depth of the substrate is larger than the substrate thickness and the signal propagates in the quasi-TEM mode. First, when the skin depth of the substrate is much smaller than the substrate

thickness, the majority of the return current flows near the surface of the substrate instead

of the metal plate. As illustrated in Figure 23, all the return current in the substrate can be

replace by an image current.

Signal Current h Insulator ox  D h sub Substrate Image Current Metal Plate
Signal Current
h
Insulator
ox
D
h
sub
Substrate
Image Current
Metal Plate

Figure 23 – Illustration of Complex Image Method when the Skin Depth of the Substrate

is Much Smaller than the Substrate Thickness

The vertical distance between the signal current and its image is given by solving the

Green’s Function [15]

46

D

2

h

ox

1

j

(77)

where

h

ox

rewritten as

is the oxide thickness and is the skin depth of the lossy substrate

2 
2


(43)

Here is the substrate permeability and is the substrate conductivity. The magnetic

permeability of silicon is very close to that of free space, which equals

4

10

7

H/m.

The conductivity of the silicon substrate is directly related to the doping level [5].

It is worth clarifying that a complex distance does not have a physical

representation, rather a computational convenience [16].

Second, when the skin depth of the substrate is much larger than the substrate

thickness, the return current will flow inside the metal plate as well as the substrate. As

illustrated in Figure 24, the return current in the metal plate as well as the substrate can be

replaced by an image current.

47

Signal Current h Insulator ox h sub Substrate D  Metal Plate Image Current
Signal Current
h
Insulator
ox
h
sub
Substrate
D
Metal Plate
Image Current

Figure 24 – Illustration of Complex Image Method when the Skin Depth of the Substrate

is Much Smaller than the Substrate Thickness

The vertical distance between the signal current and its image is given by [15]

D

2

h

ox

1

j

 

tanh

 

1 j h

sub

 

(78)

where

h

ox

is the oxide thickness,

h

sub

the thickness of the substrate, and is the

skin depth of the lossy substrate.

By taking the complex image approach, the external self-impedance of an on-chip

interconnect as shown in Figure 18 equals the external inductance of an ideal microstrip

line as shown in Figure 22, where the vertical distance between the microstrip line and

the ideal ground plane is given by

48

h

D

2

(79)

There are two expressions for D as given by Equation (77) and (78), depending on the

relationship between the substrate thickness and the substrate skin depth.

The skin depth of a silicon substrate with different doping level is plotted in

Figure 25.

2000 ­3 Na=10 16 cm ­3 1800 Na=10 17 cm Na=10 18 cm ­3 1600 1400
2000
­3
Na=10 16 cm
­3
1800
Na=10 17 cm
Na=10 18 cm
­3
1600
1400
1200
1000
800
600
400
200
0
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
Skin Depth,  m

Figure 25 – Skin Depth of Silicon Substrate at Different Doping Levels versus Frequency

Recall the external self-inductance of an ideal microstrip line is given by

L es

4

ln

1

32

2  2  h    w     1  1
2
2
h 
w 
1
1
 
w
8
h

 

 

(76)

49

Applying Equation (76) for on-chip interconnects by applying the complex image

method, h becomes a complex number that gives a complex inductance. By examining

the flux definition of the external self-inductance, a complex inductance can by explained

by a complex flux given by [15]

     
  

L

R

j

  I  
 I

(80)

where the

L

R

j

term appears as the complex inductance.

What physically gives rise to the external self-resistance? The answer is the lossy

substrate. Since the silicon substrate serves as part of the current return path with a poor

conductivity (about ten thousand times smaller than the conductivity of metal), the return

current in the substrate suffers from resistive losses and therefore limits the signal

current.

Figure 26 plots the self inductance and resistance of an on-chip interconnect on

the Metal 5 layer in a 0.25 m CMOS process.

50

13 12.5 12 11.5 11 10.5 ­3 Na=10 15 cm Na=10 16 cm Na=10 17 cm
13
12.5
12
11.5
11
10.5
­3
Na=10 15 cm
Na=10 16 cm
Na=10 17 cm
­3
­3
10
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
External Self­Inductance, nH/cm

(a) External Self-Inductance of an On-Chip Interconnect

100 15 -3 Na=10 cm 16 -3 Na=10 cm 90 17 -3 Na=10 cm 80 70
100
15
-3
Na=10
cm
16
-3
Na=10
cm
90
17
-3
Na=10
cm
80
70
60
50
40
30
20
10
0
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
External Self­Resistance,  /cm

(b) External Self-Resistance of an On-Chip Interconnect

Figure 26 – External Self-Impedance of an On-Chip Interconnect [Equation (76)]

51

The thickness of silicon substrate is 250 m [36]. The oxide thickness between the metal

strip and the substrate is about 4 m. The width of the interconnect is taken to be 4 m.

The result agrees with the full-wave solution given by ADS Momentum [15].

It is seen from Figure 26 that the substrate conductivity will greatly affect the

external self-impedance of on-chip interconnects. Figure 26 (a) shows that external self-

inductance decreases with increased substrate conductivity. This is because a higher

conductive substrate has a smaller skin depth. Therefore fewer magnetic fields can

penetrate the substrate and more return current is induced inside the substrate. This

implies more return current will flow in the substrate instead of the metal ground plane.

The external self-inductance is proportional to the flux area bounded by the signal current

and the return current. The largest flux area and external self-inductance is achieved if all

return current flows in the metal ground plane as shown in Figure 19. However, if more

return current flows in the substrate as shown in Figure 20, the average vertical distance

between the signal current and the total return current becomes smaller and thus the

average flux becomes smaller. This is why higher substrate conductivity results in

smaller external self-inductance. This also explains that when the substrate conductivity

is very low, the external self-inductance shows little frequency dependence because the

metal ground plane is the main return path. However, when the substrate conductivity

becomes higher, the external self-inductance shows more frequency dependence.

52

Similar analysis can be applied to external self-resistance, which increases with

increased substrate conductivity. The smallest external self-resistance is achieved when

the substrate has the lowest conductivity. And the whole system approaches an ideal

microstrip system.

MUTUAL IMPEDANCE BETWEEN ON-CHIP INTERCONNECTS

Between two coupled on-chip interconnects, there exist mutual inductance. The

typical layout of on-chip interconnects are either vertical or horizontal. If the two

interconnects are perpendicular to each other, they are not inductive coupled and the

mutual inductance is zero. If they are parallel to each other, the mutual inductance is

maximized.

Consider two parallel interconnects p and q as shown in Figure 27.

53

p q Insulator Substrate Metal Plate Metal Metal
p
q
Insulator
Substrate
Metal Plate
Metal
Metal

Figure 27 – Parallel On-Chip Interconnects

The mutual inductance L between p and q is defined as m , pq dI q
The mutual inductance
L
between p and q is defined as
m
,
pq
dI
q
V
L
(81)
pq
m, pq
dt
where
V
is the voltage across the two ends of p induced by q. The low frequency
pq
expression of mutual inductance between two conductors k
and
m is given by [12]
d
l
d l
1
k
m
k
m
L
 c
 c
da da
(82)
m
k
m
4
a
a
a
a
b
b
r
k
m
k
m
k
m
km
where
a
and
a
are the area of the conductor cross-section of k and m respectively,
k
m
b
and
b
are the starting points,
c
and
c
are the end points, and
d l
and
d l
k
m
k
m
k
m

are infinitesimal conductor segments. To account for high frequency effects and the lossy

semiconductor substrate, Equation (85) has to be modified.

54

Since the thickness of on-chip interconnects is smaller than double the skin depth

below 10GHz, one can assume no frequency dependence of the current distribution on

the thickness dimension of the on-chip interconnects, which can then be approximated as

filaments as shown in Figure 28. The effects of the lossy substrate can be modeled by

taking the complex image approach [16].

As shown in Figure 28, p and q are two thin parallel on-chip interconnects. q

carries a current. The return current of q in the substrate and the metal ground plane is

modeled by replacing the substrate and the metal ground plane with a complex image q’.

y

q1

p q zˆ yˆ   J x q y p2 Virtual Ground Plane y q2
p
q
J
x
q
y
p2
Virtual Ground Plane
y
q2
h
pq
y
p1
h
qq'
W
x
W
W
x
W
p
p
p
q
q
q
2
2
2
2
 J
x
q

q' (image)

Figure 28 – Illustration of Mutual Inductance Calculation between Parallel On-Chip

Interconnects

55

The induced voltage on p as a result of the current carried by q is contributed by

both the signal current on q and its image current, which is given by

V

pq

L

m, pq

L

m, pq '

dI

q

dt

(83)

The mutual inductance between p and q is the summation

L

m

,

pq

and

L

m , pq '

.

They

are opposite in sign because the image current flows in the opposite direction of the

signal current. By expanding Equation (85),

L

m

,

pq

is given by

L

m

,

pq

1

4

W

p

W W   p q J x   p 1 p 2 q 1
W
W
p
q
J
x
p 1
p 2
q 1
q 2
q
q
 x
2
 y
 x
2
 y
dx dy
dx dy
W
W
p
p
q
q
p
y
q
y
x
x
2
2
2
p 1
q 1
p 1
q 1
x
x
y
y
h
2
2
p
q
p
q
pq
W
q
2
J
x
dx
W
q
q
q
q

2

(84)

where

W

p

and

W

q

are the width of p and q respectively and

h

pq

is given by the

complex image method. Similarly,

L

m , pq '

is expressed as

56

W W   p q J x   p 1 p 2 q 1
W
W
p
q
J
x
p 1
p 2
q 1
q 2
q
q
 x
2
 y
 x
2
 y
dx
dy
dx dy
W
W
p
p
q
q
p
y
q
y
x
2
2
2
p 1
x
q 1
1
p 1
q 1
x
x
y
y
h
2
2
p
q
p
q
pq
L
m pq
,
W
4
W
q
p
2
J
x
dx
W
q
q
q
q
2
(85)
The total mutual inductance between the two parallel on-chip interconnects p and
q is given by
L
 L
 L
(86)
m
m , pq
m , pq '

The integration can be numerically calculated by finite discretization. As

illustrated in Figure 29, conductor p can be discretized into N1-by-N2 small segments,

where N1 is the total number of mesh points on the x direction and N2 is the total number

of mesh points on the y direction. Similar discretizations can be done on q and q’. The

differential mutual inductance is calculated for each two segments, and the total mutual

inductance is the summation of all the differential ones.

57

y

q1

p q zˆ yˆ   J x q y r p2 pq Virtual Ground Plane
p
q
J
x
q
y
r
p2
pq
Virtual Ground Plane
y
q2
h
pq
y
p1
h
qq'
W
x
W
W
x
W
p
p
p
q
q
q
2
2
2
2
 J
x
q

q' (image)

Figure 29 – Illustration of Discretization to Calculate Mutual Inductance between Parallel

On-Chip Interconnects

Since both the current distribution on q and q’ and the distance between q and q

are complex, the mutual inductance is complex, too. This complex inductance can again

be interpreted into the combination of mutual inductance and mutual resistance.

58

L

m complex

,

L

m

R

m

j

(87)

The mutual inductance represents the magnetic coupling of the two interconnects

through the magnetic field. The mutual resistance can be explained by the resistive

coupling between the two interconnect through the substrate. The substrate provides a

resistive path between the return current of both p and q.

The simulation results have been compared with published results and agree well

with the full-wave solution given by ADS Momentum [15].

Here, the mutual impedance between two parallel interconnects in a 0.25 m

CMOS process is studied.

Figure 30 plots the mutual impedance at different substrate doping levels versus

the frequency. The two interconnects are both on Metal 5 layer and 4 m wide. The

edge-to-edge spacing between them is taken to be 2um. The thickness of the substrate is

250 m and the oxide thickness is 3.96 m [36]. The interconnect conductivity is

3.70 10

7

S/m [36].

59

9.5 9 8.5 8 7.5 7 6.5 6 5.5 ­3 5 Na=10 19 cm Na=10 18
9.5
9
8.5
8
7.5
7
6.5
6
5.5
­3
5
Na=10 19 cm
Na=10 18 cm
­3
­3
4.5
Na=10 17 cm
Na=10 16 cm
­3
4
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
Mutual Inductance, nH/cm

(a) Mutual Inductance

100 Na=10 19 cm -3 Na=10 18 cm -3 90 Na=10 17 cm -3 Na=10 16
100
Na=10 19 cm -3
Na=10 18 cm -3
90
Na=10 17 cm -3
Na=10 16 cm -3
80
70
60
50
40
30
20
10
0
1
2
3
4
5
6
7
8
9
10
Frequency, GHz
Mutual Resistance,  /cm

(b) Mutual Resistance

Figure 30 – Mutual Impedance between Coupled On-Chip Interconnects versus Substrate

Conductivity

60

From Figure 30, it is seen that the mutual inductance decreases and the mutual

resistance increases at increased substrate conductivity. Both of them show more

frequency dependence at higher substrate doping levels.

As seen from Figure 28, the total mutual inductance consists of two terms: one is

the mutual inductance between p and q, the other is the one between p and q’. As seen

from Equation (85), mutual inductance is reverse proportional to the spacing between the

two interconnects. Since the spacing between p and q is much smaller than that between

p and q’,

L

m

,

pq

dominates the total mutual inductance. Since the current on q and q’ are

in the opposite direction,

L

m , pq '

will subtract

L

m

,

pq

to get the total mutual inductance

as shown in Equation (89). Therefore, if the spacing between p and q is constant, the

further q’ is away from p, the smaller

  • L m , pq '

and the larger the total mutual inductance.

When the substrate conductivity is very low, the majority of the return current of the

interconnect flows in the metal ground plane. The distance between the signal current

and the return current is close to twice the substrate thickness. The total mutual

inductance is maximized. However, at increased substrate conductivity, more return

current flows in the substrate instead of the metal ground plane, which leads to reduced

vertical distance between q and q’. This implies a larger

  • L m , pq '

and a smaller total

mutual inductance.

Similar analysis can be applied for the mutual resistance. If the substrate

conductivity is low, the return current of q will be mainly the surface current on the metal

61

ground plane. Since the vertical distance between the metal ground plane and p is

relatively large, the return current will induce little current on p. Therefore the mutual

resistive coupling is small. However, if the substrate conductivity is high, more return

current will flow near the substrate surface. Since they are very close to p with a thin

insulator in between, they will induce significant amount of current on p and the mutual

resistive coupling is strong.

62