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Fundamentals

Tenth Edition

Floyd

Chapter :

ADC-DAC

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Sampling

signals. For processing, the signal is normally converted to a

digital signal by sampling the input.

input must be filtered with a Analog

input Sampling

low-pass anti-aliasing filter. signal circuit

pulses

frequencies that exceed a

certain limit that is determined

by the sampling rate.

Sampled

version of

input signal

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Anti-aliasing Filter

understand the sampling theorem which essentially states:

In order to recover a signal, the sampling rate must be

greater than twice the highest frequency in the signal.

Stated as an equation, fsample > 2fa(max)

where fsample = sampling frequency

fa(max) = highest harmonic in the analog signal

If the signal is sampled less than this, the recovery process will produce

frequencies that are entirely different than in the original signal. These

“masquerading” signals are called aliases.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Anti-aliasing Filter

frequencies in the input signal to only those that meet the

requirements of the sampling theorem.

Filtered

Unfiltered

analog analog Sampling frequency

frequency

frequency

spectrum

spectrum spectrum

f

fc fsample

Overlap causes

aliasing error

The filter’s cutoff frequency, fc, should be less than ½ fsample.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion

digital system, the analog signal is converted to digital form

after the anti-aliasing filter.

The first step in converting a signal to digital form is to use a sample-

and-hold circuit. This circuit samples the input signal at a rate

determined by a clock signal and holds the level on a capacitor until

the next clock pulse.

10 V

A positive half-wave from 0-10 V

is shown in blue. The sample-and-

hold circuit produces the staircase

representation shown in red.

0V

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion

The second step is to quantize these staircase levels to binary coded

form using an analog-to-digital converter (ADC). The digital values

can then be processed by a digital signal processor or computer.

0.0000

What is the maximum unsigned binary value for 10.0001

the waveform? 100.0001

101.1110

111.0111

10 V = 10102 V. The table lists the quantized 1000.1011

1001.1001

binary values for all of the steps. Peak = 10 V 1010.0000

1010.0000

10 V 1001.1001

1000.1011

111.0111

101.1110

100.0001

10.0001

0V 0.0000

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Anti-aliasing Filter

Most signals have higher frequency harmonic and noise.

For most ADCs, the sampling and filter cutoff frequencies

are selected to be able to reconstruct the desired signal

without including unnecessary harmonics and noise.

An example of a reasonable sampling rate is in a digital audio CD. For

audio CDs, sampling is done at 44.1 kHz because audio frequencies

above 20 kHz are not detectable by the ear.

anti-aliasing filter have for a

digital audio CD?

Less than 22.05 kHz.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Sample-and-Hold and ADC

circuit and the analog-to-digital converter. At this point,

the original analog signal has been converted to a digital

signal.

Samples held for

one clock pulse

ADC

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Many ICs can perform both functions on a single chip and include

two or more channels. For audio applications, the AD1871 is an

example of a stereo audio ADC.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

+VREF

Op-amp

R comparators

Input from +

sample- –

and-hold

R + Priority

– encoder

–

7

6

5

The flash ADC uses a series high- R

+ 4

1

2

D0 Parallel

D1 binary

3

speed comparators that compare the

– output

4 D2

2

R + 1

input with reference voltages. Flash – 0 EN

+

–

+

Enable

– pulses

1023

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

The dual-slope ADC:

1. The dual-slope ADC integrates the input voltage for a fixed time

while the counter counts to n.

2. Control logic switches to the VREF input.

2. A fixed-slope ramp starts from –V as the counter counts. When it

reaches 0 V, the counter output is latched.

Vin I

+ – CLK

I C

SW – -V

R ≈0 V A1 – HIGH C

+ A2 Counter

+ R

–VREF Fixedtime

Variable interval n

0 0 t = n counts

Variable Variable

voltage slope

Fixed-slope

–V –V

ramp

Control Latches

logic

EN

D7 D6 D5 D4 D3 D2 D1 D0

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

The successive approximation ADC:

1. Starting with the MSB, each bit in the successive approximation

register (SAR) is activated and tested by the digital-to-analog converter

(DAC). Vout

DAC

2. After each test, the DAC

produces an output voltage that

D0

represents the bit.

D1 Parallel

3. The comparator compares Comparator binary

D2

– output

this voltage with the input Input + D3

signal. If the input is larger, signal (MSB) (LSB)

the bit is retained; otherwise D

SAR Serialb

inary

it is reset (0). C output

CLK

The method is fast and has a fixed conversion time for all inputs.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

An integrated circuit successive approximation ADC is the

ADC804. This popular ADC is an 8-bit converter that

completes a conversion in 64 clock periods (100 µs).

VCC

(20)

(1) (5)

CS ADC0804 INTR

RD

(2) (19) The completion is signaled by the

(3) (18) CLK R (out)

INTR line going LOW.

∆

WR D0

(4) ∆ (17)

CLK IN D1

(6) ∆ (16)

Analog Vin+ D2

(7) (15) Digital

input Vin–

∆

D3

(9) (14) data

REF/2 D4

∆

∆ (13) output

D5

(12)

D6

∆

(11)

D7

∆

(8) (10)

ANLG DGTL

GND GND

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

The sigma-delta ADC:

With sigma-delta conversion, the difference between two

samples of the analog input signal integrated and quantized.

The density of 1s at the output is proportional to the input

signal.

Summing

point

Analog + ∆ 1-bit Quantized output

input Σ Integrator is a single bit

quantizer data stream.

signal –

DAC

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Analog-to-Digital Conversion Methods

bit quantized output for a set interval. The output of the

counter is latched with the parallel binary code.

Summing

point

Analog + ∆ 1-bit n-bit Binary code

Σ Integrator Latch

input quantizer counter output

signal – . .

. .

. .

. .

. .

1-bit

DAC

Sigma-delta ADCs can have high resolution and have advantages for

rejecting noise signals (such as 60 Hz power line interference). They

are available in ICs with internal programmable amplifiers. For these

reasons, they are widely used in instrumentation applications.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital-to-Analog Conversion Methods

Binary-weighted-input DAC:

The binary-weighted-input DAC is a basic DAC in which

the input current in each resistor is proportional to the

column weight in the binary numbering system. It requires

very accurate resistors and identical HIGH level voltages

for accuracy. LSB 8R

D0 Rf

The MSB is represented by the + –

I0

4R If

largest current, so it has the D1

smallest resistor. To simplify I1 – Vout

2R

analysis, assume all current D2 I=0

+ Analog

goes through Rf and none into R

I2

output

the op-amp. D3

MSB I3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital-to-Analog Conversion Methods

A certain binary-weighted-input DAC has a binary input of

1101. If a HIGH = +3.0 V and a LOW = 0 V, what is Vout?

120 kΩ

+3.0 V Rf

60 kΩ

10 kΩ

0V

30 kΩ

–

+3.0 V Vout

+

15 kΩ

+3.0 V

I out = −( I 0 + I1 + I 2 + I 3 )

⎛ 3.0 V 3.0 V 3.0 V ⎞

= − ⎜ +0 V+ + ⎟ = −0.325 mA

⎝ 120 kΩ 30 kΩ 15 kΩ ⎠

Vout = Iout Rf = (−0.325 mA)(10 kΩ) = −3.25 V

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital-to-Analog Conversion Methods

R-2R ladder:

The R-2R ladder requires only two values of resistors. By calculating

a Thevenin equivalent circuit for each input, you can show that the

output is proportional to the binary weight of inputs that are HIGH.

VS

Each input that is HIGH contributes to the output: Vout = − n −i

2

where VS = input HIGH level voltage

n = number of bits Inputs

i = bit number D0 D1 D2 D3

For accuracy, the resistors R1 R3 R5 R7 Rf = 2R

must be precise ratios, 2R 2R 2R 2R

R2 R4 R6 R8

which is easily done in –

integrated circuits. 2R R R R Vout

+

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital-to-Analog Conversion Methods

An R-2R ladder has a binary input of 1011. If a

HIGH = +5.0 V and a LOW = 0 V, what is Vout?

D0 D1 D2 D3

+5.0 V +5.0 V 0V +5.0 V

R1 R3 R5 R7 Rf = 50 kΩ

50 kΩ

50 kΩ

50 kΩ

50 kΩ

R2 R4 R6 R8

–

50 kΩ

25 kΩ

25 kΩ

25 kΩ

Vout

+

VS

Apply Vout = −

n −i

to all inputs that are HIGH, then sum the results.

2

5V 5V

Vout ( D0 ) = − 4−0 = −0.3125 V Vout ( D1 ) = − 4−1 = −0.625 V

2 2

5V

Vout ( D3 ) = − 4−3 = −2.5 V Applying superposition, Vout = −3.43 V

2

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Resolution and Accuracy of DACs

available in IC packages. DACs based on the R-2R network

are available in 8, 10, and 12-bit versions. The resolution

is an important specification, defined as the reciprocal of

the number of steps in the output.

What is the resolution of the BCN31 R-2R

ladder network, which has 8-bits?

28 – 1 = 255 1/255 = 0.39%

The accuracy is another important specification and is derived from a

comparison of the actual output to the expected output. For the BCN31,

the accuracy is specified as ±½ LSB = 0.2%.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Reconstruction Filter

After converting a digital signal to analog, it is passed

through a low-pass “reconstruction filter” to smooth the

stair steps in the output. The cutoff frequency of the

reconstruction filter is often set to the same limit as the

anti-aliasing filter, to block higher harmonics due to the

digitizing process.

Reconstruction

Filter

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital Signal Processing

working in real time (as events happen). It is basically a

specialized microprocessor with a reduced instruction set.

After filtering and converting the analog signal to digital, the DSP takes

over. It may enhance the signal in some predetermined way (reducing

noise or echoes, improving images, encrypting the signal, etc.). The

signal can then be converted back to analog form if desired.

10110 10110

01101 01101

00011 00011

11100 11100 Enhanced

Analog Anti-aliasing Sample-and- Reconstruction

signal filter hold circuit ADC DSP DAC filter analog

signal

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Summary

Digital Signal Processing

Because speed is important in DSP applications, assembly

language is frequently used because in general it executes

faster. Program cache/program memory

(32-bit address, 256-bit data)

Program fetch

Control

Instruction dispatch registers

EMIF Control

Data path A Data path B logic

Test

of the TMS320C6000 .L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2

Evaluation

Interrupts

series DSP

Data cache/data memory Additional

(32-bit address, 8-, 16-, 32-. 64-bit data) peripherals

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

Selected Key Terms

frequency

at a specified sampling frequency; a frequency

equal or less than half the sampling frequency.

Quantization

The process whereby a binary code is assigned to

each sampled value during analog-to-digital

conversion.

Analog-to-digital A circuit used to convert an analog signal to

converter (ADC)

digital form.

DSP

Digital signal Processor; a special type of

microprocessor that processes data in real time.

converter (DAC) form.

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

1. If an anti-aliasing filter is not used in digitizing a signal

the recovery process

a. is slowed

b. may include alias signals

c. will have less noise

d. all of the above

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

2. An anti-aliasing filter should have

a. fc more than 2 times the Nyquist frequency

b. fc equal to the Nyquist frequency

c. fc more than ½ fsample

d. fc less than ½ fsample

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

3. The number of comparators required in a 10-bit flash

ADC is

a. 255

b. 511

c. 1023

d. 4095

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

4. The block diagram is for a successive-approximation

ADC. The top block is

a. an SAR

Vout

b. a DAC

c. an ADC D0

Parallel

D1

binary

d. a comparator D2 output

–

Input + D3

signal (MSB) (LSB)

D Serialb

inary

C output

CLK

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

5. The ADC804 integrated circuit signals a completed

conversion by

a. INTR goes LOW VCC

(20)

(5)

CS ADC0804 INTR

(2) (19)

RD CLK R (out)

c. RD goes LOW WR

(3)

(4)

∆

∆

(18)

(17)

D0

CLK IN D1

(6) ∆ (16)

Analog Vin+ D2

d. CLK R goes HIGH input Vin–

(7)

(9)

∆ (15)

(14)

D3 Digital

data

REF/2 D4

∆

∆ (13) output

D5

(12)

D6

∆

(11)

D7

∆

(8) (10)

ANLG DGTL

GND GND

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

6. A sigma-delta circuit is a form of

a. DSP

b. DAC

c. ADC

d. SAR

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

7. The circuit shown is a

a. DSP 8R

Rf

+ –

b. DAC 4R

I0

If

c. ADC 2R

I1 – Vout

I=0

+

d. SAR R

I2

I3

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

8. For the circuit shown, the input on the far left is for the

a. analog input

b. clock Inputs

c. LSB

R1 R3 R5 R7 Rf = 2R

d. MSB R2

2R

R4

2R

R6

2R

R8

2R

–

2R R R R Vout

+

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

9. A reconstruction filter

a. is a low-pass filter

b. can have the same response as an anti-aliasing filter

c. smoothes the output from a DAC

d. all of the above

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

10. A DSP is a specialized microprocessor that

a. has a very large instruction set

b. is deigned to be very fast

c. has internal anti-aliasing and reconstruction filters

d. all of the above

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

© 2008 Pearson Education

Answers:

1. b 6. c

2. d 7. b

3. c 8. c

4. b 9. d

5. a 10. b

Floyd, Digital Fundamentals, 10th ed © 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved

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