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Lab Lezione03

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Parte 2

Corso di Architettura degli Elaboratori (laboratorio)

francesco.deangelis@unicam.it

Scuola di Scienze e Tecnologie - Sezione di Informatica

Architettura degli Elaboratori e Laboratorio - AA 2011/12

Overview

! Part 1 Gate Circuits and Boolean Equations

Binary Logic and Gates

Boolean Algebra

Standard Forms

Two-Level Optimization

Map Manipulation

Practical Optimization (Espresso)

Multi-Level Circuit Optimization

Other Gate Types

Exclusive-OR Operator and Gates

High-Impedance Outputs

Chapter 2 - Part 2

Circuit Optimization

! Goal: To obtain the simplest

implementation for a given function

! Optimization is a more formal approach

to simplification that is performed using

a specific procedure or algorithm

! Optimization requires a cost criterion to

measure the simplicity of a circuit

! Distinct cost criteria we will use:

Literal cost (L)

Gate input cost (G)

Gate input cost with NOTs (GN)

Chapter 2 - Part 2

Literal Cost

! Literal a variable or it complement

! Literal cost the number of literal

appearances in a Boolean expression

corresponding to the logic circuit

diagram

! Examples:

F = BD + A B C + A C D

L=8

F = BD + A BC + A B D + AB C

L=?

F = (A + B)(A + D)(B + C + D)(B + C + D) L = ?

Which solution is best?

Chapter 2 - Part 2

! Gate input costs - the number of inputs to the gates in the

implementation corresponding exactly to the given equation

or equations. (G - inverters not counted, GN - inverters counted)

! For SOP and POS equations, it can be found from the

equation(s) by finding the sum of:

all literal appearances

the number of terms excluding single literal terms,(G) and

optionally, the number of distinct complemented single literals (GN).

! Example:

F = BD + A B C + AC D

G = 11, GN = 14

F = BD + A B C + A B D + AB C

G = , GN =

F = (A + B)(A + D)(B + C + D)( B + C + D) G = , GN =

Which solution is best?

Chapter 2 - Part 2

GN = G + 2 = 9

L=5

! F = A + B C + B C

G=L+2= 7

! Example 1:

B

C

A

literal OR input.

! G (gate input count) adds the remaining OR gate inputs

! GN(gate input count with NOTs) adds the inverter inputs

Chapter 2 - Part 2

! Example 2:

!

!

!

!

A

B

C

F = A B C + AB C

L = 6 G = 8 GN = 11

F = (A + C)( B + C)( A + B)

L = 6 G = 9 GN = 12

A

literal cost

B

! But first circuit has better C

gate input count and better

gate input count with NOTs

! Select it!

Chapter 2 - Part 2

! Minimizing the gate input (or literal) cost of a (a

set of) Boolean equation(s) reduces circuit cost.

! We choose gate input cost.

! Boolean Algebra and graphical techniques are

tools to minimize cost criteria values.

! Some important questions:

When do we stop trying to reduce the cost?

Do we know when we have a minimum cost?

for two-level (SOP and POS) circuits first.

! Introduce a graphical technique using Karnaugh

maps (K-maps, for short)

Chapter 2 - Part 2

! A K-map is a collection of squares

The collection of squares is a graphical representation

of a Boolean function

Adjacent squares differ in the value of one variable

Alternative algebraic expressions for the same function

are derived by recognizing patterns of squares

A reorganized version of the truth table

A topologically-warped Venn diagram as used to

visualize sets in algebra of sets

Chapter 2 - Part 2

! Provide a means for:

Finding optimum or near optimum

! SOP and POS standard forms, and

! two-level AND/OR and OR/AND circuit

implementations

variables

Visualizing concepts related to manipulating

Boolean expressions, and

Demonstrating concepts used by computeraided design programs to simplify large

circuits

Chapter 2 - Part 2

10

! A 2-variable Karnaugh Map:

y=0 y=1

Note that minterm m0 and

m0 = m1 =

minterm m1 are adjacent

x=0

and differ in the value of the

xy

xy

variable y

x = 1 m2 = m3 =

Similarly, minterm m0 and

xy xy

minterm m2 differ in the x variable.

Also, m1 and m3 differ in the x variable as well.

Finally, m2 and m3 differ in the value of the

variable y

Chapter 2 - Part 2

11

! The K-Map is just a different form of the truth table.

! Example Two variable function:

We choose a,b,c and d from the set {0,1} to

implement a particular function, F(x,y).

Function Table

Input

Values

(x,y)

Function

Value

F(x,y)

00

01

10

11

a

b

c

d

K-Map

y=0

x=0 a

x=1 c

y=1

b

d

Chapter 2 - Part 2

12

! Example: F(x,y) = x

x=0

x=1

containing 1 s can be combined using the

Minimization Theorem:

F( x , y ) = x y + x y = x

Chapter 2 - Part 2

13

! Example: G(x,y) = x + y

G = x+y y = 0 y = 1

x=0

x=1

1 s can be combined using the Minimization

Theorem: G (x,y) = xy + xy + xy

G( x , y ) = (x y + x y )+ (xy + x y )= x + y

Duplicate x y

Chapter 2 - Part 2

14

! A three-variable K-map:

yz=00

yz=01

yz=11

yz=10

x=0

m0

m1

m3

m2

x=1

m4

m5

m7

m6

terms:

yz=00 yz=01 yz=11

x=0 x y z

xyz

xyz

xyz

x=1

xyz

xyz

yz=10

xyz

xyz

bit position, the minterms are adjacent on the K-Map

Chapter 2 - Part 2

15

Adjacency

Chapter 2 - Part 2

16

! Map use largely involves:

Entering values into the map, and

Reading off product terms from the

map.

y

y

x

x

yz

00 01 11 10

0 0

x 1

Chapter 2 - Part 2

17

Example Functions

! By convention, we represent the minterms of F by a "1"

in the map and leave the minterms of F blank

y

! Example:

F(x, y, z) = m(2,3,4,5)

x 41

! Example:

G(a, b, c) = m(3,4,6,7)

! Learn the locations of the 8

indices based on the variable x

order shown (x, most significant

and z, least significant) on the

map boundaries

0

4

1

7

1

2

6

z

Chapter 2 - Part 2

18

Combining Squares

! By combining squares, we reduce number of

literals in a product term, reducing the literal cost,

thereby reducing the other two cost criteria

On a 3-variable K-Map:

One square represents a minterm with three

variables

Two adjacent squares represent a product term with

two variables

Four adjacent terms represent a product term

with one variable

Eight adjacent terms is the function of all ones (no

variables) = 1.

Chapter 2 - Part 2

19

! Example: Let

F = m(2,3,6,7)

1

7

1

1

6

1

z

! Applying the Minimization Theorem three

times:

F( x, y , z ) = x y z + x y z + x y z + x y z

= yz + y z

=y

correspond to the term "y".

Chapter 2 - Part 2

20

Three-Variable Maps

! Reduced literal product terms for SOP standard

forms correspond to rectangles on K-maps

containing cell counts that are powers of 2.

! Rectangles of 2 cells represent 2 adjacent

minterms; of 4 cells represent 4 minterms that

form a pairwise adjacent ring.

! Rectangles can contain non-adjacent cells as

illustrated by the pairwise adjacent ring

above.

Chapter 2 - Part 2

21

Three-Variable Maps

! Topological warps of 3-variable K-maps

that show all adjacencies:

! Venn Diagram

0

Cylinder

4 X

6 7 5

Y 3 1Z

2

Chapter 2 - Part 2

22

Three-Variable Maps

! Example Shapes of 2-cell Rectangles:

z

! Read off the product terms for the

rectangles shown

Chapter 2 - Part 2

23

Three-Variable Maps

! Example Shapes of 4-cell Rectangles:

z

! Read off the product terms for the

rectangles shown

Chapter 2 - Part 2

24

! K-Maps can be used to simplify Boolean functions by

systematic methods. Terms are selected to cover the

1s in the map.

! Example:

xy

1 1 1

x

1 1

z

F(x, y, z) =

z+xy

Chapter 2 - Part 2

25

! Use a K-map to find an optimum SOP

equation for F(X, Y, Z) = m(0,1,2,4,6,7)

Chapter 2 - Part 2

26

! Map and location of minterms:

Y

Variable Order

W

12

13

15

14

11

10

Z

Chapter 2 - Part 2

27

! Four variable maps can have rectangles

corresponding to:

A single 1 = 4 variables, (i.e. Minterm)

Two 1s = 3 variables,

Four 1s = 2 variables

Eight 1s = 1 variable,

Sixteen 1s = zero variables (i.e.

Constant "1")

Chapter 2 - Part 2

28

Four-Variable Maps

! Example Shapes of Rectangles:

Y

12

13

15

14

11

10

Z

Chapter 2 - Part 2

29

Four-Variable Maps

Chapter 2 - Part 2

30

Four-Variable Maps

! Example Shapes of Rectangles:

Y

12

13

15

14

11

10

Z

Chapter 2 - Part 2

31

!F(W, X, Y, Z) = m(0, 2,4,5,6,7,8,10,13,15)

Chapter 2 - Part 2

32

! F(W, X, Y, Z) = m(3,4,5,7,9,13,14,15)

Chapter 2 - Part 2

33

Systematic Simplification

!A Prime Implicant is a product term obtained by combining

the maximum possible number of adjacent squares in the map

into a rectangle with the number of squares a power of 2.

the only prime implicant that covers (includes) one or more

minterms.

determined by inspection of a K-Map.

minterm of the function, at least one prime implicant in the set

of prime implicants includes the minterm.

Chapter 2 - Part 2

34

! Find ALL Prime Implicants

CD

C

BD

1

BD

A

AB

D

AD

C

BD

1

B

BD

1

B

BC

Chapter 2 - Part 2

35

! Find all prime implicants for:

F(A, B, C, D) = m(0,2,3,8,9,10,11,12,13,14,15)

Chapter 2 - Part 2

36

Another Example

! Find all prime implicants for:

G(A, B, C, D) = m(0,2,3,4,7,12,13,14,15)

Hint: There are seven prime implicants!

Chapter 2 - Part 2

37

! For five variable problems, we use two adjacent K-maps.

It becomes harder to visualize adjacent minterms for

selecting PIs. You can extend the problem to six

variables by using four K-Maps.

V=0

V=1

Y

Y

X

W

W

Z

Z

Chapter 2 - Part 2

38

! Sometimes a function table or map contains entries for

which it is known:

the input values for the minterm will never occur, or

The output value for the minterm is not used

! Instead, the output value is defined as a don't care

! By placing don't cares ( an x entry) in the function table

or map, the cost of the logic circuit may be lowered.

! Example 1: A logic function having the binary codes for the

BCD digits as its inputs. Only the codes for 0 through 9 are

used. The six codes, 1010 through 1111 never occur, so the

output values for these codes are x to represent don t

cares.

Chapter 2 - Part 2

39

! The map below gives a function F1(w,x,y,z) which

is defined as "5 or more" over BCD inputs. With

the don't cares used for the 6 non-BCD

combinations:

y

F1 (w,x,y,z) = w + x z + x y G = 7

00 01 03 02

04 15 17 16

the don't cares were treated as "0s."

x

X12 X13 X15 X14 F2(w, x, y, z) = w x z + w x y + w x y G = 12

! For this particular function, cost G for the

1 8 1 9 X11 X10

POS solution for F1(w,x,y,z) is not changed

z

by using the don't cares.

Chapter 2 - Part 2

40

! Find the optimum POS solution:

d (1,4,6)

Hint: Use F and complement it to get the

result.

Chapter 2 - Part 2

41

Optimization Algorithm

! Find all prime implicants.

! Include all essential prime implicants in the

solution

! Select a minimum cost set of non-essential

prime implicants to cover all minterms not yet

covered:

Obtaining an optimum solution: See Reading

Supplement - More on Optimization

Obtaining a good simplified solution: Use the

Selection Rule

Chapter 2 - Part 2

42

! Minimize the overlap among prime

implicants as much as possible. In

particular, in the final solution, make

sure that each prime implicant selected

includes at least one minterm not

included in any other prime implicant

selected.

Chapter 2 - Part 2

43

! Simplify F(A, B, C, D) given on the KSelected Essential

map.

C

1

1

A

1

1

D

1

D

Chapter 2 - Part 2

44

! Simplify F(A, B, C, D) given on the K-map.

C

1

A

x

1

1

D

Essential

Selected

B

A

x

1

D

Minterms covered by essential prime implicants

Chapter 2 - Part 2

45

Practical Optimization

! Problem: Automated optimization

algorithms:

require minterms as starting point,

require determination of all prime

implicants, and/or

require a selection process with a potentially

very large number of candidate solutions to

be found.

requiring any of the above in the general

case

Chapter 2 - Part 2

46

Chapter 2 - Part 2

47

Chapter 2 - Part 2

48

Multiple-Level Optimization

! Multiple-level circuits - circuits that are

not two-level (with or without input and/

or output inverters)

! Multiple-level circuits can have reduced

gate input cost compared to two-level

(SOP and POS) circuits

! Multiple-level optimization is performed

by applying transformations to circuits

represented by equations while

evaluating cost

Chapter 2 - Part 2

50

Transformations

! Factoring - finding a factored form from

SOP or POS expression

Algebraic - No use of axioms specific to

Boolean algebra such as complements or

idempotence

Boolean - Uses axioms unique to Boolean

algebra

as a set of new functions

Chapter 2 - Part 2

51

Transformations (continued)

! Substitution of G into F - expression

function F as a function of G and some or

all of its original variables

! Elimination - Inverse of substitution

! Extraction - decomposition applied to

multiple functions simultaneously

Chapter 2 - Part 2

52

Transformation Examples

! Algebraic Factoring

F = A C D + A B C + ABC + AC D

G = 16

Factoring:

F = A (C D + BC) + A (BC + C D ) G = 16

Factoring again:

F = A C ( B + D ) + AC (B + D )

G = 12

Factoring again:

F = (A C + AC) (B + D)

G = 10

Chapter 2 - Part 2

53

Transformation Examples

! Decomposition

The terms B + D and A C + AC can be defined

as new functions E and H respectively,

decomposing F:

F = E H, E = B + D , and H = A C + AC G = 10

! This series of transformations has reduced G from

16 to 10, a substantial savings. The resulting

circuit has three levels plus input inverters.

Chapter 2 - Part 2

54

Transformation Examples

! Substitution of E into F

Returning to F just before the final factoring step:

F = A C ( B + D ) + AC (B + D)

G = 12

Defining E = B + D, and substituting in F:

F = A C E + ACE

G = 10

This substitution has resulted in the same cost as the

decomposition

Chapter 2 - Part 2

55

Transformation Examples

! Elimination

Beginning with a new set of functions:

X=B+C

Y=A+B

Z = AX + C Y

G = 10

Eliminating X and Y from Z:

Z = A (B + C) + C (A + B)

G = 10

Flattening (Converting to SOP expression):

Z = A B + A C + AC + BC

G = 12

This has increased the cost, but has provided an new

SOP expression for two-level optimization.

Chapter 2 - Part 2

56

Transformation Examples

! Two-level Optimization

The result of 2-level optimization is:

Z=AB+ C

G=4

! This example illustrates that:

Optimization can begin with any set of equations,

not just with minterms or a truth table

Increasing gate input count G temporarily during a

series of transformations can result in a final

solution with a smaller G

Chapter 2 - Part 2

57

Transformation Examples

! Extraction

Beginning with two functions:

E = A B D + A BD

H = B C D + BCD

G = 16

Finding a common factor and defining it as a

function:

F = B D + BD

We perform extraction by expressing E and H as

the three functions:

F = B D + BD, E = A F, H = CF

G = 10

The reduced cost G results from the sharing of logic

between the two output functions

Chapter 2 - Part 2

58

G=ACE + ACF + ADE + ADF + BCDEF (figure (a))

H= ABCD + ABE + ABF + BCE + BCF

G=A(CE+CF+DE+DF) + BCDEF

G=A(C+D)(E+F)+BCDEF

G=A(C+D)X2 + BX1EF

X1=CD, X1=C+D, X2=(E+F), X2=EF

G=AX1X2 + BX1X2

H=B(ACD+AE+AF+CE+CF)

H=B(A(CD) + (A+C)(E+F)) X3=A+C

G=AX1X2 + BX1X2

H=B(AX1+X3X2) = BAX1 + BX3X2 (figure (b) and (c))

Chapter 2 - Part 2

59

Chapter 2 - Part 2

60

Chapter 2 - Part 2

61

! Why?

Implementation feasibility and low cost

Power in implementing Boolean functions

Convenient conceptual representation

! Gate classifications

Primitive gate - a gate that can be described using a

single primitive operation type (AND or OR) plus an

optional inversion(s).

Complex gate - a gate that requires more than one

primitive operation type for its description

Chapter 2 - Part 3

62

Buffer

! A buffer is a gate with the function F = X:

X

same as a connection!

! So why use it?

A buffer is an electronic amplifier used to

improve circuit voltage levels and increase the

speed of circuit operation.

Chapter 2 - Part 3

63

NAND Gate

! The basic NAND gate has the following symbol,

illustrated for three inputs:

AND-Invert (NAND)

X

Y

Z

F( X , Y , Z ) = X Y Z

function with a NOT applied. The symbol shown

is an AND-Invert. The small circle ( bubble )

represents the invert function.

Chapter 2 - Part 3

64

! Applying DeMorgan's Law gives Invert-OR (NAND)

X

Y

Z

F( X , Y , Z ) = X + Y + Z

inverted and then ORed together.

! AND-Invert and Invert-OR both represent the NAND

gate. Having both makes visualization of circuit function

easier.

! A NAND gate with one input degenerates to an inverter.

Chapter 2 - Part 3

65

! The NAND gate is the natural implementation for

CMOS technology in terms of chip area and speed.

! Universal gate - a gate type that can implement any

Boolean function.

! The NAND gate is a universal gate as shown in Figure

2-24 of the text.

! NAND usually does not have a operation symbol defined

since

the NAND operation is not associative, and

we have difficulty dealing with non-associative mathematics!

Chapter 2 - Part 3

66

NOR Gate

! The basic NOR gate has the following symbol,

illustrated for three inputs:

OR-Invert (NOR)

X

Y

Z

F(X, Y, Z) = X +Y+ Z

with a NOT applied. The symbol shown is an

OR-Invert. The small circle ( bubble )

represents the invert function.

Chapter 2 - Part 3

67

! Applying DeMorgan's Law gives Invert-AND

(NOR)

X

Y

Z

inputs are inverted and then ANDed together.

! OR-Invert and Invert-AND both represent the

NOR gate. Having both makes visualization of

circuit function easier.

! A NOR gate with one input degenerates to an

inverter.

Chapter 2 - Part 3

68

! The NOR gate is a natural implementation for some

technologies other than CMOS in terms of chip area

and speed.

! The NOR gate is a universal gate

! NOR usually does not have a defined operation

symbol since

the NOR operation is not associative, and

we have difficulty dealing with non-associative

mathematics!

Chapter 2 - Part 3

69

! The eXclusive OR (XOR) function is an important

Boolean function used extensively in logic circuits.

! The XOR function may be;

implemented directly as an electronic circuit (truly a gate) or

implemented by interconnecting other gate types (used as a

convenient representation)

XOR function

! By our definition, XOR and XNOR gates are complex

gates.

Chapter 2 - Part 3

70

!

Adders/subtractors/multipliers

Counters/incrementers/decrementers

Parity generators/checkers

! Definitions

The XOR function is: X Y = X Y + X Y

The eXclusive NOR (XNOR) function, otherwise

known as equivalence is: X Y = X Y + X Y

exist for more that two inputs. Instead, they are

replaced by odd and even functions.

Chapter 2 - Part 3

71

! Operator Rules: XOR

XNOR

Y XY

0

0

1

1

0

1

0

1

0

0

1

1

0

1

1

0

Y (XY)

or X Y

0

1

1

0

0

0

1

1

X OR Y, but NOT BOTH

! Why is the XNOR function also known as the

equivalence function, denoted by the operator ?

Chapter 2 - Part 3

72

XOR/XNOR (Continued)

! The XOR function can be extended to 3 or more variables.

For more than 2 variables, it is called an odd function or

modulo 2 sum (Mod 2 sum), not an XOR:

! The complement of the odd function is the even function.

! The XOR identities:

X0 = X

X 1 = X

XX =0

XX =1

XY = YX

( X Y) Z = X ( Y Z ) = X Y Z

Chapter 2 - Part 3

73

! XOR symbol:

! XNOR symbol:

Chapter 2 - Part 3

74

XOR Implementations

! The simple SOP implementation uses the

following structure: X

X Y

X

X Y

Y

Chapter 2 - Part 3

75

Chapter 2 - Part 2

76

! The odd and even functions on a K-map form

checkerboard patterns.

! The 1s of an odd function correspond to minterms

having an index with an odd number of 1s.

! The 1s of an even function correspond to minterms

having an index with an even number of 1s.

! Implementation of odd and even functions for greater

than four variables as a two-level circuit is difficult, so

we use trees made up of :

2-input XOR or XNORs

3- or 4-input odd or even functions

Chapter 2 - Part 3

77

! Design a 3-input odd function F = X + Y + Z

with 2-input XOR gates

! Factoring, F = (X + Y) + Z

! The circuit:

X

Y

Z

Chapter 2 - Part 3

78

! Design a 4-input odd function F = W + X + Y + Z

with 2-input XOR and XNOR gates

! Factoring, F = (W + X) + (Y + Z)

! The circuit:

W

X

Y

Z

Chapter 2 - Part 3

79

! In Chapter 1, a parity bit added to n-bit code to produce an n

+ 1 bit code:

Add odd parity bit to generate code words with even parity

Add even parity bit to generate code words with odd parity

Use odd parity circuit to check code words with even parity

Use even parity circuit to check code words with odd parity

X

parity code words of length four

Y

with odd parity generator:

Z

! Check even parity code words of

X

length four with odd parity checker: Y

! Operation: (X,Y,Z) = (0,0,1) gives

Z

(X,Y,Z,P) = (0,0,1,1) and E = 0.

P

If Y changes from 0 to 1 between

generator and checker, then E = 1 indicates an error.

Chapter 2 - Part 3

80

Hi-Impedance Outputs

! Logic gates introduced thus far

have 1 and 0 output values,

cannot have their outputs connected together, and

transmit signals on connections in only one direction.

! Three-state logic adds a third logic value, HiImpedance (Hi-Z), giving three states: 0, 1, and Hi-Z

on the outputs.

! The presence of a Hi-Z state makes a gate output as

described above behave quite differently:

1 and 0 become 1, 0, and Hi-Z

cannot becomes can, and

only one becomes two

Chapter 2 - Part 3

81

! What is a Hi-Z value?

This means that, looking back into the circuit, the output

appears to be disconnected.

It is as if a switch between the internal circuitry and the

output has been opened.

restrict gates to a 3-state buffer

each of which has one data input and one control

input.

Chapter 2 - Part 3

82

! For the symbol and truth table, IN

Symbol

is the data input, and EN, the

control input.

IN

OUT

! For EN = 0, regardless of the

value on IN (denoted by X), the

EN

output value is Hi-Z.

Truth Table

! For EN = 1, the output value

follows the input value.

EN IN OUT

! Variations:

0

X

Hi-Z

Data input, IN, can be inverted

Control input, EN, can be inverted

1

0

0

by addition of bubbles to signals.

1

1

1

Chapter 2 - Part 3

83

! Connection of two 3-state buffer

outputs, B1 and B0, to a wire, OUT

! Assumption: Buffer data inputs can

take on any combination of values 0

and 1

! Resulting Rule: At least one buffer

output value must be Hi-Z. Why?

! How many valid buffer output

combinations exist?

! What is the rule for n 3-state buffers

connected to wire, OUT?

! How many valid buffer output

combinations exist?

Resolution Table

B1

B0

OUT

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Chapter 2 - Part 3

84

! Data Selection Function: If s = 0, OL = IN0, else OL = IN1

! Performing data selection with 3-state buffers:

EN0

IN0

EN1

IN1

OL

0

0

1

X

X

0

1

1

0

0

1

X

0

1

0

1

0

1

X

0

0

X

X

1

X

IN0

S

EN0

OL

IN1

EN1

always Hi-Z plus the last row of the table never occurs.

Chapter 2 - Part 3

85

Chapter 2 - Part 2

86

! The remaining complex gates are SOP or

POS structures with and without an output

inverter.

! The names are derived using:

A - AND

O - OR

I - Inverter

Numbers of inputs on first-level gates or

directly to second-level gates

Chapter 2 - Part 3

87

! Example: AOI - AND-OR-Invert consists of a

single gate with AND functions driving an OR

function which is inverted.

! Example: 2-2-1 AO has two 2-input ANDS

driving an OR with one additional OR input

! These gate types are used because:

the number of transistors needed is fewer than required

by connecting together primitive gates

potentially, the circuit delay is smaller, increasing the

circuit operating speed

Chapter 2 - Part 3

88

Chapter 2 - Part 2

89

Terms of Use

! All (or portions) of this material 2008 by Pearson

Education, Inc.

! Permission is given to incorporate this material or

adaptations thereof into classroom presentations and

handouts to instructors in courses adopting the latest

edition of Logic and Computer Design Fundamentals

as the course textbook.

! These materials or adaptations thereof are not to be

sold or otherwise offered for consideration.

! This Terms of Use slide or page is to be included within

the original materials or any adaptations thereof.

Chapter 2 - Part 2

90

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